This implements and enforces the full set of rules for determining
timescales in SystemVerilog. The previous relaxation of the rules
that allowed timescales to be redefined within the compilation unit
scope has been removed. Time unit and precision redeclarations are
now recognised after a nested module declaration.
(* my_fancy_attribute *)
foobar1 foobar (clk(clk), rst(rst) ...);
- Modifies PGModule to hold the attribute map (can be verified with pform_dump)
- pform_make_modgate(s) bind the attributes from the parser to the above map
- The attributes from PGModule are inserted into the NetScope of that module
PGModule::elaborate_scope_mod_instances_
- Currently these attributes automatically make it into netlist
- These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val
from ivl_target.h
Replace explicit comparisons against generation_flag with calls to
the gn_system_verilog helper function, both for code clarity and
to fix a couple of bugs. Also simplify the implementation of the
function, as we already rely on the generation_flag enumeration
being an ordered list.
This just enables the compiler to parse path declarations that
contain part selects. As for bit selects, the part select is
discarded, and if elaboration of specify blocks is enabled,
the path declaration will be applied to the entire vector. If
elaboration is enabled, a warning message will now be output
when a bit or part select is discarded.
If a static variable declared in a task, function, or block has an
initialisation expression, SystemVerilog requires the declaration to
have an explicit static lifetime. This is supposed to be a compile
error, but for now just output a warning.
Implementing this required adding support in the parser for explicit
lifetimes in variable declarations. For now, just output an error if
the user asks for a lifetime that isn't the default for that scope.
This is syntax permitted in 1364-2001 but removed in 1364-2005.
Also update the iverilog man page to document the anachronisms warning
class that warns about use of this feature when a later generation is
selected.
The compiler was emitting a "sorry" message and aborting compilation when
it encountered attributes on a wire declaration/assignment. Change this
to a warning, as most attributes are ignored anyway.
Get rid of the data_type, signed_flag, and range arguments to the
pform_module_define_port because they add no value within the
parse.y parser. Cleaning these out will hopefully ease the addition
of new functionality.
This can be handled entirely in the parser, where we rewrite the
syntax to me a begin/end block that contains the index variable
declaration and the for loop.
The verinum arithmetic operators now observe the standard Verilog
rules for calculating the result width if all operands are sized.
If any operand is unsized, the result is lossless, as before.
They also now all observe the standard rules for handling partially
undefined operands (if any operand bit is 'x', the entire result is
'x').
I've also added the unary '-' operator, and renamed v_not() to be
the unary '~' operator. This has allowed some simplification in
other parts of the compiler.
This implementation works by detecting assignments
to constant properties in elaboration. Allow initializer
assignments to assign to the constant, error all other
assignments, and otherwise treat the constant like any
other property.
Class constructors are the "new" method in a class description.
Elaborate the constructor as an ordinary method, but the only
way to access this method is to implicitly call it. The elaborator
will take the constructor call and generate a naked "new" expression
and implicit constructor method call with the object itself as the
return value.
Rework lexical support for PACKAGE_IDENTIFIER so that the lexor
can help with package scoped identifiers.
Pform package types and package functions up to elaboration.
This patch adds support for bool/bit vector types on the LHS of
a parameter declaration and ensures implicit casts in parameter
declarations are performed where necessary.
A package can have parameters, but it does not have specparams or
keep the order the parameters are defined. This patch skips these
items if the scope is not a Module.
This was temporarily implemented to just copy definitions to the
local scope, but the better method is to create a PEIdent that has
the package attached to it.
The parser does not distinguish between module and UDP instances, so
a UDP delay is handled by the rules used for parsing module parameter
overrides. Although these rules had been relaxed to accept the case of
a simple decimal value (e.g. #10), they did not allow a simple real
value (e.g. #0.1).
Implement through the ivl core to the ivl_target.h API.
Also draft implementation of creating and storing arrays
in the vvp runtime and code generator.
In vvp, create the .var/str variable for representing strings, and
handle strings in the $display system task.
Add to vvp threads the concept of a stack of strings. This is going to
be how complex objects are to me handled in the future: forth-like
operation stacks. Also add the first two instructions to minimally get
strings to work.
In the parser, handle the variable declaration and make it available
to the ivl_target.h code generator. The vvp code generator can use this
information to generate the code for new vvp support.
The parser had been changed to support null statements in sequential
and parallel blocks (a feature introduced in SystemVerilog), but was
not supported in elaboration, leading to a compiler crash. This patch
fixes this by discarding the null statements during parsing.
Making the scope type NESTED_MODULE was just plain wrong, because
it didn't really encapsulate the meaning of program blocks OR
nested modules. So instead create nested_module() and program_block()
flags and use those to test scope constraints.
An important advantage of program blocks is its ability to nest
within a module. This winds up also allowing modules to nest, which
is legal but presumably less used feature.
This patch extends the compiler to support all specparam declarations
allowed by the 1364-2005 standard. For compatibility with other
simulators, it allows specparam values to be used in any constant
expression, but outputs a warning message and disables run-time
annotation of a specparam if it is used in an expression that must
be evaluated at compile time.
This is a cleanup in preparation for better support of range lists.
(cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68)
Conflicts:
PTask.h
elab_scope.cc
elab_sig.cc
parse.y
pform.cc
pform.h
pform_types.h
Signed-off-by: Stephen Williams <steve@icarus.com>
The SystemVerilog unbased literals (e.g. '0, '1, etc.) are expected to be
used standalone and cannot take a size. This patch modifies the parsing
code to give a good error message when this is done.
Class methods belong in a class scope, not the containing module.
So create a lexical scope that carries tasks and functions and
create a PClass to represent classes.
Tasks call arguments may be dropped in favor of default values.
Allow for that in the syntax. This requires a little handling
of the non-SystemVerilog case during elaboration.
Class names can be declared early, before definitions, so that the
name can be used as a type name. This thus allows class definitions
to be separate from the declaration. This creates some complexity in
the parser, since the lexor knows about the class names.
This adds the vector_type_t and real_type_t types to handle
vector and real types in tf_port items. This cleans up a lot
of the parsing for these items.
During parse/pform processing, convert increment statements to
the equivalent compressed assignment statement. This is less weird
for elaboration processing and better expresses what is going on.
This gets me to the point where the parser stashes a defined type,
and the lexical analyzer uses the type names to differentiate
IDENTIFIER and TYPE_IDENTIFIER.
Parse typedefs with structs and enums, but give a sorry message,
because they are not yet supported. Rearrange some of the parse
rules for variables in order to increase comonality with the
typedef rules.
The standard allows a parameter (or localparam) declaration of the
form "parameter signed my_param = ...". The parser currently rejects
this. A small adjustment is also required in the parameter evaluation
code to correctly apply the type.
This patch adds wreal support when in Verilog-AMS mode. It doesn't add
everything that is shown in the Verilog-A standard.
It adds the following:
Declaring a wreal net.
Declaring a wreal net with an initialization.
Declaring a wreal input/output using ANSI syntax.
Declaring a wreal input/output using the old style.
Declaring wreal inout ports are also allowed and parsed, but the
compiler does not know how to handle this. There are other deviations
from what is shown in the Verilog-A standard, but this should get most
of the syntax people actually use.
It is legal for a named block to contain variable definitions and
no statements. This patch fixes this for both style of blocks. It
also organizes the block parsing code to be a bit more clear, adds
an error case for fork/join and changes on check for size() > 0 for
the more efficient ! empty().
This patch fixes a few more bugs in the enumeration code.
It add support for saving the file and line information to make
diagnostic messages better.
It updates some of the compiler warning messages to use the file
and line information.
It passes if the enumeration type is signed all the way to the
code generators.
It fixes the parser to correctly have the range after the signed
designation for the vector types.
It adds a warning that vvp does not currently support a negative
two state enumeration value.
Add a new IVL_PR_FINAL process type.
Add a flag to NetScope in_final_ which is set when elaborating the
statement of a final procedure.
Add checks during statement elaboration for invalid statements in a
final procedure, similar to checks for statements in functions.
Do a final check to make sure no final blocks have delays.
In the vvp runtime, use "$final" as the flag for the thread created by
the final procedure. During compilation, instead of adding such a
thread to the sched_list, add it to a new schedule_final_list that
mirrors the schedule_init_list, but is run at the end of simulation.
This patch adds support for increment/decrement operators as an
expression. The operations on real and vector slices have been
disabled for now.
These operators can be used as in independent statements. However, the
corresponding support is not added in parser.
Changes since V2:
- Additional error checking in elaboration to deny operation on vector
slices and real (suggested by Martin)
Changes since V1:
- Use 'i' and 'I' for increment (suggested by Cary)
- Evaluate sub-expression once (suggested by Cary and Stev)
- Add necessary checks during elaboration to ensure that the
expression is valid (suggested Stev)
- Proper width handling with vectors (suggested by Martin)
Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
This patch adds code to check for a negative or undefined value used in
an enumeration sequence name, it verifies that the count in an enumeration
sequence name is not zero and allows more decimal constant values in the
enumeration sequence name..
SystemVerilog extended the assignments operator support to C-like
assignment operators and special bitwise assignment operators.
For example:
a += 1;
a -= 1;
The list of these operators can be found in SV LRM (1800-2009)
section 11.4.1.
NOTE: I fixed a few parts of this. In particular, the PEBShift
class is used for shift operators.
Acked-and-Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
pow(int, int) is ambiguous since it could use the double version from
the math library or the verinum version. This patch makes it obvious that
we want to use the double version.
SystemVerilog has support for time literals. The time literal for
example #10ns, adds a delay of 10ns no matter the time unit currently
in effect. For more details please refer to
http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals
Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
A bit/logic output type in a module initially is defaulted to as a
variable. Depending on how they are used in the module, the type
changes accordingly.
For example
module test(output logic l);
assign l = '0;
endmodule
The variable 'l' would be promoted to a Net data type, when the
'assign' statement is encountered.
Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
The module declaration should allow initialization of the bit and
logic data types.
For example:
$ cat clkgen.sv
module clkgen(output logic clk = 0, output bit p = 1);
initial begin
#200;
$display("p = %b", p);
$finish;
end
initial forever #10 clk = ~clk;
endmodule
$ iverilog -g 2009 clkgen.sv
$ ./a.out
p = 1
Suggested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
SystemVerilog allows passing the 'bit' and 'logic' arguments to a
function. The patch adds support for parsing these function
definitions. The 'bit' data type is treated as boolean, whereas 'logic'
data type remains as logic.
Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
The patch allows parsing of function definitions which do not have
explicit data type or range. The default return data type is assumed
to be reg unsigned and the default range is 0.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows returning variables of 'reg' type. The icarus verilog
implicitly assumes the default returned type of the function as
'reg unsigned'. The patch allows to explicitly specify the 'reg' return
type.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'logic'. The data type
'logic' is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'bit'. The data type 'bit'
is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
If there are attributes attached to a module port declaration them
pform_bind_attribute() which is called from pform_module_define_port()
will delete the attribute list. They do not need to be deleted locally.
IEEE 1800-2005/9 says "each fixed-size dimension shall be represented by
an address range, such as [1:1024], or a single positive number to
specify the size of a fixed-size unpacked array, as in C. In other
words, [size] becomes the same as [0:size-1]."
This patch implements that translation in the parser. It issues a
warning when doing so when the generation flag is less than 2005-sv.
This patch adds/fixes the following:
Adds file/line information to a UDP definition.
Prints an error message if a UDP is passed signals wider than 1 bit.
A UDP should supports a range, but the compiler currently does not.
Add scope information for constants.
Fix the Icarus extension UDP table entry element 'h' to use h.
The ivl_udp_init() value is a char not unsigned.
Add FILE_NAME() for a bunch more of the ivl interface objects.
In the standard a pull device can be given both a 1 and 0 strength.
Only the appropriate one is actually used. This patch adds support
for giving both pull strength to a pull device.
This patch fixes the following problem in the compiler:
An integer task argument should be marked as an integer port.
An implicit register can be converted to either a reg or an integer.
An old style task port should default to <no type> unless reg or some
other type is provided. ANSI style is always defined. For example:
input ri;
output ro;
inout rio;
real ri, ro, rio;
should define all three task ports to be of type real.
It was a poor choice to only add -g2009 for 1800-2009 and ignore the
previous version of System Verilog 1800-2005. This patch adds a
generation for 1800-2005 and also adds `begin_keywords support for
1800-2005. The previous SystemVerilog keywords have been put under
the 1800-2005 generation and the new one from 1800-2009 have also
been added.
Cadence allows an ifnone with an edge-sensitive path. Until we understand
exactly what this is and how to implement it this patch adds a warning
that an ifnone with an edge-sensitive path is not supported.
This patch changes all the iterator code to use a prefix ++ instead
of postfix since it is more efficient (no need for a temporary). It
is likely that the compiler could optimize this away, but lets make
it efficient from the start.
I'm adding more uses of the make_range_from_width function, so
it seems like time to get rid of its use of the svector template.
This thread led to a lot of other uses of svector that had to
also be removed.
SystemVerilog allows variables to be either variables or unresolved
nets, depending on how they are used. If they are assigned by
procedural code, then they are variables. If they are assigned
by a continuous assignment, they are unresolved nets. Note that
they cannot be both, and when they are unresolved nets they can
only be assigned once.
The error routines for task and function definitions were incorrectly
popping the scope. This should not be done since no scope was pushed.
Also assert that the current_task/function is 0 to catch that kind of
error like the other definition rules.
Generate schemes may nest freely, but generate regions
(an anachronistic concept from 1364-2001) cannot nest,
not within schemes or other regions. Have the parser detect
the nesting and print an error message.
This is part of the 1800-2009 standard (Section 23.3.2.3) and allows
ports of module instances to be declared like:
modname instance(.foo, .bar);
instead of
modname instead(.foo(foo), .bar(bar));
The only tricky part about this is the implicit port connection shall
not create an implicit net declaration. To make this happen, the path
of least resistance was to add a bool to PEIdent indicating that it
should not implicitely create a net.
This does not rely on the generation flag to be 2009, following the
trend that new port naming convention (like ANSI style ports) work
regardless of the generation.
Added generation flag -g2009 which enables support for 1800-2009
constructs. Added related support such as "1800-2009" in the
`begin_keywords directive.
Keeps 2005 as the default generation for now.
Removed the -gsytem-verilog flag and folded the 1800-2005 stuff into
1800-2009. The rationale behind this is we have so little of
1800-2005 actually implemented that it does not make sense to
distinguish between 1800-2005 and 1800-2009 SystemVerilog extensions,
so we just count them all as the new 1800-2009 Verilog language.
Like I did for SystemVerilog the other day this patch adds all the
Verilog-AMS 2.3.1 keywords. This necessitated adding one my byte
to the gperf -k argument (byte 9) to make the laplace_?? tokens
have a unique hash.
This patch adds the SystemVerilog keywords to Icarus. This allows
use to easily verify that out plain Verilog does not contain any
SystemVerilog keywords. The keywords are not parsed in any way.
When parsing a Verilog file using -gsystem-verilog any identifier
that is a keyword will cause a parse error. It is the users
responsibility to figure out the problem since bison does not
give nice error message when it finds a keyword instead of an
identifier.
The $setuphold and $recrem timing checks can create delayed signals
that are needed to get a model to work correctly when negative timing
check values are used. Since we do not support timing checks and just
ignore them this can create simulation problems when a user tries to
use these delayed signals since they are not driven.
This patch adds a waring when the circuit is being compiled that these
delayed signals will not be driven. This will be needed until we get
time to add the real timing checks are mimic the delayed properties of
the timing check.
This patch modifies the original SystemVerilog timeunit/timeprecision
patch in the following way:
Removed trailing space.
Reworked some code to use standard spacing rules.
Added some comments.
Combined some code.
Major rework of local/global timeunit/timeprecision logic.
Major rework of timeunit/timeprecision declaration/check code.
This was needed to remove the shift/reduce warnings.
Add a number of checks for invalid combinations.
Martin Whitaker
Vamsi Vytla
Stephen Williams
Henry Wong
Cary R
Maciej Suminski
Martin Whitaker
Larry Doolittle
Todd Strader (todd.strader@gmail.com)
Arun Persaud
Jared Casper
Prasad Joshi
Prasad Joshi
Sreeraj R