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be6b2a3b8d
Merge pull request #37 from AngeloJacobo/dev_max_freq
2026-01-18 12:25:34 +0800
e22c2b1c53
fix whitespaces
2026-01-18 12:17:36 +0800
2226aa4461
Step 7: Resize registers
2026-01-18 12:01:58 +0800
859963ad20
Step 6: Optimize wb_stall logic
2026-01-18 11:55:31 +0800
5066c3d280
Step 5: Optimize stage-1 stall and stage-2 stall logic
2026-01-18 11:40:26 +0800
f724ec0d43
Step 4: Arrange logic (stage-2 pre/act/wr-rd logic)
2026-01-18 11:25:47 +0800
fad0a7b19a
Step 3: Register conditions in advance (calibration fsm)
2026-01-18 11:19:04 +0800
282d9596ca
Step 2: Register conditions in advance (2-stage pipeline)
2026-01-18 11:06:49 +0800
98fe547262
Step 1: Separate _q (sequential) from _d (combinational) logic
2026-01-18 10:52:57 +0800
a653bbeb35
revert ddr3_controller to commit a1258e2
2026-01-18 10:19:05 +0800
b46b2ca06d
Merge pull request #36 from AngeloJacobo/dev_max_freq
2026-01-11 13:34:08 +0800
30731d1b4c
add files for caas and linked uberddr3 files
2026-01-11 13:30:06 +0800
df67fc038b
add files for caas and linked uberddr3 files
2026-01-11 12:03:03 +0800
31b3642fbe
run @ 133MHz with yosys
2025-12-31 14:40:04 +0800
ad50f79695
run @ 100MHz with yosys
2025-12-31 14:39:16 +0800
407c1a8115
update dfu file
2025-12-31 14:38:32 +0800
383e53d647
run @ 125MHz with yosys
2025-12-31 14:38:13 +0800
b38d9801ba
run @ 100MHz with yosys
2025-12-31 14:37:32 +0800
3c4c4b9f83
optimize stage1/2 stall logic, optimize size of registers (delay_before_*, added_read_pipe*, delay_read_pipe), register huge conditions, explicit removal of unused states)
2025-12-31 14:35:04 +0800
3d94fae1e6
separated sequential from combinational logic for pipeline stage logic
2025-12-29 14:36:25 +0800
a3ffeb670f
register conditions for anticipate logic; change logic order for stage 2 from r/w-act-pre to pre-act-r/w
2025-12-29 10:26:32 +0800
0b3bb30fae
added define for UART-debugging of BIST exclusively
2025-12-27 13:01:19 +0800
356c6cc1a2
run at DDR3-1000 (125MHz controller clock)
2025-12-26 10:02:16 +0800
80da754a64
achieve >40% increase in max frequency
2025-12-26 09:50:12 +0800
864b8069c3
fix read_data_store_lane logic
2025-12-23 10:01:57 +0800
a3edea5e00
add prep state for ANALYZE_DATA to cut timing path due to indexing with lane
2025-12-22 13:11:20 +0800
c605135dd9
make o_wb_stall/o_wb_stall_calib combinational logic
2025-12-22 08:50:40 +0800
fdf1becc03
register stage2 if-else conditions (2.4% increase in max freq)
2025-12-19 17:39:03 +0800
ba640ca59c
optimize wb_stall/wb_stall_calib logic (3.7% increase in max freq)
2025-12-14 11:53:04 +0800
a1258e2eed
added back main wcfg file
2025-06-14 11:52:13 +0800
a3efc861da
update bistream files from latest CI run
2025-06-05 18:55:44 +0800
9c3249b8dd
log files are renamed with PASS_ for easier checking
2025-06-03 19:26:05 +0800
db8e0fd400
test GoCD CI with this new commit
2025-05-28 19:44:40 +0800
426a4e626b
revert back current_design (test gocd)
2025-05-25 13:15:13 +0800
e2b0829b74
removed iodelay group string (test gocd)
2025-05-25 13:14:43 +0800
76815bac35
remove current_design on xdc (not supported in openxc7)
2025-05-25 12:54:02 +0800
4d60a19154
Merge pull request #32 from AngeloJacobo/run_iverilog_sim
2025-05-25 09:12:59 +0800
da4ffebe9b
update vivado sim log files
2025-05-25 09:03:28 +0800
e5bd0d74c3
use SIM_MODEL directive to use models during vivado simulation
2025-05-25 09:03:16 +0800
a33560122c
added icarus simulation scripts (PASSING!)
2025-05-24 17:35:39 +0800
cb5f78b057
modified vivado simulation files
2025-05-24 17:33:49 +0800
972506bb4b
moved verilog models to model/
2025-05-24 17:31:55 +0800
8fbb6387ab
removed UART in example demo for arty s7 to pass openxc7 timing
2025-05-24 17:31:13 +0800
f0b4a15b7c
icarus verilog simulation now working!
2025-05-18 17:08:38 +0800
4be9a30ff8
added files needed for icarus simulation (not yet working)
2025-05-18 15:24:10 +0800
4b159fa03a
Merge pull request #31 from AngeloJacobo/pass_verilator_lint
2025-05-12 18:35:28 +0800
157cca28d8
fixed late_dq logic
2025-05-12 18:27:57 +0800
90647a70e0
resolved (again) the verilator lint
2025-05-12 16:28:07 +0800
5f8f5974b4
added vivado on makefile (make vivado)
2025-05-12 16:02:38 +0800
fe8563ed65
update all simulation log files
2025-05-12 11:05:36 +0800
9fd104b566
updated example demo bitstream files
2025-05-11 20:11:05 +0800
50c0a6488d
verilator now passing lint even with older verilator version
2025-05-11 20:02:13 +0800
264801fc99
Merge pull request #30 from AngeloJacobo/ecp5_phy
2025-04-19 14:57:57 +0800
5b0c48ca0a
fixed bug on vivado IP (convert string to long for SELF_REFRESH)
2025-04-19 13:59:30 +0800
c7ec0a54fc
set default BIST_MODE to 1 for shorter bring up
2025-04-19 13:37:58 +0800
73431cdd82
added simulation for DLL Off (low frequency ddr3 clk)
2025-04-19 13:32:07 +0800
baaa2a2482
added example demo for orangecrab ecp5
2025-04-19 13:30:40 +0800
b990372663
added support for DLL_OFF and Lattice ECP5 PHY
2025-04-19 13:24:20 +0800
08ead41fd6
updated simulation
2025-04-19 10:07:51 +0800
a34a5369ec
Merge pull request #26 from AngeloJacobo/openxc7_run
2025-03-21 20:33:19 +0800
8c088fee72
Merge branch 'main' into openxc7_run
2025-03-21 20:32:51 +0800
b02e66b7d8
revert changes in shiftin and iodelay_group string name since openxc7 now works on them
2025-03-16 12:29:48 +0800
0175db1ca6
openFPGAloader now working on qmtech_wukong
2025-03-14 16:12:25 +0800
58f887ced3
openfpgaloader now works on qmtech_kintex7
2025-03-14 16:03:18 +0800
5ab1ac5d42
add UART to ax7325b board, make openFPGAloader works on ax7325b board
2025-03-14 15:23:34 +0800
75e42476f5
openfpgaloader now working on alinx ax7103b board
2025-03-14 14:34:25 +0800
117a9c5837
update enclustra demo project
2025-03-14 13:56:24 +0800
d787c77116
pass simulation
2025-03-13 18:31:23 +0800
47067f6903
remove xadc define and uncomment INTERNAL_VREF to make this work in openxc7 (openxc7 still fails due to shiftout ports)
2025-03-09 10:57:43 +0800
89568b127c
add demo project for qmtech kintex-7 board
2025-03-09 10:41:33 +0800
42b42023dd
Update README.md
2025-03-09 10:13:07 +0800
7f801b1f1d
add uart_tx to top
2025-03-02 19:05:30 +0800
c0bc4ca48a
removed extra semicolon
2025-03-02 18:46:07 +0800
4ce06f5fd8
all example demos passing openxc7 run!
2025-03-02 18:42:49 +0800
e8444fb379
fix flagged errors from openxc7 (shiftin grounded, iodelay_group string)
2025-03-02 18:40:18 +0800
0c484d54f6
fix flagged errors from openxc7
2025-03-02 14:34:59 +0800
94b4e0866b
added UART for debugging, DQ now support 1 cycle late
2025-03-02 14:15:44 +0800
5c52351bce
uncommented default_nettype
2025-03-01 19:32:35 +0800
e19c6023c4
remove wb2 related logic when SECOND_WISHBONE == 0 to pass DDR3-1600 timing
2025-03-01 15:51:48 +0800
4a71002cf8
ignore new fiels due to new verilator, run_compile can now run lint separately
2025-03-01 14:42:05 +0800
99eaa7d103
added IODELAY_GROUP for ODELAY,IDELAY,and IDELAYCTRL
2025-03-01 14:41:00 +0800
74f68760a4
removed mark_debug
2025-03-01 14:40:21 +0800
f10fc7d10b
vivado simulation files directory are now relative, can now run sim anywhere
2025-03-01 14:39:54 +0800
af48f1fa08
solve timing slack due to 64-bit counters
2025-02-27 20:28:55 +0800
c0e3f32bfb
Merge pull request #22 from AngeloJacobo/higher_speed_feature
2025-02-22 11:32:19 +0800
3898b1e762
Merge branch 'main' into higher_speed_feature
2025-02-22 11:31:54 +0800
1db41ad9e1
add xdc for microblaze run, and minor fixes in params
2025-02-22 11:23:24 +0800
d6f50b3a6a
update UberDDR3 AXI for Vivado custom IP
2025-02-16 14:53:05 +0800
48fd64588b
update to ddr3-1333
2025-02-13 19:32:19 +0800
c21b8a0a37
uberddr3 test on enclustra board, with MicroBlaze for summary reporting via UART
2025-02-13 19:27:11 +0800
d4ecfee105
improve latency of ack after write
2025-02-09 16:16:42 +0800
97424583ba
formal all passing
2025-02-09 09:52:29 +0800
7ada4bcbab
add support for BIST_MODE = 0,1,and 2 , write data is also randomized
2025-02-09 09:48:46 +0800
058da90bfc
changed SKIP_INTERNAL_TEST to BIST_MODE (0,1, or 2)
2025-02-09 09:45:30 +0800
016df010c7
added regression test shell scrip to simulate multiple corners
2025-01-30 19:16:11 +0800
c81f9044d8
add activate-to-activate delay, calibrate-able for both late-write-dq and early-read-dq, simulation passing for ddr3-1600!
2025-01-30 19:07:09 +0800
760979db27
hardware runs on ddr3-1333! Now working on ddr3-1600
2025-01-19 17:15:40 +0800
faa94a839a
Merge pull request #21 from AngeloJacobo/uberddr3_with_xadc
2025-01-18 14:15:10 +0800
339adfe8d6
added simulation and project demo with XADC
2025-01-12 14:55:43 +0800
ae3cb666e6
Merge pull request #20 from AngeloJacobo/spd_reader
2025-01-11 14:18:26 +0800
Angelo Jacobo