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Add YPCB-00338-1P1 DDR3 example

This commit is contained in:
Roland Coeurjoly 2026-05-11 09:46:58 +02:00
parent be6b2a3b8d
commit bbb08811ac
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# YPCB-00338-1P1 DDR3 example
This board is an XC7K480T-FFG1156 design with two DDR3 channels. The example in
`example_demo/ypcb_00338_1p1` targets DDR3 channel 0 with a 64-bit data bus and
uses UberDDR3's built-in BIST. The three user LEDs report:
- LED 0: PLL locked.
- LED 1: DDR3 calibration complete.
- LED 2: heartbeat after calibration.
The example uses the board's 50 MHz clock and generates a low-rate 25 MHz
controller clock, 100 MHz DDR3 clock, 100 MHz 90-degree DDR3 clock, and 200 MHz
reference clock. The low-rate configuration is intended as a bring-up target for
open-source flows.
Build with OpenXC7:
```sh
cd example_demo/ypcb_00338_1p1
make openxc7
```
Program with:
```sh
make program
```
The pin constraints are derived from the LiteX-Boards `ypcb_00338_1p1.py`
platform definition.

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example_demo/ypcb_00338_1p1/Makefile Normal file
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PROJECT = ypcb_00338_1p1_ddr3
FAMILY = kintex7
PART = xc7k480tffg1156-2
CHIPDB = ${KINTEX7_CHIPDB}
ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v ../../rtl/ddr3_phy.v ../../rtl/ddr3_top.v clk_wiz_ypcb.v
NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
PRJXRAY_DB_DIR ?= ${NEXTPNR_XILINX_DIR}/external/prjxray-db
DBPART = $(shell echo ${PART} | sed -e 's/-[0-9]//g')
SPEEDGRADE = $(shell echo ${PART} | sed -e 's/.*\-\([0-9]\)/\1/g')
CHIPDB ?= ./
ifeq ($(CHIPDB),)
CHIPDB = ./
endif
PYPY3 ?= pypy3
TOP ?= ${PROJECT}
TOP_MODULE ?= ${TOP}
TOP_VERILOG ?= ${TOP}.v
PNR_DEBUG ?= # --verbose --debug
PNR_ARGS ?=
JTAG_LINK ?= -c digilent_hs3
XDC ?= ${PROJECT}.xdc
.PHONY: openxc7
openxc7: ${PROJECT}_openxc7.bit
.PHONY: program
program: ${PROJECT}_openxc7.bit
openFPGALoader ${JTAG_LINK} --bitstream $<
${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
yosys -p "synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json" $< ${ADDITIONAL_SOURCES}
${CHIPDB}/${DBPART}.bin:
${PYPY3} ${NEXTPNR_XILINX_PYTHON_DIR}/bbaexport.py --device ${PART} --bba ${DBPART}.bba
bbasm -l ${DBPART}.bba ${CHIPDB}/${DBPART}.bin
rm -f ${DBPART}.bba
${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --json ${PROJECT}.json --fasm $@ ${PNR_ARGS} ${PNR_DEBUG}
${PROJECT}.frames: ${PROJECT}.fasm
fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
${PROJECT}_openxc7.bit: ${PROJECT}.frames
xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
.PHONY: clean
clean:
rm -f *.bit
rm -f *.frames
rm -f *.fasm
rm -f *.json
rm -f *.bin
rm -f *.bba

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example_demo/ypcb_00338_1p1/clk_wiz_ypcb.v Normal file
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`default_nettype none
`timescale 1ps / 1ps
module clk_wiz_ypcb (
input wire clk50,
output wire locked,
output wire controller_clk,
output wire ddr3_clk,
output wire ddr3_clk_90,
output wire ref_clk
);
wire clkfb;
wire clk100_raw;
wire clk100_90_raw;
wire clk25_raw;
wire clk200_raw;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(20),
.CLKFBOUT_PHASE(0.000),
.CLKIN1_PERIOD(20.000),
.CLKOUT0_DIVIDE(10),
.CLKOUT0_DUTY_CYCLE(0.500),
.CLKOUT0_PHASE(0.000),
.CLKOUT1_DIVIDE(10),
.CLKOUT1_DUTY_CYCLE(0.500),
.CLKOUT1_PHASE(90.000),
.CLKOUT2_DIVIDE(40),
.CLKOUT2_DUTY_CYCLE(0.500),
.CLKOUT2_PHASE(0.000),
.CLKOUT3_DIVIDE(5),
.CLKOUT3_DUTY_CYCLE(0.500),
.CLKOUT3_PHASE(0.000),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.STARTUP_WAIT("FALSE")
) pll_inst (
.CLKFBOUT(clkfb),
.CLKOUT0(clk100_raw),
.CLKOUT1(clk100_90_raw),
.CLKOUT2(clk25_raw),
.CLKOUT3(clk200_raw),
.CLKOUT4(),
.CLKOUT5(),
.LOCKED(locked),
.CLKFBIN(clkfb),
.CLKIN1(clk50),
.PWRDWN(1'b0),
.RST(1'b0)
);
BUFG clk100_bufg (
.I(clk100_raw),
.O(ddr3_clk)
);
BUFG clk100_90_bufg (
.I(clk100_90_raw),
.O(ddr3_clk_90)
);
BUFG clk25_bufg (
.I(clk25_raw),
.O(controller_clk)
);
BUFG clk200_bufg (
.I(clk200_raw),
.O(ref_clk)
);
endmodule
`default_nettype wire

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example_demo/ypcb_00338_1p1/ypcb_00338_1p1_ddr3.v Normal file
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`default_nettype none
`timescale 1ps / 1ps
module ypcb_00338_1p1_ddr3 (
input wire clk50,
input wire SYS_RSTN,
output wire [2:0] led_3bits_tri_o,
output wire [14:0] ddram_a,
output wire [2:0] ddram_ba,
output wire ddram_cas_n,
output wire ddram_cke,
output wire ddram_clk_n,
output wire ddram_clk_p,
output wire ddram_cs_n,
inout wire [63:0] ddram_dq,
inout wire [7:0] ddram_dqs_n,
inout wire [7:0] ddram_dqs_p,
output wire ddram_odt,
output wire ddram_ras_n,
output wire ddram_reset_n,
output wire ddram_we_n
);
localparam integer ROW_BITS = 15;
localparam integer COL_BITS = 10;
localparam integer BA_BITS = 3;
localparam integer BYTE_LANES = 8;
localparam integer AUX_WIDTH = 4;
localparam integer WB_ADDR_BITS = ROW_BITS + COL_BITS + BA_BITS - 3;
localparam integer WB_DATA_BITS = 8 * BYTE_LANES * 8;
localparam integer WB_SEL_BITS = WB_DATA_BITS / 8;
wire controller_clk;
wire ddr3_clk;
wire ddr3_clk_90;
wire ref_clk;
wire pll_locked;
wire calib_complete;
wire [31:0] debug1;
wire [0:0] ddr3_clk_p_w;
wire [0:0] ddr3_clk_n_w;
wire [0:0] ddr3_cke_w;
wire [0:0] ddr3_cs_n_w;
wire [0:0] ddr3_odt_w;
wire [BYTE_LANES - 1:0] ddr3_dm_w;
wire uart_tx;
reg [25:0] heartbeat_counter = 26'd0;
clk_wiz_ypcb clk_wiz_inst (
.clk50(clk50),
.locked(pll_locked),
.controller_clk(controller_clk),
.ddr3_clk(ddr3_clk),
.ddr3_clk_90(ddr3_clk_90),
.ref_clk(ref_clk)
);
always @(posedge controller_clk) begin
if (!SYS_RSTN || !pll_locked || !calib_complete) begin
heartbeat_counter <= 26'd0;
end else begin
heartbeat_counter <= heartbeat_counter + 26'd1;
end
end
assign led_3bits_tri_o[0] = pll_locked;
assign led_3bits_tri_o[1] = calib_complete;
assign led_3bits_tri_o[2] = calib_complete && heartbeat_counter[25];
assign ddram_clk_p = ddr3_clk_p_w[0];
assign ddram_clk_n = ddr3_clk_n_w[0];
assign ddram_cke = ddr3_cke_w[0];
assign ddram_cs_n = ddr3_cs_n_w[0];
assign ddram_odt = ddr3_odt_w[0];
ddr3_top #(
.CONTROLLER_CLK_PERIOD(40_000),
.DDR3_CLK_PERIOD(10_000),
.ROW_BITS(ROW_BITS),
.COL_BITS(COL_BITS),
.BA_BITS(BA_BITS),
.BYTE_LANES(BYTE_LANES),
.AUX_WIDTH(AUX_WIDTH),
.WB2_ADDR_BITS(7),
.WB2_DATA_BITS(32),
.DUAL_RANK_DIMM(0),
.SPEED_BIN(0),
.SDRAM_CAPACITY(5),
.TRCD(13_750),
.TRP(13_750),
.TRAS(35_000),
.ODELAY_SUPPORTED(0),
.SECOND_WISHBONE(0),
.DLL_OFF(1),
.WB_ERROR(0),
.BIST_MODE(1),
.ECC_ENABLE(0)
) ddr3_top_inst (
.i_controller_clk(controller_clk),
.i_ddr3_clk(ddr3_clk),
.i_ref_clk(ref_clk),
.i_ddr3_clk_90(ddr3_clk_90),
.i_rst_n(SYS_RSTN && pll_locked),
.i_wb_cyc(1'b1),
.i_wb_stb(1'b0),
.i_wb_we(1'b0),
.i_wb_addr({WB_ADDR_BITS{1'b0}}),
.i_wb_data({WB_DATA_BITS{1'b0}}),
.i_wb_sel({WB_SEL_BITS{1'b1}}),
.i_aux({AUX_WIDTH{1'b0}}),
.o_wb_stall(),
.o_wb_ack(),
.o_wb_err(),
.o_wb_data(),
.o_aux(),
.i_wb2_cyc(1'b0),
.i_wb2_stb(1'b0),
.i_wb2_we(1'b0),
.i_wb2_addr(7'd0),
.i_wb2_data(32'd0),
.i_wb2_sel(4'd0),
.o_wb2_stall(),
.o_wb2_ack(),
.o_wb2_data(),
.o_ddr3_clk_p(ddr3_clk_p_w),
.o_ddr3_clk_n(ddr3_clk_n_w),
.o_ddr3_reset_n(ddram_reset_n),
.o_ddr3_cke(ddr3_cke_w),
.o_ddr3_cs_n(ddr3_cs_n_w),
.o_ddr3_ras_n(ddram_ras_n),
.o_ddr3_cas_n(ddram_cas_n),
.o_ddr3_we_n(ddram_we_n),
.o_ddr3_addr(ddram_a),
.o_ddr3_ba_addr(ddram_ba),
.io_ddr3_dq(ddram_dq),
.io_ddr3_dqs(ddram_dqs_p),
.io_ddr3_dqs_n(ddram_dqs_n),
.o_ddr3_dm(ddr3_dm_w),
.o_ddr3_odt(ddr3_odt_w),
.o_calib_complete(calib_complete),
.o_debug1(debug1),
.i_user_self_refresh(1'b0),
.uart_tx(uart_tx)
);
wire unused = ^debug1 ^ ^ddr3_dm_w ^ uart_tx;
endmodule
`default_nettype wire

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# YPCB-00338-1P1, DDR3 channel 0.
# Pins are derived from LiteX-Boards ypcb_00338_1p1.py.
set_property LOC AA28 [get_ports {clk50}]
set_property IOSTANDARD LVCMOS18 [get_ports {clk50}]
create_clock -name clk50 -period 20.000 [get_ports clk50]
set_property LOC R28 [get_ports {SYS_RSTN}]
set_property IOSTANDARD LVCMOS18 [get_ports {SYS_RSTN}]
set_property LOC P30 [get_ports {led_3bits_tri_o[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {led_3bits_tri_o[0]}]
set_property LOC M30 [get_ports {led_3bits_tri_o[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {led_3bits_tri_o[1]}]
set_property LOC N30 [get_ports {led_3bits_tri_o[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {led_3bits_tri_o[2]}]
set_property LOC AK27 [get_ports {ddram_a[0]}]
set_property LOC AN23 [get_ports {ddram_a[1]}]
set_property LOC AL24 [get_ports {ddram_a[2]}]
set_property LOC AK26 [get_ports {ddram_a[3]}]
set_property LOC AH24 [get_ports {ddram_a[4]}]
set_property LOC AH25 [get_ports {ddram_a[5]}]
set_property LOC AL26 [get_ports {ddram_a[6]}]
set_property LOC AJ24 [get_ports {ddram_a[7]}]
set_property LOC AJ25 [get_ports {ddram_a[8]}]
set_property LOC AM23 [get_ports {ddram_a[9]}]
set_property LOC AL28 [get_ports {ddram_a[10]}]
set_property LOC AL25 [get_ports {ddram_a[11]}]
set_property LOC AM25 [get_ports {ddram_a[12]}]
set_property LOC AK24 [get_ports {ddram_a[13]}]
set_property LOC AM27 [get_ports {ddram_a[14]}]
set_property SLEW FAST [get_ports {ddram_a[0]}]
set_property SLEW FAST [get_ports {ddram_a[1]}]
set_property SLEW FAST [get_ports {ddram_a[2]}]
set_property SLEW FAST [get_ports {ddram_a[3]}]
set_property SLEW FAST [get_ports {ddram_a[4]}]
set_property SLEW FAST [get_ports {ddram_a[5]}]
set_property SLEW FAST [get_ports {ddram_a[6]}]
set_property SLEW FAST [get_ports {ddram_a[7]}]
set_property SLEW FAST [get_ports {ddram_a[8]}]
set_property SLEW FAST [get_ports {ddram_a[9]}]
set_property SLEW FAST [get_ports {ddram_a[10]}]
set_property SLEW FAST [get_ports {ddram_a[11]}]
set_property SLEW FAST [get_ports {ddram_a[12]}]
set_property SLEW FAST [get_ports {ddram_a[13]}]
set_property SLEW FAST [get_ports {ddram_a[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}]
set_property LOC AM26 [get_ports {ddram_ba[0]}]
set_property LOC AP24 [get_ports {ddram_ba[1]}]
set_property LOC AN28 [get_ports {ddram_ba[2]}]
set_property SLEW FAST [get_ports {ddram_ba[0]}]
set_property SLEW FAST [get_ports {ddram_ba[1]}]
set_property SLEW FAST [get_ports {ddram_ba[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}]
set_property LOC AJ29 [get_ports {ddram_ras_n}]
set_property LOC AP26 [get_ports {ddram_cas_n}]
set_property LOC AN27 [get_ports {ddram_we_n}]
set_property LOC AK28 [get_ports {ddram_cs_n}]
set_property LOC AP27 [get_ports {ddram_cke}]
set_property LOC AK29 [get_ports {ddram_odt}]
set_property LOC AD31 [get_ports {ddram_reset_n}]
set_property SLEW FAST [get_ports {ddram_ras_n}]
set_property SLEW FAST [get_ports {ddram_cas_n}]
set_property SLEW FAST [get_ports {ddram_we_n}]
set_property SLEW FAST [get_ports {ddram_cs_n}]
set_property SLEW FAST [get_ports {ddram_cke}]
set_property SLEW FAST [get_ports {ddram_odt}]
set_property SLEW FAST [get_ports {ddram_reset_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_cs_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_reset_n}]
set_property LOC AG17 [get_ports {ddram_dq[0]}]
set_property LOC AG16 [get_ports {ddram_dq[1]}]
set_property LOC AH17 [get_ports {ddram_dq[2]}]
set_property LOC AJ19 [get_ports {ddram_dq[3]}]
set_property LOC AH18 [get_ports {ddram_dq[4]}]
set_property LOC AH19 [get_ports {ddram_dq[5]}]
set_property LOC AJ16 [get_ports {ddram_dq[6]}]
set_property LOC AJ17 [get_ports {ddram_dq[7]}]
set_property LOC AL20 [get_ports {ddram_dq[8]}]
set_property LOC AN17 [get_ports {ddram_dq[9]}]
set_property LOC AL19 [get_ports {ddram_dq[10]}]
set_property LOC AM16 [get_ports {ddram_dq[11]}]
set_property LOC AL18 [get_ports {ddram_dq[12]}]
set_property LOC AL16 [get_ports {ddram_dq[13]}]
set_property LOC AM20 [get_ports {ddram_dq[14]}]
set_property LOC AN18 [get_ports {ddram_dq[15]}]
set_property LOC AL23 [get_ports {ddram_dq[16]}]
set_property LOC AN20 [get_ports {ddram_dq[17]}]
set_property LOC AK23 [get_ports {ddram_dq[18]}]
set_property LOC AP19 [get_ports {ddram_dq[19]}]
set_property LOC AN22 [get_ports {ddram_dq[20]}]
set_property LOC AN19 [get_ports {ddram_dq[21]}]
set_property LOC AM22 [get_ports {ddram_dq[22]}]
set_property LOC AP20 [get_ports {ddram_dq[23]}]
set_property LOC AJ21 [get_ports {ddram_dq[24]}]
set_property LOC AH22 [get_ports {ddram_dq[25]}]
set_property LOC AK21 [get_ports {ddram_dq[26]}]
set_property LOC AG21 [get_ports {ddram_dq[27]}]
set_property LOC AG22 [get_ports {ddram_dq[28]}]
set_property LOC AG20 [get_ports {ddram_dq[29]}]
set_property LOC AH23 [get_ports {ddram_dq[30]}]
set_property LOC AG23 [get_ports {ddram_dq[31]}]
set_property LOC AJ32 [get_ports {ddram_dq[32]}]
set_property LOC AK32 [get_ports {ddram_dq[33]}]
set_property LOC AK31 [get_ports {ddram_dq[34]}]
set_property LOC AL30 [get_ports {ddram_dq[35]}]
set_property LOC AL34 [get_ports {ddram_dq[36]}]
set_property LOC AL31 [get_ports {ddram_dq[37]}]
set_property LOC AK34 [get_ports {ddram_dq[38]}]
set_property LOC AL29 [get_ports {ddram_dq[39]}]
set_property LOC AJ34 [get_ports {ddram_dq[40]}]
set_property LOC AH32 [get_ports {ddram_dq[41]}]
set_property LOC AJ30 [get_ports {ddram_dq[42]}]
set_property LOC AH34 [get_ports {ddram_dq[43]}]
set_property LOC AF31 [get_ports {ddram_dq[44]}]
set_property LOC AG30 [get_ports {ddram_dq[45]}]
set_property LOC AG31 [get_ports {ddram_dq[46]}]
set_property LOC AF30 [get_ports {ddram_dq[47]}]
set_property LOC AE32 [get_ports {ddram_dq[48]}]
set_property LOC AC33 [get_ports {ddram_dq[49]}]
set_property LOC AF33 [get_ports {ddram_dq[50]}]
set_property LOC AC32 [get_ports {ddram_dq[51]}]
set_property LOC AD34 [get_ports {ddram_dq[52]}]
set_property LOC AC34 [get_ports {ddram_dq[53]}]
set_property LOC AE33 [get_ports {ddram_dq[54]}]
set_property LOC AE31 [get_ports {ddram_dq[55]}]
set_property LOC AE26 [get_ports {ddram_dq[56]}]
set_property LOC AF29 [get_ports {ddram_dq[57]}]
set_property LOC AE24 [get_ports {ddram_dq[58]}]
set_property LOC AF28 [get_ports {ddram_dq[59]}]
set_property LOC AF24 [get_ports {ddram_dq[60]}]
set_property LOC AG25 [get_ports {ddram_dq[61]}]
set_property LOC AF26 [get_ports {ddram_dq[62]}]
set_property LOC AF25 [get_ports {ddram_dq[63]}]
set_property SLEW FAST [get_ports {ddram_dq[0]}]
set_property SLEW FAST [get_ports {ddram_dq[1]}]
set_property SLEW FAST [get_ports {ddram_dq[2]}]
set_property SLEW FAST [get_ports {ddram_dq[3]}]
set_property SLEW FAST [get_ports {ddram_dq[4]}]
set_property SLEW FAST [get_ports {ddram_dq[5]}]
set_property SLEW FAST [get_ports {ddram_dq[6]}]
set_property SLEW FAST [get_ports {ddram_dq[7]}]
set_property SLEW FAST [get_ports {ddram_dq[8]}]
set_property SLEW FAST [get_ports {ddram_dq[9]}]
set_property SLEW FAST [get_ports {ddram_dq[10]}]
set_property SLEW FAST [get_ports {ddram_dq[11]}]
set_property SLEW FAST [get_ports {ddram_dq[12]}]
set_property SLEW FAST [get_ports {ddram_dq[13]}]
set_property SLEW FAST [get_ports {ddram_dq[14]}]
set_property SLEW FAST [get_ports {ddram_dq[15]}]
set_property SLEW FAST [get_ports {ddram_dq[16]}]
set_property SLEW FAST [get_ports {ddram_dq[17]}]
set_property SLEW FAST [get_ports {ddram_dq[18]}]
set_property SLEW FAST [get_ports {ddram_dq[19]}]
set_property SLEW FAST [get_ports {ddram_dq[20]}]
set_property SLEW FAST [get_ports {ddram_dq[21]}]
set_property SLEW FAST [get_ports {ddram_dq[22]}]
set_property SLEW FAST [get_ports {ddram_dq[23]}]
set_property SLEW FAST [get_ports {ddram_dq[24]}]
set_property SLEW FAST [get_ports {ddram_dq[25]}]
set_property SLEW FAST [get_ports {ddram_dq[26]}]
set_property SLEW FAST [get_ports {ddram_dq[27]}]
set_property SLEW FAST [get_ports {ddram_dq[28]}]
set_property SLEW FAST [get_ports {ddram_dq[29]}]
set_property SLEW FAST [get_ports {ddram_dq[30]}]
set_property SLEW FAST [get_ports {ddram_dq[31]}]
set_property SLEW FAST [get_ports {ddram_dq[32]}]
set_property SLEW FAST [get_ports {ddram_dq[33]}]
set_property SLEW FAST [get_ports {ddram_dq[34]}]
set_property SLEW FAST [get_ports {ddram_dq[35]}]
set_property SLEW FAST [get_ports {ddram_dq[36]}]
set_property SLEW FAST [get_ports {ddram_dq[37]}]
set_property SLEW FAST [get_ports {ddram_dq[38]}]
set_property SLEW FAST [get_ports {ddram_dq[39]}]
set_property SLEW FAST [get_ports {ddram_dq[40]}]
set_property SLEW FAST [get_ports {ddram_dq[41]}]
set_property SLEW FAST [get_ports {ddram_dq[42]}]
set_property SLEW FAST [get_ports {ddram_dq[43]}]
set_property SLEW FAST [get_ports {ddram_dq[44]}]
set_property SLEW FAST [get_ports {ddram_dq[45]}]
set_property SLEW FAST [get_ports {ddram_dq[46]}]
set_property SLEW FAST [get_ports {ddram_dq[47]}]
set_property SLEW FAST [get_ports {ddram_dq[48]}]
set_property SLEW FAST [get_ports {ddram_dq[49]}]
set_property SLEW FAST [get_ports {ddram_dq[50]}]
set_property SLEW FAST [get_ports {ddram_dq[51]}]
set_property SLEW FAST [get_ports {ddram_dq[52]}]
set_property SLEW FAST [get_ports {ddram_dq[53]}]
set_property SLEW FAST [get_ports {ddram_dq[54]}]
set_property SLEW FAST [get_ports {ddram_dq[55]}]
set_property SLEW FAST [get_ports {ddram_dq[56]}]
set_property SLEW FAST [get_ports {ddram_dq[57]}]
set_property SLEW FAST [get_ports {ddram_dq[58]}]
set_property SLEW FAST [get_ports {ddram_dq[59]}]
set_property SLEW FAST [get_ports {ddram_dq[60]}]
set_property SLEW FAST [get_ports {ddram_dq[61]}]
set_property SLEW FAST [get_ports {ddram_dq[62]}]
set_property SLEW FAST [get_ports {ddram_dq[63]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[15]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[16]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[17]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[18]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[19]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[20]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[21]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[22]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[23]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[24]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[25]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[26]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[27]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[28]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[29]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[30]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[31]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[32]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[33]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[34]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[35]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[36]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[37]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[38]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[39]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[40]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[41]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[42]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[43]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[44]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[45]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[46]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[47]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[48]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[49]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[50]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[51]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[52]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[53]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[54]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[55]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[56]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[57]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[58]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[59]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[60]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[61]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[62]}]
set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[63]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[16]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[17]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[18]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[19]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[20]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[21]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[22]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[23]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[24]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[25]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[26]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[27]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[28]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[29]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[30]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[31]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[32]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[33]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[34]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[35]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[36]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[37]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[38]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[39]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[40]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[41]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[42]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[43]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[44]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[45]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[46]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[47]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[48]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[49]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[50]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[51]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[52]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[53]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[54]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[55]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[56]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[57]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[58]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[59]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[60]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[61]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[62]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[63]}]
set_property LOC AK16 [get_ports {ddram_dqs_p[0]}]
set_property LOC AM17 [get_ports {ddram_dqs_p[1]}]
set_property LOC AP21 [get_ports {ddram_dqs_p[2]}]
set_property LOC AH20 [get_ports {ddram_dqs_p[3]}]
set_property LOC AK33 [get_ports {ddram_dqs_p[4]}]
set_property LOC AG33 [get_ports {ddram_dqs_p[5]}]
set_property LOC AE34 [get_ports {ddram_dqs_p[6]}]
set_property LOC AE27 [get_ports {ddram_dqs_p[7]}]
set_property LOC AK17 [get_ports {ddram_dqs_n[0]}]
set_property LOC AM18 [get_ports {ddram_dqs_n[1]}]
set_property LOC AP22 [get_ports {ddram_dqs_n[2]}]
set_property LOC AJ20 [get_ports {ddram_dqs_n[3]}]
set_property LOC AL33 [get_ports {ddram_dqs_n[4]}]
set_property LOC AH33 [get_ports {ddram_dqs_n[5]}]
set_property LOC AF34 [get_ports {ddram_dqs_n[6]}]
set_property LOC AE28 [get_ports {ddram_dqs_n[7]}]
set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
set_property SLEW FAST [get_ports {ddram_dqs_p[2]}]
set_property SLEW FAST [get_ports {ddram_dqs_p[3]}]
set_property SLEW FAST [get_ports {ddram_dqs_p[4]}]
set_property SLEW FAST [get_ports {ddram_dqs_p[5]}]
set_property SLEW FAST [get_ports {ddram_dqs_p[6]}]
set_property SLEW FAST [get_ports {ddram_dqs_p[7]}]
set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
set_property SLEW FAST [get_ports {ddram_dqs_n[2]}]
set_property SLEW FAST [get_ports {ddram_dqs_n[3]}]
set_property SLEW FAST [get_ports {ddram_dqs_n[4]}]
set_property SLEW FAST [get_ports {ddram_dqs_n[5]}]
set_property SLEW FAST [get_ports {ddram_dqs_n[6]}]
set_property SLEW FAST [get_ports {ddram_dqs_n[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[7]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[0]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[1]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[2]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[3]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[4]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[5]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[6]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[7]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[0]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[1]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[2]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[3]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[4]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[5]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[6]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[7]}]
set_property LOC AN25 [get_ports {ddram_clk_p}]
set_property LOC AP25 [get_ports {ddram_clk_n}]
set_property SLEW FAST [get_ports {ddram_clk_p}]
set_property SLEW FAST [get_ports {ddram_clk_n}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}]