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UberDDR3
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all example demos passing openxc7 run!

This commit is contained in:
AngeloJacobo 2025-03-02 18:42:49 +08:00
parent e8444fb379
commit 4ce06f5fd8
10 changed files with 27 additions and 16 deletions
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example_demo/alinx_ax7103b/ax7103_ddr3.bit Normal file
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example_demo/alinx_ax7103b/ax7103_ddr3.v
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@ -238,9 +238,7 @@
.io_ddr3_dqs_n(ddr3_dqs_n),
.o_ddr3_dm(ddr3_dm),
.o_ddr3_odt(ddr3_odt), // on-die termination
.o_debug1(o_debug1),
.o_debug2(),
.o_debug3()
.o_debug1(o_debug1)
);
endmodule

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example_demo/alinx_ax7325b/ax7325b_ddr3.bit Normal file
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example_demo/alinx_ax7325b/ax7325b_ddr3.v
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@ -88,7 +88,7 @@
//Differentia system clock to single end clock
//===========================================================================
wire sys_clk; // 200MHz
IBUFGDS u_ibufg_sys_clk
IBUFDS u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
@ -213,9 +213,7 @@
.io_ddr3_dqs_n(ddr3_dqs_n),
.o_ddr3_dm(ddr3_dm),
.o_ddr3_odt(ddr3_odt), // on-die termination
.o_debug1(o_debug1),
.o_debug2(),
.o_debug3()
.o_debug1(o_debug1)
);
endmodule

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example_demo/arty_s7/arty_ddr3.bit Normal file
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27
example_demo/enclustra_kx2_st1/clk_wiz.v
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@ -6,12 +6,16 @@ module clk_wiz
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4,
output clk_out5,
input reset,
output locked
);
wire clk_out1_clk_wiz_0;
wire clk_out2_clk_wiz_0;
wire clk_out3_clk_wiz_0;
// wire clk_out4_clk_wiz_0;
// wire clk_out5_clk_wiz_0;
wire clkfbout;
@ -20,17 +24,23 @@ module clk_wiz
.COMPENSATION ("INTERNAL"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (10), // 200 MHz * 10 = 2000 MHz
.CLKFBOUT_MULT (5), // 200 MHz * 5 = 1000 MHz
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (12), // 2000 MHz / 12 = 166.67 MHz
.CLKOUT0_DIVIDE (12), // 1000 MHz / 12 = 83.333 MHz
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (3), // 2000 MHz / 3 = 666.67 MHz
.CLKOUT1_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (10), // 2000 MHz / 10 = 200 MHz
.CLKOUT2_DIVIDE (5), // 1000 MHz / 5 = 200 MHz
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
// .CLKOUT3_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz, 90 phase
// .CLKOUT3_PHASE (90.000),
// .CLKOUT3_DUTY_CYCLE (0.500),
// .CLKOUT4_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz, 180 phase
// .CLKOUT4_PHASE (180),
// .CLKOUT4_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (5) // 200 MHz input
)
plle2_adv_inst
@ -39,6 +49,8 @@ module clk_wiz
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT2 (clk_out3_clk_wiz_0),
// .CLKOUT3 (clk_out4_clk_wiz_0),
// .CLKOUT4 (clk_out5_clk_wiz_0),
.CLKFBIN (clkfbout),
.CLKIN1 (clk_in1),
.LOCKED (locked),
@ -53,5 +65,10 @@ module clk_wiz
BUFG clkout3_buf
(.O (clk_out3),
.I (clk_out3_clk_wiz_0));
// BUFG clkout4_buf
// (.O (clk_out4),
// .I (clk_out4_clk_wiz_0));
// BUFG clkout5_buf
// (.O (clk_out5),
// .I (clk_out5_clk_wiz_0));
endmodule

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example_demo/enclustra_kx2_st1/enclustra_ddr3.bit Normal file
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example_demo/enclustra_kx2_st1/enclustra_ddr3.xdc
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@ -4,7 +4,7 @@
# cpu_reset_n:0
set_property PACKAGE_PIN C22 [get_ports i_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports i_rst_n]
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports btn]
# set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports btn]
# clk200:0.p
set_property IOSTANDARD LVDS [get_ports i_clk200_p]

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example_demo/qmtech_wukong/wukong_ddr3.bit Normal file
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example_demo/qmtech_wukong/wukong_ddr3.v
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@ -206,9 +206,7 @@
.io_ddr3_dqs_n(ddr3_dqs_n),
.o_ddr3_dm(ddr3_dm),
.o_ddr3_odt(ddr3_odt), // on-die termination
.o_debug1(o_debug1),
.o_debug2(),
.o_debug3()
.o_debug1(o_debug1)
);
endmodule