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UberDDR3
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Merge pull request #22 from AngeloJacobo/higher_speed_feature 

Pass simulation and hardware test for DDR3-1333 and DDR3-1600!
This commit is contained in:
Angelo Jacobo 2025-02-22 11:32:19 +08:00 committed by GitHub
parent d4ecfee105 3898b1e762
commit c0e3f32bfb
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GPG Key ID: B5690EEEBB952194
66 changed files with 320302 additions and 60395 deletions
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8
.gitignore vendored
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@ -2,3 +2,11 @@ formal/ddr3_multiconfig*prf*
formal/ecc/
formal/ddr3_singleconfig/
example_demo/nexys_video/build/
testbench/xsim/xsim*
testbench/xsim/*backup*
testbench/xsim/*.log
testbench/xsim/*.pb
testbench/xsim/*.wdb
# But do not ignore testbench/xsim/test_*.log
!testbench/xsim/test_*.log

17
example_demo/enclustra_kx2_st1/clk_wiz.v
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@ -6,14 +6,12 @@ module clk_wiz
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4,
input reset,
output locked
);
wire clk_out1_clk_wiz_0;
wire clk_out2_clk_wiz_0;
wire clk_out3_clk_wiz_0;
wire clk_out4_clk_wiz_0;
wire clkfbout;
@ -22,20 +20,17 @@ module clk_wiz
.COMPENSATION ("INTERNAL"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (5), // 200 MHz * 5 = 1000 MHz
.CLKFBOUT_MULT (10), // 200 MHz * 10 = 2000 MHz
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (12), // 1000 MHz / 12 = 83.333 MHz
.CLKOUT0_DIVIDE (12), // 2000 MHz / 12 = 166.67 MHz
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz
.CLKOUT1_DIVIDE (3), // 2000 MHz / 3 = 666.67 MHz
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (5), // 1000 MHz / 5 = 200 MHz
.CLKOUT2_DIVIDE (10), // 2000 MHz / 10 = 200 MHz
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz, 90 phase
.CLKOUT3_PHASE (90.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (5) // 200 MHz input
)
plle2_adv_inst
@ -44,7 +39,6 @@ module clk_wiz
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT2 (clk_out3_clk_wiz_0),
.CLKOUT3 (clk_out4_clk_wiz_0),
.CLKFBIN (clkfbout),
.CLKIN1 (clk_in1),
.LOCKED (locked),
@ -59,8 +53,5 @@ module clk_wiz
BUFG clkout3_buf
(.O (clk_out3),
.I (clk_out3_clk_wiz_0));
BUFG clkout4_buf
(.O (clk_out4),
.I (clk_out4_clk_wiz_0));
endmodule

367
example_demo/enclustra_kx2_st1/ddr3_test.v Normal file
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@ -0,0 +1,367 @@
////////////////////////////////////////////////////////////////////////////////
//
// Filename: ddr3_test.v
// Project: Test the UberDDR3 by sending traffic via the Wishbone interface
//
// Purpose: Sends traffic over Wishbone interface of UberDDR3. This has 3 tests:
// - burst write/read
// - random write/read
// - alternating write/read
// Uses MicroBlaze to report via UART the number of read matches, mismatches, and
// total time elapsed. Report summary is sent every second.
//
// Engineer: Angelo C. Jacobo
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2023-2025 Angelo Jacobo
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////////////
// `default_nettype none
`timescale 1ps / 1ps
module ddr3_test #(
parameter WB_ADDR_BITS = 25,
WB_DATA_BITS = 512,
WB_SEL_BITS = WB_DATA_BITS / 8,
AUX_WIDTH = 4,
DATA_MASK = 1,
parameter[0:0] MICRON_SIM = 0
)
(
input wire i_clk, // ddr3 test clock
input wire i_clk100, // microblaze clock
input wire i_rst_n,
//
// Wishbone inputs
output reg o_wb_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
output reg o_wb_stb, //request a transfer
output reg o_wb_we, //write-enable (1 = write, 0 = read)
output reg[WB_ADDR_BITS - 1:0] o_wb_addr, //burst-addressable {row,bank,col}
output reg[WB_DATA_BITS - 1:0] o_wb_data, //write data, for a 4:1 controller data width is 8 times the number of pins on the device
output reg[WB_SEL_BITS - 1:0] o_wb_sel, //byte strobe for write (1 = write the byte)
output reg[AUX_WIDTH - 1:0] o_aux, //for AXI-interface compatibility (given upon strobe)
//
// Wishbone outputs
input wire i_wb_stall, //1 = busy, cannot accept requests
input wire i_wb_ack, //1 = read/write request has completed
input wire i_wb_err, //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
input wire[WB_DATA_BITS - 1:0] i_wb_data, //read data, for a 4:1 controller data width is 8 times the number of pins on the device
input wire[AUX_WIDTH - 1:0] i_aux, //for AXI-interface compatibility (given upon strobe)
//
// Done Calibration pin
input wire i_calib_complete,
//
// UART line
input wire rx,
output wire tx,
// Button for fault-injection
input wire btn,
//
// Debug
output wire timer_pulse,
output wire wrong_data_counter_non_zero
);
localparam IDLE=0,
BURST_WRITE=1,
BURST_READ=2,
RANDOM_WRITE=3,
RANDOM_READ=4,
ALTERNATE_WRITE_READ=5,
DONE_TEST=6;
localparam SIM_ADDRESS_INCR_LOG2 = WB_ADDR_BITS-2-6; // 2^(WB_ADDR_BITS-2)/64
localparam HALF_ADDRESS = 13;
localparam SIM_ADDRESS_START = {(WB_ADDR_BITS){1'b1}} - 99; // minus odd number so result is even (similar to default address start of zero)
(* mark_debug = "true" *) reg[3:0] state=IDLE;
reg[3:0] rest_counter=0;
wire[WB_DATA_BITS-1:0] correct_data;
wire[WB_DATA_BITS-1:0] wb_data_randomized;
reg[WB_ADDR_BITS-1:0] write_test_address_counter = 0, read_test_address_counter = 0;
reg[WB_ADDR_BITS-1:0] check_test_address_counter = 0;
reg[$clog2(WB_SEL_BITS)-1:0] write_by_byte_counter = 0;
(* mark_debug = "true" *) reg[63:0] correct_read_data_counter = 0, wrong_read_data_counter = 0; // 64-bit counter for correct and wrong read data, this make sure the counter will not overflow when several day's worth of DDR3 test is done on hardware
(* mark_debug = "true" *) reg[WB_DATA_BITS-1:0] wrong_data, expected_data;
reg[63:0] time_counter = 0;
(* mark_debug = "true" *) reg[31:0] injected_faults_counter = 0;
assign timer_pulse = time_counter[27]; // 1.34 sec
assign wrong_data_counter_non_zero = wrong_read_data_counter != 0; // pulse when there is wrong data
always @(posedge i_clk, negedge i_rst_n) begin
if(!i_rst_n) begin
state <= IDLE;
rest_counter <= 0;
o_wb_cyc <= 0;
o_wb_stb <= 0;
o_wb_we <= 0;
o_wb_addr <= 0;
o_wb_data <= 0;
o_wb_sel <= 0;
o_aux <= 0;
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
rest_counter <= 0;
read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
write_by_byte_counter <= 0;
injected_faults_counter <= 0;
end
else begin
case(state)
IDLE: if(i_calib_complete) begin // wait until DDR3 is done calibrating
rest_counter = rest_counter + 1;
if(rest_counter == 4'hf) begin // rest for 16 cycles before starting test
state <= BURST_WRITE;
o_wb_cyc <= 1'b1;
end
end
else begin
o_wb_cyc <= 0;
o_wb_stb <= 0;
o_wb_we <= 0;
o_wb_addr <= 0;
o_wb_data <= 0;
o_wb_sel <= 0;
o_aux <= 0;
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
rest_counter <= 0;
read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
write_by_byte_counter <= 0;
injected_faults_counter <= 0;
end
BURST_WRITE: if(!i_wb_stall) begin // Test 1: Burst write (per byte write to test datamask feature), then burst read
o_wb_stb <= 1'b1;
o_aux <= 2; // write
o_wb_we <= 1;
if(DATA_MASK) begin // If datamasking is available, test datamask by writing 8 bytes at a time
o_wb_sel <= {{WB_SEL_BITS-8{1'b0}}, 8'hff} << write_by_byte_counter; // write_by_byte_counter increments by 8 from 0 to (WB_SEL_BITS-8)
o_wb_addr <= write_test_address_counter;
o_wb_data <= {WB_SEL_BITS{8'haa}}; // fill data initially by 8'haa
o_wb_data[8*write_by_byte_counter +: 64] <= btn_pulse? {64{1'b0}} : wb_data_randomized[8*write_by_byte_counter +: 64]; // place the real data at the datamasked bytes
injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
if(write_by_byte_counter == (WB_SEL_BITS-8)) begin // once every 64bytes of data is written, go to next address
write_test_address_counter <= write_test_address_counter + 1;
/* verilator lint_off WIDTHEXPAND */
if( write_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin // wait until all address space is writtten
/* verilator lint_on WIDTHEXPAND */
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= BURST_READ;
end
end
write_by_byte_counter <= write_by_byte_counter + 8;
end
else begin // Burst write to all bytes (all datamask on)
o_wb_sel <= {WB_SEL_BITS{1'b1}};
o_wb_addr <= write_test_address_counter;
o_wb_data <= btn_pulse? {WB_DATA_BITS{1'b0}} : wb_data_randomized;
injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
write_test_address_counter <= write_test_address_counter + 1;
/* verilator lint_off WIDTHEXPAND */
if( write_test_address_counter == {WB_ADDR_BITS{1'b1}} ) begin // wait until all address space is writtten
/* verilator lint_on WIDTHEXPAND */
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= BURST_READ;
end
end
end
BURST_READ: if(!i_wb_stall) begin
o_wb_stb <= 1'b1;
o_aux <= 3; // read
o_wb_we <= 0;
o_wb_addr <= read_test_address_counter;
read_test_address_counter <= read_test_address_counter + 1;
/* verilator lint_off WIDTHEXPAND */
if( read_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin // wait until all address space is read
/* verilator lint_on WIDTHEXPAND */
read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= RANDOM_WRITE;
end
end
RANDOM_WRITE: if(!i_wb_stall) begin // Test 2: Random write (increments row address to force precharge-act-r/w) then random read
o_wb_stb <= 1'b1;
o_aux <= 2; // write
o_wb_sel <= {WB_SEL_BITS{1'b1}};
o_wb_we <= 1;
// swap the halves of address counter, since address mapping is {row,bank,col} then every increment of address counter will now increment the {row, bank} preventing burst operation and forcing precharge-activate before write/read
o_wb_addr[WB_ADDR_BITS-1:HALF_ADDRESS] <= write_test_address_counter[HALF_ADDRESS-1:0]; // [25:13] <= [12:0]
o_wb_addr[HALF_ADDRESS-1:0] <= write_test_address_counter[WB_ADDR_BITS-1:HALF_ADDRESS]; // [12:0] <= [25:13]
o_wb_data <= btn_pulse? {WB_DATA_BITS{1'b0}} : wb_data_randomized;
injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
write_test_address_counter <= write_test_address_counter + 1;
/* verilator lint_off WIDTHEXPAND */
if( write_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin // wait until all address space is writtten
/* verilator lint_on WIDTHEXPAND */
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= RANDOM_READ;
end
end
RANDOM_READ: if(!i_wb_stall) begin
o_wb_stb <= 1'b1;
o_aux <= 3; // read
o_wb_we <= 0;
// swap the halves of address counter, since address mapping is {row,bank,col} then every increment of address counter will now increment the {row, bank} preventing burst operation and forcing precharge-activate before write/read
o_wb_addr[WB_ADDR_BITS-1:HALF_ADDRESS] <= read_test_address_counter[HALF_ADDRESS-1:0]; // [25:13] <= [12:0]
o_wb_addr[HALF_ADDRESS-1:0] <= read_test_address_counter[WB_ADDR_BITS-1:HALF_ADDRESS]; // [12:0] <= [25:13]
read_test_address_counter <= read_test_address_counter + 1;
/* verilator lint_off WIDTHEXPAND */
if( read_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin // wait until all address space is read
/* verilator lint_on WIDTHEXPAND */
read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= ALTERNATE_WRITE_READ;
end
end
ALTERNATE_WRITE_READ: if(!i_wb_stall) begin
o_wb_stb <= 1'b1;
o_aux <= 2 + (o_wb_we? 1:0); //2 (write), 3 (read)
o_wb_sel <= {WB_SEL_BITS{1'b1}};
o_wb_we <= !o_wb_we; // alternating write-read
o_wb_addr <= write_test_address_counter;
o_wb_data <= btn_pulse? {WB_DATA_BITS{1'b0}} : wb_data_randomized;
injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
// if current operation is write, then dont increment address since we wil read the same address next
if(o_wb_we) begin // current operation is read thus increment address
write_test_address_counter <= write_test_address_counter + 1;
end
/* verilator lint_off WIDTHEXPAND */
if( (o_wb_addr == {(WB_ADDR_BITS){1'b1}}) && !o_wb_we ) begin // only
/* verilator lint_on WIDTHEXPAND */
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= DONE_TEST;
rest_counter <= 0;
end
end
DONE_TEST: begin
o_wb_stb <= 0;
rest_counter <= rest_counter + 1;
if(rest_counter == 4'hf) begin // rest for 16 cycles before repeating test
state <= BURST_WRITE;
end
end
endcase
end
end
// Uses different operations (XOR, addition, subtraction, bit rotation) to generate different values per byte.
assign wb_data_randomized = {
{(WB_SEL_BITS/8){write_test_address_counter[0 +: 8] ^ 8'hA5, // Byte 7
write_test_address_counter[0 +: 8] | 8'h1A, // Byte 6
write_test_address_counter[0 +: 8] & 8'h33, // Byte 5
write_test_address_counter[0 +: 8] ^ 8'h5A, // Byte 4
write_test_address_counter[0 +: 8] & 8'h21, // Byte 3
write_test_address_counter[0 +: 8] | 8'hC7, // Byte 2
write_test_address_counter[0 +: 8] ^ 8'h7E, // Byte 1
write_test_address_counter[0 +: 8] ^ 8'h3C}} // Byte 0
};
/******************************************************* Test Receiver *******************************************************/
assign correct_data = {
{(WB_SEL_BITS/8){check_test_address_counter[0 +: 8] ^ 8'hA5, // Byte 7
check_test_address_counter[0 +: 8] | 8'h1A, // Byte 6
check_test_address_counter[0 +: 8] & 8'h33, // Byte 5
check_test_address_counter[0 +: 8] ^ 8'h5A, // Byte 4
check_test_address_counter[0 +: 8] & 8'h21, // Byte 3
check_test_address_counter[0 +: 8] | 8'hC7, // Byte 2
check_test_address_counter[0 +: 8] ^ 8'h7E, // Byte 1
check_test_address_counter[0 +: 8] ^ 8'h3C }} // Byte 0
};
always @(posedge i_clk, negedge i_rst_n) begin
if(!i_rst_n) begin
check_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
correct_read_data_counter <= 64'd0;
wrong_read_data_counter <= 64'd0;
wrong_data <= 512'd0;
expected_data <= 512'd0;
end
else begin
if(i_calib_complete) begin
if ( i_wb_ack && i_aux[2:0] == 3'd3 ) begin //o_aux = 3 is for read requests from DDR3 test
if(i_wb_data == correct_data) begin // if read data matches the expected, increment correct_read_data_counter
correct_read_data_counter <= correct_read_data_counter + 64'd1;
end
else begin
wrong_read_data_counter <= wrong_read_data_counter + 64'd1;
wrong_data <= i_wb_data;
expected_data <= correct_data;
end
/* verilator lint_off WIDTHEXPAND */
check_test_address_counter <= check_test_address_counter + 1;
if(check_test_address_counter+1'b1 == {(WB_ADDR_BITS){1'b0}}) begin // if next address returns to zero, then if in MICRON_SIM jump to SIM_ADDRESS_START
check_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : {(WB_ADDR_BITS){1'b0}};
end
/* verilator lint_on WIDTHEXPAND */
end
end
else begin
check_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
correct_read_data_counter <= 64'd0;
wrong_read_data_counter <= 64'd0;
wrong_data <= 512'd0;
expected_data <= 512'd0;
end
end
end
/*********************************************************************************************************************************************/
// 64-bit counter to know how much time had passed and also debounce of btn for fault-injection
(* mark_debug = "true" *) reg[27:0] btn_debounce_delay;
(* mark_debug = "true" *) reg btn_pulse_long, btn_pulse_long_prev;
(* mark_debug = "true" *) wire btn_pulse;
assign btn_pulse = btn_pulse_long && !btn_pulse_long_prev; // if current btn_pulse is high but previously low (posedge) then make pulse
always @(posedge i_clk, negedge i_rst_n) begin
if(!i_rst_n) begin
btn_pulse_long_prev <= 1'b0;
btn_debounce_delay <= 0;
btn_pulse_long <= 0;
end
else begin
btn_pulse_long_prev <= btn_pulse_long;
if(btn && !btn_pulse_long) begin // when btn asserts and btn_pulse_long is still low
btn_pulse_long <= 1'b1;
end
if(btn_debounce_delay[27]) begin // if ~1.3s had passed, set btn_pulse_long low and reset delay
btn_pulse_long <= 0;
btn_debounce_delay <= 0;
end
else begin
btn_debounce_delay <= btn_pulse_long? btn_debounce_delay + 1 : 0;
end
end
end
always @(posedge i_clk100, negedge i_rst_n) begin
if(!i_rst_n) begin
time_counter <= 64'd0;
end
else begin
time_counter <= time_counter + 1;
end
end
design_1_wrapper microblaze_inst
( .clk_in1_0(i_clk100),
.correct_read_data_counter_0(correct_read_data_counter),
.reset_rtl_0(i_rst_n),
.time_counter_0(time_counter),
.injected_faults_counter_0(injected_faults_counter),
.uart_rtl_0_rxd(rx),
.uart_rtl_0_txd(tx),
.wrong_read_data_counter_0(wrong_read_data_counter)
);
endmodule

86
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/bd/bd.tcl Normal file
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@ -0,0 +1,86 @@
proc init { cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
set full_sbusif_list [list ]
foreach busif $all_busif {
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
set busif_param_list [list]
set busif_name [get_property NAME $busif]
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
continue
}
foreach tparam $axi_standard_param_list {
lappend busif_param_list "C_${busif_name}_${tparam}"
}
bd::mark_propagate_only $cell_handle $busif_param_list
}
}
}
proc pre_propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
if { $val_on_cell != "" } {
set_property CONFIG.${tparam} $val_on_cell $busif
}
}
}
}
}
proc propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
if { $val_on_cell_intf_pin != "" } {
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
}
}
}
}
}

900
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/component.xml Normal file
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@ -0,0 +1,900 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>user.org</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>ddr3_test_monitor_axi</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>s00_axi</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
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<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_rdata</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_rresp</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_rvalid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_rready</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI data bus</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="3" spirit:rangeType="long">32</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI address bus</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">7</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_6fc15197</spirit:name>
<spirit:enumeration>32</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_list_74b5137e</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/ddr3_test_monitor_axi_v1_0_S00_AXI.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ddr3_test_monitor_axi_v1_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_e4de66a6</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/ddr3_test_monitor_axi_v1_0_S00_AXI.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ddr3_test_monitor_axi_v1_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.mdd</spirit:name>
<spirit:userFileType>mdd</spirit:userFileType>
<spirit:userFileType>driver_mdd</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>driver_tcl</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/Makefile</spirit:name>
<spirit:userFileType>driver_src</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.h</spirit:name>
<spirit:fileType>cSource</spirit:fileType>
<spirit:userFileType>driver_src</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.c</spirit:name>
<spirit:fileType>cSource</spirit:fileType>
<spirit:userFileType>driver_src</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi_selftest.c</spirit:name>
<spirit:fileType>cSource</spirit:fileType>
<spirit:userFileType>driver_src</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xgui/ddr3_test_monitor_axi_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_080b65eb</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>bd_tcl_view_fileset</spirit:name>
<spirit:file>
<spirit:name>bd/bd.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>monitors ddr3 test results</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI data bus</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="3">32</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_DATA_WIDTH">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI address bus</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">7</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_ADDR_WIDTH">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S00_AXI_BASEADDR</spirit:name>
<spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
<spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ddr3_test_monitor_axi_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Pre-Production">kintex7</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>ddr3_test_monitor_axi_v1.0</xilinx:displayName>
<xilinx:coreRevision>9</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-02-09T12:59:49Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="2149db2e"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="0c04c4c2"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f7195f90"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="9e6f557d"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a0a6f17f"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="07777575"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>

10
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.mdd Normal file
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@ -0,0 +1,10 @@
OPTION psf_version = 2.1;
BEGIN DRIVER ddr3_test_monitor_axi
OPTION supported_peripherals = (ddr3_test_monitor_axi);
OPTION copyfiles = all;
OPTION VERSION = 1.0;
OPTION NAME = ddr3_test_monitor_axi;
END DRIVER

5
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.tcl Normal file
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@ -0,0 +1,5 @@
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "ddr3_test_monitor_axi" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
}

26
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/src/Makefile Normal file
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@ -0,0 +1,26 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling ddr3_test_monitor_axi..."
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

6
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.c Normal file
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@ -0,0 +1,6 @@
/***************************** Include Files *******************************/
#include "ddr3_test_monitor_axi.h"
/************************** Function Definitions ***************************/

107
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.h Normal file
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@ -0,0 +1,107 @@
#ifndef DDR3_TEST_MONITOR_AXI_H
#define DDR3_TEST_MONITOR_AXI_H
/****************** Include Files ********************/
#include "xil_types.h"
#include "xstatus.h"
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG0_OFFSET 0
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG1_OFFSET 4
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG2_OFFSET 8
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG3_OFFSET 12
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG4_OFFSET 16
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG5_OFFSET 20
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG6_OFFSET 24
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG7_OFFSET 28
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG8_OFFSET 32
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG9_OFFSET 36
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG10_OFFSET 40
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG11_OFFSET 44
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG12_OFFSET 48
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG13_OFFSET 52
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG14_OFFSET 56
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG15_OFFSET 60
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG16_OFFSET 64
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG17_OFFSET 68
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG18_OFFSET 72
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG19_OFFSET 76
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG20_OFFSET 80
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG21_OFFSET 84
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG22_OFFSET 88
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG23_OFFSET 92
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG24_OFFSET 96
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG25_OFFSET 100
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG26_OFFSET 104
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG27_OFFSET 108
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG28_OFFSET 112
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG29_OFFSET 116
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG30_OFFSET 120
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG31_OFFSET 124
/**************************** Type Definitions *****************************/
/**
*
* Write a value to a DDR3_TEST_MONITOR_AXI register. A 32 bit write is performed.
* If the component is implemented in a smaller width, only the least
* significant data is written.
*
* @param BaseAddress is the base address of the DDR3_TEST_MONITOR_AXIdevice.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note
* C-style signature:
* void DDR3_TEST_MONITOR_AXI_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
*
*/
#define DDR3_TEST_MONITOR_AXI_mWriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/**
*
* Read a value from a DDR3_TEST_MONITOR_AXI register. A 32 bit read is performed.
* If the component is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the DDR3_TEST_MONITOR_AXI device.
* @param RegOffset is the register offset from the base to write to.
*
* @return Data is the data from the register.
*
* @note
* C-style signature:
* u32 DDR3_TEST_MONITOR_AXI_mReadReg(u32 BaseAddress, unsigned RegOffset)
*
*/
#define DDR3_TEST_MONITOR_AXI_mReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ****************************/
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the DDR3_TEST_MONITOR_AXI instance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.
*
*/
XStatus DDR3_TEST_MONITOR_AXI_Reg_SelfTest(void * baseaddr_p);
#endif // DDR3_TEST_MONITOR_AXI_H

60
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi_selftest.c Normal file
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@ -0,0 +1,60 @@
/***************************** Include Files *******************************/
#include "ddr3_test_monitor_axi.h"
#include "xparameters.h"
#include "stdio.h"
#include "xil_io.h"
/************************** Constant Definitions ***************************/
#define READ_WRITE_MUL_FACTOR 0x10
/************************** Function Definitions ***************************/
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the DDR3_TEST_MONITOR_AXIinstance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.
*
*/
XStatus DDR3_TEST_MONITOR_AXI_Reg_SelfTest(void * baseaddr_p)
{
u32 baseaddr;
int write_loop_index;
int read_loop_index;
int Index;
baseaddr = (u32) baseaddr_p;
xil_printf("******************************\n\r");
xil_printf("* User Peripheral Self Test\n\r");
xil_printf("******************************\n\n\r");
/*
* Write to user logic slave module register(s) and read back
*/
xil_printf("User logic slave module test...\n\r");
for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
DDR3_TEST_MONITOR_AXI_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
if ( DDR3_TEST_MONITOR_AXI_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
return XST_FAILURE;
}
xil_printf(" - slave register write/read passed\n\n\r");
return XST_SUCCESS;
}

197
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/example_designs/bfm_design/ddr3_test_monitor_axi_v1_0_tb.sv Normal file
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@ -0,0 +1,197 @@
`timescale 1ns / 1ps
`include "ddr3_test_monitor_axi_v1_0_tb_include.svh"
import axi_vip_pkg::*;
import ddr3_test_monitor_axi_v1_0_bfm_1_master_0_0_pkg::*;
module ddr3_test_monitor_axi_v1_0_tb();
xil_axi_uint error_cnt = 0;
xil_axi_uint comparison_cnt = 0;
axi_transaction wr_transaction;
axi_transaction rd_transaction;
axi_monitor_transaction mst_monitor_transaction;
axi_monitor_transaction master_moniter_transaction_queue[$];
xil_axi_uint master_moniter_transaction_queue_size =0;
axi_monitor_transaction mst_scb_transaction;
axi_monitor_transaction passthrough_monitor_transaction;
axi_monitor_transaction passthrough_master_moniter_transaction_queue[$];
xil_axi_uint passthrough_master_moniter_transaction_queue_size =0;
axi_monitor_transaction passthrough_mst_scb_transaction;
axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$];
xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0;
axi_monitor_transaction passthrough_slv_scb_transaction;
axi_monitor_transaction slv_monitor_transaction;
axi_monitor_transaction slave_moniter_transaction_queue[$];
xil_axi_uint slave_moniter_transaction_queue_size =0;
axi_monitor_transaction slv_scb_transaction;
xil_axi_uint mst_agent_verbosity = 0;
xil_axi_uint slv_agent_verbosity = 0;
xil_axi_uint passthrough_agent_verbosity = 0;
bit clock;
bit reset;
integer result_slave;
bit [31:0] S00_AXI_test_data[3:0];
localparam LC_AXI_BURST_LENGTH = 8;
localparam LC_AXI_DATA_WIDTH = 32;
task automatic COMPARE_DATA;
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected;
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave = 0; $stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.", " expected = 0x%h",expected, " actual = 0x%h",actual);
result_slave = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
" expected = 0x%h",expected, " actual = 0x%h",actual);
end
end
endtask
integer i;
integer j;
xil_axi_uint trans_cnt_before_switch = 48;
xil_axi_uint passthrough_cmd_switch_cnt = 0;
event passthrough_mastermode_start_event;
event passthrough_mastermode_end_event;
event passthrough_slavemode_end_event;
xil_axi_uint mtestID;
xil_axi_ulong mtestADDR;
xil_axi_len_t mtestBurstLength;
xil_axi_size_t mtestDataSize;
xil_axi_burst_t mtestBurstType;
xil_axi_lock_t mtestLOCK;
xil_axi_cache_t mtestCacheType = 0;
xil_axi_prot_t mtestProtectionType = 3'b000;
xil_axi_region_t mtestRegion = 4'b000;
xil_axi_qos_t mtestQOS = 4'b000;
xil_axi_data_beat dbeat;
xil_axi_data_beat [255:0] mtestWUSER;
xil_axi_data_beat mtestAWUSER = 'h0;
xil_axi_data_beat mtestARUSER = 0;
xil_axi_data_beat [255:0] mtestRUSER;
xil_axi_uint mtestBUSER = 0;
xil_axi_resp_t mtestBresp;
xil_axi_resp_t[255:0] mtestRresp;
bit [63:0] mtestWDataL;
bit [63:0] mtestRDataL;
axi_transaction pss_wr_transaction;
axi_transaction pss_rd_transaction;
axi_transaction reactive_transaction;
axi_transaction rd_payload_transaction;
axi_transaction wr_rand;
axi_transaction rd_rand;
axi_transaction wr_reactive;
axi_transaction rd_reactive;
axi_transaction wr_reactive2;
axi_transaction rd_reactive2;
axi_ready_gen bready_gen;
axi_ready_gen rready_gen;
axi_ready_gen awready_gen;
axi_ready_gen wready_gen;
axi_ready_gen arready_gen;
axi_ready_gen bready_gen2;
axi_ready_gen rready_gen2;
axi_ready_gen awready_gen2;
axi_ready_gen wready_gen2;
axi_ready_gen arready_gen2;
xil_axi_payload_byte data_mem[xil_axi_ulong];
ddr3_test_monitor_axi_v1_0_bfm_1_master_0_0_mst_t mst_agent_0;
`BD_WRAPPER DUT(
.ARESETN(reset),
.ACLK(clock)
);
initial begin
mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms
mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE);
mst_agent_0.set_agent_tag("Master VIP");
mst_agent_0.set_verbosity(mst_agent_verbosity);
mst_agent_0.start_master();
$timeformat (-12, 1, " ps", 1);
end
initial begin
reset <= 1'b0;
#200ns;
reset <= 1'b1;
repeat (5) @(negedge clock);
end
always #5 clock <= ~clock;
initial begin
S_AXI_TEST ( );
#1ns;
$finish;
end
task automatic S_AXI_TEST;
begin
#1;
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method starts");
mtestID = 0;
mtestADDR = 64'h00000000;
mtestBurstLength = 0;
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
mtestCacheType = 0;
mtestProtectionType = 0;
mtestRegion = 0;
mtestQOS = 0;
result_slave = 1;
mtestWDataL[31:0] = 32'h00000001;
for(int i = 0; i < 4;i++) begin
S00_AXI_test_data[i] <= mtestWDataL[31:0];
mst_agent_0.AXI4LITE_WRITE_BURST(
mtestADDR,
mtestProtectionType,
mtestWDataL,
mtestBresp
);
mtestWDataL[31:0] = mtestWDataL[31:0] + 1;
mtestADDR = mtestADDR + 64'h4;
end
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method completes");
$display("Sequential read transfers example similar to AXI BFM READ_BURST method starts");
mtestID = 0;
mtestADDR = 64'h00000000;
mtestBurstLength = 0;
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
mtestCacheType = 0;
mtestProtectionType = 0;
mtestRegion = 0;
mtestQOS = 0;
for(int i = 0; i < 4;i++) begin
mst_agent_0.AXI4LITE_READ_BURST(
mtestADDR,
mtestProtectionType,
mtestRDataL,
mtestRresp
);
mtestADDR = mtestADDR + 64'h4;
COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL);
end
$display("Sequential read transfers example similar to AXI BFM READ_BURST method completes");
$display("Sequential read transfers example similar to AXI VIP READ_BURST method completes");
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
endmodule

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proc create_ipi_design { offsetfile design_name } {
create_bd_design $design_name
open_bd_design $design_name
# Create Clock and Reset Ports
set ACLK [ create_bd_port -dir I -type clk ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
# Create instance: ddr3_test_monitor_axi_0, and set properties
set ddr3_test_monitor_axi_0 [ create_bd_cell -type ip -vlnv user.org:user:ddr3_test_monitor_axi:1.0 ddr3_test_monitor_axi_0]
# Create instance: master_0, and set properties
set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip master_0]
set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
# Create interface connections
connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins ddr3_test_monitor_axi_0/S00_AXI]
# Create port connections
connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins ddr3_test_monitor_axi_0/S00_AXI_ACLK]
connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins ddr3_test_monitor_axi_0/S00_AXI_ARESETN]
set_property target_simulator XSim [current_project]
set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
# Auto assign address
assign_bd_address
# Copy all address to interface_address.vh file
set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
upvar 1 $offsetfile offset_file
set offset_file "${bd_path}/ddr3_test_monitor_axi_v1_0_tb_include.svh"
set fp [open $offset_file "w"]
puts $fp "`ifndef ddr3_test_monitor_axi_v1_0_tb_include_vh_"
puts $fp "`define ddr3_test_monitor_axi_v1_0_tb_include_vh_\n"
puts $fp "//Configuration current bd names"
puts $fp "`define BD_NAME ${design_name}"
puts $fp "`define BD_INST_NAME ${design_name}_i"
puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
puts $fp "//Configuration address parameters"
puts $fp "`endif"
close $fp
}
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:ddr3_test_monitor_axi:1.0]]]]
set test_bench_file ${ip_path}/example_designs/bfm_design/ddr3_test_monitor_axi_v1_0_tb.sv
set interface_address_vh_file ""
# Set IP Repository and Update IP Catalogue
set repo_paths [get_property ip_repo_paths [current_fileset]]
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
update_ip_catalog
}
set design_name ""
set all_bd {}
set all_bd_files [get_files *.bd -quiet]
foreach file $all_bd_files {
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
lappend all_bd $bd_name
}
for { set i 1 } { 1 } { incr i } {
set design_name "ddr3_test_monitor_axi_v1_0_bfm_${i}"
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
break
}
}
create_ipi_design interface_address_vh_file ${design_name}
validate_bd_design
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
import_files -force -norecurse $wrapper_file
set_property SOURCE_SET sources_1 [get_filesets sim_1]
import_files -fileset sim_1 -norecurse -force $test_bench_file
remove_files -quiet -fileset sim_1 ddr3_test_monitor_axi_v1_0_tb_include.vh
import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
set_property top ddr3_test_monitor_axi_v1_0_tb [get_filesets sim_1]
set_property top_lib {} [get_filesets sim_1]
set_property top_file {} [get_filesets sim_1]
launch_simulation -simset sim_1 -mode behavioral

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example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/example_designs/debug_hw_design/ddr3_test_monitor_axi_v1_0_hw_test.tcl Normal file
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# Runtime Tcl commands to interact with - ddr3_test_monitor_axi_v1_0
# Sourcing design address info tcl
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
source ${bd_path}/ddr3_test_monitor_axi_v1_0_include.tcl
# jtag axi master interface hardware name, change as per your design.
set jtag_axi_master hw_axi_1
set ec 0
# hw test script
# Delete all previous axis transactions
if { [llength [get_hw_axi_txns -quiet]] } {
delete_hw_axi_txn [get_hw_axi_txns -quiet]
}
# Test all lite slaves.
set wdata_1 abcd1234
# Test: S00_AXI
# Create a write transaction at s00_axi_addr address
create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
# Create a read transaction at s00_axi_addr address
create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
# Initiate transactions
run_hw_axi r_s00_axi_addr
run_hw_axi w_s00_axi_addr
run_hw_axi r_s00_axi_addr
set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
# Compare read data
if { $rdata_tmp == $wdata_1 } {
puts "Data comparison test pass for - S00_AXI"
} else {
puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
inc ec
}
# Check error flag
if { $ec == 0 } {
puts "PTGEN_TEST: PASSED!"
} else {
puts "PTGEN_TEST: FAILED!"
}

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proc create_ipi_design { offsetfile design_name } {
create_bd_design $design_name
open_bd_design $design_name
# Create and configure Clock/Reset
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
#Constraints will be provided manually while pin planning.
create_bd_port -dir I -type rst reset_rtl
set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
set external_reset_port reset_rtl
create_bd_port -dir I -type clk clock_rtl
connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
set external_clock_port clock_rtl
#Avoid IPI DRC, make clock port synchronous to reset
if { $external_clock_port ne "" && $external_reset_port ne "" } {
set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
}
# Connect other sys_reset pins
connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
# Create instance: ddr3_test_monitor_axi_0, and set properties
set ddr3_test_monitor_axi_0 [ create_bd_cell -type ip -vlnv user.org:user:ddr3_test_monitor_axi:1.0 ddr3_test_monitor_axi_0 ]
# Create instance: jtag_axi_0, and set properties
set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Create instance: axi_peri_interconnect, and set properties
set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Connect all clock & reset of ddr3_test_monitor_axi_0 slave interfaces..
connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins ddr3_test_monitor_axi_0/S00_AXI]
connect_bd_net [get_bd_pins ddr3_test_monitor_axi_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins ddr3_test_monitor_axi_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Auto assign address
assign_bd_address
# Copy all address to ddr3_test_monitor_axi_v1_0_include.tcl file
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
upvar 1 $offsetfile offset_file
set offset_file "${bd_path}/ddr3_test_monitor_axi_v1_0_include.tcl"
set fp [open $offset_file "w"]
puts $fp "# Configuration address parameters"
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_ddr3_test_monitor_axi_0_S00_AXI_* ]]
puts $fp "set s00_axi_addr ${offset}"
close $fp
}
# Set IP Repository and Update IP Catalogue
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:ddr3_test_monitor_axi:1.0]]]]
set hw_test_file ${ip_path}/example_designs/debug_hw_design/ddr3_test_monitor_axi_v1_0_hw_test.tcl
set repo_paths [get_property ip_repo_paths [current_fileset]]
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
update_ip_catalog
}
set design_name ""
set all_bd {}
set all_bd_files [get_files *.bd -quiet]
foreach file $all_bd_files {
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
lappend all_bd $bd_name
}
for { set i 1 } { 1 } { incr i } {
set design_name "ddr3_test_monitor_axi_v1_0_hw_${i}"
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
break
}
}
set intf_address_include_file ""
create_ipi_design intf_address_include_file ${design_name}
save_bd_design
validate_bd_design
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
import_files -force -norecurse $wrapper_file
puts "-------------------------------------------------------------------------------------------------"
puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
puts " please perform following steps to test design in targeted board."
puts "1. Generate bitstream"
puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
puts "3. Download generated bitstream"
puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
puts " : source -notrace ${hw_test_file}"
puts "-------------------------------------------------------------------------------------------------"

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`timescale 1 ns / 1 ps
module ddr3_test_monitor_axi_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 7
)
(
// Users to add ports here
input wire[63:0] correct_read_data_counter, // address x0 = [31:0], x1 = [63:32]
input wire[63:0] wrong_read_data_counter, // address x2 = [31:0], x3 = [63:32]
input wire[63:0] time_counter, // address x4 = [31:0], x5 = [63:32]
input wire[31:0] injected_faults_counter,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
ddr3_test_monitor_axi_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) ddr3_test_monitor_axi_v1_0_S00_AXI_inst (
.correct_read_data_counter(correct_read_data_counter),
.wrong_read_data_counter(wrong_read_data_counter),
.timer_counter(time_counter),
.injected_faults_counter(injected_faults_counter),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule

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`timescale 1 ns / 1 ps
module ddr3_test_monitor_axi_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 7
)
(
// Users to add ports here
input wire[63:0] correct_read_data_counter,
input wire[63:0] wrong_read_data_counter,
input wire[63:0] timer_counter,
input wire[31:0] injected_faults_counter,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 4;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 32
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
slv_reg4 <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
slv_reg8 <= 0;
slv_reg9 <= 0;
slv_reg10 <= 0;
slv_reg11 <= 0;
slv_reg12 <= 0;
slv_reg13 <= 0;
slv_reg14 <= 0;
slv_reg15 <= 0;
slv_reg16 <= 0;
slv_reg17 <= 0;
slv_reg18 <= 0;
slv_reg19 <= 0;
slv_reg20 <= 0;
slv_reg21 <= 0;
slv_reg22 <= 0;
slv_reg23 <= 0;
slv_reg24 <= 0;
slv_reg25 <= 0;
slv_reg26 <= 0;
slv_reg27 <= 0;
slv_reg28 <= 0;
slv_reg29 <= 0;
slv_reg30 <= 0;
slv_reg31 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
5'h00:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h01:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h02:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h03:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h04:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 4
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h05:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 5
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h06:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 6
slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h07:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 7
slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h08:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 8
slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h09:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 9
slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0A:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 10
slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0B:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 11
slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0C:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 12
slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0D:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 13
slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0E:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 14
slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0F:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 15
slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h10:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 16
slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h11:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 17
slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h12:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 18
slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h13:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 19
slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h14:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 20
slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h15:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 21
slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h16:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 22
slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h17:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 23
slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h18:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 24
slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h19:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 25
slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1A:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 26
slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1B:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 27
slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1C:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 28
slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1D:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 29
slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1E:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 30
slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1F:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 31
slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
5'h00 : reg_data_out <= correct_read_data_counter[31:0];
5'h01 : reg_data_out <= correct_read_data_counter[63:32];
5'h02 : reg_data_out <= wrong_read_data_counter[31:0];
5'h03 : reg_data_out <= wrong_read_data_counter[63:32];
5'h04 : reg_data_out <= timer_counter[31:0];
5'h05 : reg_data_out <= timer_counter[63:32];
5'h06 : reg_data_out <= injected_faults_counter[31:0];
5'h07 : reg_data_out <= slv_reg7;
5'h08 : reg_data_out <= slv_reg8;
5'h09 : reg_data_out <= slv_reg9;
5'h0A : reg_data_out <= slv_reg10;
5'h0B : reg_data_out <= slv_reg11;
5'h0C : reg_data_out <= slv_reg12;
5'h0D : reg_data_out <= slv_reg13;
5'h0E : reg_data_out <= slv_reg14;
5'h0F : reg_data_out <= slv_reg15;
5'h10 : reg_data_out <= slv_reg16;
5'h11 : reg_data_out <= slv_reg17;
5'h12 : reg_data_out <= slv_reg18;
5'h13 : reg_data_out <= slv_reg19;
5'h14 : reg_data_out <= slv_reg20;
5'h15 : reg_data_out <= slv_reg21;
5'h16 : reg_data_out <= slv_reg22;
5'h17 : reg_data_out <= slv_reg23;
5'h18 : reg_data_out <= slv_reg24;
5'h19 : reg_data_out <= slv_reg25;
5'h1A : reg_data_out <= slv_reg26;
5'h1B : reg_data_out <= slv_reg27;
5'h1C : reg_data_out <= slv_reg28;
5'h1D : reg_data_out <= slv_reg29;
5'h1E : reg_data_out <= slv_reg30;
5'h1F : reg_data_out <= slv_reg31;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
// User logic ends
endmodule

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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
}
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to validate C_S00_AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to validate C_S00_AXI_BASEADDR
return true
}
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to validate C_S00_AXI_HIGHADDR
return true
}
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
}

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////////////////////////////////////////////////////////////////////////////////
//
// Filename: ddr3_test_top.v
// Project: Top level module instantiating the ddr3 test and UberDDR3.
//
// Engineer: Angelo C. Jacobo
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2023-2025 Angelo Jacobo
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module enclustra_ddr3_test
(
input wire i_clk200_p, i_clk200_n,
input wire i_rst_n,
// DDR3 I/O Interface
output wire ddr3_clk_p, ddr3_clk_n,
output wire ddr3_reset_n,
output wire ddr3_cke,
output wire ddr3_cs_n,
output wire ddr3_ras_n,
output wire ddr3_cas_n,
output wire ddr3_we_n,
output wire[15-1:0] ddr3_addr,
output wire[3-1:0] ddr3_ba,
inout wire[64-1:0] ddr3_dq,
inout wire[8-1:0] ddr3_dqs_p, ddr3_dqs_n,
output wire[8-1:0] ddr3_dm,
output wire ddr3_odt,
// UART line
input wire rx,
output wire tx,
//Debug LEDs
output wire[3:0] led,
// Button for fault injection
input wire btn
);
localparam CONTROLLER_CLK_PERIOD = 5_000, // ps, clock period of the controller interface
DDR3_CLK_PERIOD = 1_250, // ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
ROW_BITS = 15, // Width of row address
COL_BITS = 10, // Width of column address
BA_BITS = 3, // Width of bank address
BYTE_LANES = 8, // Number of DDR3 modules to be controlled
AUX_WIDTH = 16, // Width of aux line (must be >= 4)
BIST_MODE = 0; // Don't perform BIST, go straight to external DDR3 test
parameter MICRON_SIM = 0, // Enable faster simulation for Micron DDR3 model
ODELAY_SUPPORTED = 1, // Set to 1 when ODELAYE2 is supported
DATA_MASK = 1; // enable test on datamask
localparam WB_ADDR_BITS = ROW_BITS + COL_BITS + BA_BITS - 3,
WB_DATA_BITS = 8*BYTE_LANES*8,
WB_SEL_BITS = WB_DATA_BITS / 8;
wire sys_clk_200MHz;
wire i_controller_clk, i_ddr3_clk, i_ref_clk,i_clk100;
wire clk_locked;
wire timer_pulse, wrong_data_counter_non_zero;
// Wishbone output signals
wire o_wb_cyc; // Bus cycle active (1 = normal operation, 0 = cancel all ongoing transactions)
wire o_wb_stb; // Request a transfer
wire o_wb_we; // Write-enable (1 = write, 0 = read)
wire [WB_ADDR_BITS - 1:0] o_wb_addr; // Burst-addressable {row, bank, col}
wire [WB_DATA_BITS - 1:0] o_wb_data; // Write data (depends on controller width)
wire [WB_SEL_BITS - 1:0] o_wb_sel; // Byte strobe for write (1 = write the byte)
wire [AUX_WIDTH - 1:0] o_aux; // AXI-interface compatibility (given upon strobe)
// Wishbone input signals
wire i_wb_stall; // 1 = Busy, cannot accept requests
wire i_wb_ack; // 1 = Read/write request completed
wire [WB_DATA_BITS - 1:0] i_wb_data; // Read data
wire [AUX_WIDTH - 1:0] i_aux; // AXI-interface compatibility (given upon strobe)
(* mark_debug = "true" *) wire calib_complete;
assign led[0] = !calib_complete; //light up if at DONE_CALIBRATE
assign led[1] = !wrong_data_counter_non_zero; //light up if at there is wrong data
assign led[2] = !timer_pulse; //light up at timer pulse
assign led[3] = !timer_pulse; //light up at timer pulse
IBUFDS sys_clk_ibufgds
(
.O(sys_clk_200MHz),
.I(i_clk200_p),
.IB(i_clk200_n)
);
clk_wiz_0 clk_wiz_inst
(
// Clock out ports
.controller_clk(i_controller_clk),
.ddr3_clk(i_ddr3_clk),
.ref200_clk(i_ref_clk),
.clk100(i_clk100),
// Status and control signals
.reset(!i_rst_n),
.locked(clk_locked),
// Clock in ports
.clk_in1(sys_clk_200MHz)
);
// DDR3 Controller
ddr3_top #(
.CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.ROW_BITS(ROW_BITS), //width of row address
.COL_BITS(COL_BITS), //width of column address
.BA_BITS(BA_BITS), //width of bank address
.BYTE_LANES(BYTE_LANES), //number of DDR3 modules to be controlled
.AUX_WIDTH(AUX_WIDTH), //width of aux line (must be >= 4)
.MICRON_SIM(MICRON_SIM), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
.ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 when ODELAYE2 is supported
.BIST_MODE(BIST_MODE)
) ddr3_top_inst
(
//clock and reset
.i_controller_clk(i_controller_clk),
.i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD
.i_ref_clk(i_ref_clk),
.i_ddr3_clk_90(),
.i_rst_n(i_rst_n && clk_locked),
// Wishbone inputs
.i_wb_cyc(o_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
.i_wb_stb(o_wb_stb), //request a transfer
.i_wb_we(o_wb_we), //write-enable (1 = write, 0 = read)
.i_wb_addr(o_wb_addr), //burst-addressable {row,bank,col}
.i_wb_data(o_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
.i_wb_sel(o_wb_sel), //byte strobe for write (1 = write the byte)
.i_aux(o_aux), //for AXI-interface compatibility (given upon strobe)
// Wishbone outputs
.o_wb_stall(i_wb_stall), //1 = busy, cannot accept requests
.o_wb_ack(i_wb_ack), //1 = read/write request has completed
.o_wb_data(i_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
.o_aux(i_aux),
// PHY Interface (to be added later)
// DDR3 I/O Interface
.o_ddr3_clk_p(ddr3_clk_p),
.o_ddr3_clk_n(ddr3_clk_n),
.o_ddr3_reset_n(ddr3_reset_n),
.o_ddr3_cke(ddr3_cke), // CKE
.o_ddr3_cs_n(ddr3_cs_n), // chip select signal (controls rank 1 only)
.o_ddr3_ras_n(ddr3_ras_n), // RAS#
.o_ddr3_cas_n(ddr3_cas_n), // CAS#
.o_ddr3_we_n(ddr3_we_n), // WE#
.o_ddr3_addr(ddr3_addr),
.o_ddr3_ba_addr(ddr3_ba),
.io_ddr3_dq(ddr3_dq),
.io_ddr3_dqs(ddr3_dqs_p),
.io_ddr3_dqs_n(ddr3_dqs_n),
.o_ddr3_dm(ddr3_dm),
.o_ddr3_odt(ddr3_odt), // on-die termination
// debug
.o_calib_complete(calib_complete)
);
ddr3_test #(
.WB_ADDR_BITS(WB_ADDR_BITS),
.WB_DATA_BITS(WB_DATA_BITS),
.WB_SEL_BITS(WB_SEL_BITS),
.AUX_WIDTH(AUX_WIDTH),
.DATA_MASK(DATA_MASK),
.MICRON_SIM(MICRON_SIM)
) ddr3_test_inst
(
.i_clk(i_controller_clk),
.i_clk100(i_clk100),
.i_rst_n(i_rst_n),
//
// Wishbone inputs
.o_wb_cyc(o_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
.o_wb_stb(o_wb_stb), //request a transfer
.o_wb_we(o_wb_we), //write-enable (1 = write, 0 = read)
.o_wb_addr(o_wb_addr), //burst-addressable {row,bank,col}
.o_wb_data(o_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
.o_wb_sel(o_wb_sel), //byte strobe for write (1 = write the byte)
.o_aux(o_aux), //for AXI-interface compatibility (given upon strobe)
//
// Wishbone outputs
.i_wb_stall(i_wb_stall), //1 = busy, cannot accept requests
.i_wb_ack(i_wb_ack), //1 = read/write request has completed
.i_wb_err(0), //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
.i_wb_data(i_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
.i_aux(i_aux), //for AXI-interface compatibility (given upon strobe)
//
// Done Calibration pin
.i_calib_complete(calib_complete),
//
// UART line
.rx(rx),
.tx(tx),
// Button for fault injection
.btn(!btn),
// Debug
.timer_pulse(timer_pulse),
.wrong_data_counter_non_zero(wrong_data_counter_non_zero)
);
endmodule

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////////////////////////////////////////////////////////////////////////////////
//
// Filename: ddr3_test_top.v
// Project: Testbench for ddr3_test_top.v
//
// Engineer: Angelo C. Jacobo
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2023-2025 Angelo Jacobo
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module ddr3_test_top_tb;
// PHY Interface to DDR3 Device
wire[1:0] ddr3_cke; // CKE
wire[1:0] ddr3_cs_n; // chip select signal
wire[1:0] ddr3_odt; // on-die termination
wire ddr3_ras_n; // RAS#
wire ddr3_cas_n; // CAS#
wire ddr3_we_n; // WE#
wire ddr3_reset_n;
wire[$bits(DUT.ddr3_addr)-1:0] ddr3_addr;
wire[$bits(DUT.ddr3_ba)-1:0] ddr3_ba;
wire[$bits(DUT.ddr3_dm)-1:0] ddr3_dm;
wire[$bits(DUT.ddr3_dq)-1:0] ddr3_dq;
wire[$bits(DUT.ddr3_dqs_p)-1:0] ddr3_dqs_p;
wire[$bits(DUT.ddr3_dqs_n)-1:0] ddr3_dqs_n;
wire[1:0] ddr3_clk_p, ddr3_clk_n;
// clocks and reset
reg i_clk200_p;
reg i_rst_n;
initial begin
i_clk200_p = 0;
i_rst_n = 0;
#1000;
i_rst_n = 1;
end
always #2_500 i_clk200_p = !i_clk200_p; // 200MHz
enclustra_ddr3_test #(
.MICRON_SIM(1),
.ODELAY_SUPPORTED(1),
.DATA_MASK(1)
)
DUT (
.i_clk200_p(i_clk200_p),
.i_clk200_n(!i_clk200_p),
.i_rst_n(i_rst_n),
// DDR3 I/O Interface
.ddr3_clk_p(ddr3_clk_p),
.ddr3_clk_n(ddr3_clk_n),
.ddr3_reset_n(ddr3_reset_n),
.ddr3_cke(ddr3_cke),
.ddr3_cs_n(ddr3_cs_n),
.ddr3_ras_n(ddr3_ras_n),
.ddr3_cas_n(ddr3_cas_n),
.ddr3_we_n(ddr3_we_n),
.ddr3_addr(ddr3_addr),
.ddr3_ba(ddr3_ba),
.ddr3_dq(ddr3_dq),
.ddr3_dqs_p(ddr3_dqs_p),
.ddr3_dqs_n(ddr3_dqs_n),
.ddr3_dm(ddr3_dm),
.ddr3_odt(ddr3_odt),
// UART line
.rx(0),
.tx(),
// Debug LEDs
.led()
);
// DDR3 Device
ddr3_module ddr3_module(
.reset_n(ddr3_reset_n),
.ck(ddr3_clk_p), //[1:0]
.ck_n(ddr3_clk_n), //[1:0]
.cke(ddr3_cke), //[1:0]
.s_n(ddr3_cs_n), //[1:0]
.ras_n(ddr3_ras_n),
.cas_n(ddr3_cas_n),
.we_n(ddr3_we_n),
.ba(ddr3_ba),
.addr({0,ddr3_addr}),
.odt(ddr3_odt), //[1:0]
.dqs({ddr3_dm[0], ddr3_dm,ddr3_dm[0],ddr3_dqs_p}), //ddr3_module uses last 8 MSB [16:9] as datamask
.dqs_n(ddr3_dqs_n),
.dq(ddr3_dq)
);
assign ddr3_cke[1]=0,
ddr3_cs_n[1]=1,
ddr3_odt[1]=0,
ddr3_clk_p[1]=0,
ddr3_clk_n[1]=0;
endmodule

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################################################################################
################################################################################
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
# set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS18 } [get_ports {CLK_100_CAL}]
# set_property DCI_CASCADE {32 33} [get_iobanks 34]
## For a 1.5V memory, the appropriate VREF voltage is half of 1.5, or 0.75 Volts
## Of the DDR3 bank(s), only bank 33 needs the INTERNAL_VREF. The other DDR3
## banks are explicitly connected to an external VREF signal. However, bank
## 33s IOs are overloaded--there was no room for the VREF. Hence, to spare
## two pins, bank 33 uses an internal voltage reference. Sadly, the same
## problem plays out in banks 12-16 as well.
# set_property INTERNAL_VREF 0.750 [get_iobanks 33]
# ## Other IO banks have internal VREFs as well, those these aren't as critical
# set_property INTERNAL_VREF 0.90 [get_iobanks 12]
# set_property INTERNAL_VREF 0.60 [get_iobanks 13]
# set_property INTERNAL_VREF 0.90 [get_iobanks 14]
# set_property INTERNAL_VREF 0.90 [get_iobanks 15]
# set_property INTERNAL_VREF 0.90 [get_iobanks 16]
## Clocks
# 100MHz single ended input clock
set_property -dict {PACKAGE_PIN AA4 IOSTANDARD SSTL15} [get_ports i_clk]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk]
# Baseboard LEDs
# set_property -dict {SLEW SLOW PACKAGE_PIN F22 IOSTANDARD LVCMOS18 } [get_ports { o_led_status[4] }] # GPIO0_LED0_N
set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports {led[0]}]
set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS12} [get_ports {led[1]}]
set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS12} [get_ports {led[2]}]
## UART
## {{{
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18 } [get_ports {rx}]
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18 } [get_ports {tx}]
## }}}
## Buttons
## {{{
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18 } [get_ports {i_rst_n}]
## DDR3 MEMORY
set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_reset_n}]
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_clk_p}]
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_clk_n}]
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_cke}]
## set_property -dict {SLEW SLOW PACKAGE_PIN AA3 IOSTANDARD LVCMOS15 } [get_ports {o_ddr3_vsel}]
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_cs_n}]
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_ras_n}]
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_cas_n}]
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_we_n}]
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_odt}]
## Address lines
set_property -dict {PACKAGE_PIN AE11 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[0]}]
set_property -dict {PACKAGE_PIN AF9 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[1]}]
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[2]}]
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[3]}]
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[4]}]
set_property -dict {PACKAGE_PIN AB9 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[5]}]
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[6]}]
set_property -dict {PACKAGE_PIN AC8 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[7]}]
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[8]}]
set_property -dict {PACKAGE_PIN AE8 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[9]}]
set_property -dict {PACKAGE_PIN AF10 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[10]}]
set_property -dict {PACKAGE_PIN AD8 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[11]}]
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[12]}]
set_property -dict {PACKAGE_PIN AF8 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[13]}]
set_property -dict {PACKAGE_PIN AC7 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[14]}]
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_ba[0]}]
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_ba[1]}]
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_ba[2]}]
## Byte lane #0
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[0]}]
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[1]}]
set_property -dict {PACKAGE_PIN AB2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[2]}]
set_property -dict {PACKAGE_PIN V1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[3]}]
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[4]}]
set_property -dict {PACKAGE_PIN W1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[5]}]
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[6]}]
set_property -dict {PACKAGE_PIN V2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[7]}]
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[0]}]
set_property -dict {PACKAGE_PIN AB1 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[0]}]
set_property -dict {PACKAGE_PIN AC1 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[0]}]
## Byte lane #1
set_property -dict {PACKAGE_PIN W3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[8]}]
set_property -dict {PACKAGE_PIN V3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[9]}]
set_property -dict {PACKAGE_PIN U1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[10]}]
set_property -dict {PACKAGE_PIN U7 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[11]}]
set_property -dict {PACKAGE_PIN U6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[12]}]
set_property -dict {PACKAGE_PIN V4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[13]}]
set_property -dict {PACKAGE_PIN V6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[14]}]
set_property -dict {PACKAGE_PIN U2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[15]}]
set_property -dict {PACKAGE_PIN U5 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[1]}]
set_property -dict {PACKAGE_PIN W6 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[1]}]
set_property -dict {PACKAGE_PIN W5 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[1]}]
## Byte lane #2
set_property -dict {PACKAGE_PIN AE3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[16]}]
set_property -dict {PACKAGE_PIN AE6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[17]}]
set_property -dict {PACKAGE_PIN AF3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[18]}]
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[19]}]
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[20]}]
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[21]}]
set_property -dict {PACKAGE_PIN AF2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[22]}]
set_property -dict {PACKAGE_PIN AE5 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[23]}]
set_property -dict {PACKAGE_PIN AD4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[2]}]
set_property -dict {PACKAGE_PIN AF5 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[2]}]
set_property -dict {PACKAGE_PIN AF4 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[2]}]
## Byte lane #3
set_property -dict {PACKAGE_PIN AD5 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[24]}]
set_property -dict {PACKAGE_PIN Y5 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[25]}]
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[26]}]
set_property -dict {PACKAGE_PIN Y6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[27]}]
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[28]}]
set_property -dict {PACKAGE_PIN AD6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[29]}]
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[30]}]
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[31]}]
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[3]}]
set_property -dict {PACKAGE_PIN AA5 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[3]}]
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[3]}]
## Byte lane #4
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[32]}]
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[33]}]
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[34]}]
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[35]}]
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[36]}]
set_property -dict {PACKAGE_PIN AF14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[37]}]
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[38]}]
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[39]}]
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[4]}]
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[4]}]
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[4]}]
## Byte lane #5
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[40]}]
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[41]}]
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[42]}]
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[43]}]
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[44]}]
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[45]}]
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[46]}]
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[47]}]
set_property -dict {PACKAGE_PIN AC16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[5]}]
set_property -dict {PACKAGE_PIN Y15 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[5]}]
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[5]}]
## Byte lane #6
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[48]}]
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[49]}]
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[50]}]
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[51]}]
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[52]}]
set_property -dict {PACKAGE_PIN AC17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[53]}]
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[54]}]
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[55]}]
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[6]}]
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[6]}]
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[6]}]
## Byte lane #7
set_property -dict {PACKAGE_PIN W15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[56]}]
set_property -dict {PACKAGE_PIN W16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[57]}]
set_property -dict {PACKAGE_PIN W14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[58]}]
set_property -dict {PACKAGE_PIN V16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[59]}]
set_property -dict {PACKAGE_PIN V19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[60]}]
set_property -dict {PACKAGE_PIN V17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[61]}]
set_property -dict {PACKAGE_PIN V18 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[62]}]
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[63]}]
set_property -dict {PACKAGE_PIN V14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[7]}]
set_property -dict {PACKAGE_PIN W18 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[7]}]
set_property -dict {PACKAGE_PIN W19 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[7]}]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

55
example_demo/enclustra_kx2_st1/enclustra_ddr3.v
View File

@ -110,25 +110,40 @@
end
wire clk_locked;
wire i_ddr3_clk_90;
clk_wiz clk_wiz_inst
// PLL
// clk_wiz clk_wiz_inst
// (
// // Clock out ports
// .clk_out1(i_controller_clk), // 166 Mhz
// .clk_out2(i_ddr3_clk), // 1333 MHz
// .clk_out3(i_ref_clk), // 200 MHz
// // Status and control signals
// .reset(!i_rst_n),
// .locked(clk_locked),
// // Clock in ports
// .clk_in1(sys_clk_200MHz)
// );
// Clock Wizard
wire clkfb_out;
clk_wiz_0 clk_wiz_inst
(
// Clock out ports
.clk_out1(i_controller_clk), //83.333 Mhz
.clk_out2(i_ddr3_clk), // 333.333 MHz
.clk_out3(i_ref_clk), // 200 MHz
.clk_out4(i_ddr3_clk_90), // 333.333 MHz with 90 degrees shift
// Status and control signals
.reset(!i_rst_n),
.locked(clk_locked),
// Clock in ports
.clk_in1(sys_clk_200MHz)
// Clock out ports
.controller_clk(i_controller_clk),
.ddr3_clk(i_ddr3_clk),
.ref200_clk(i_ref_clk),
// Status and control signals
.reset(!i_rst_n),
.locked(clk_locked),
// Clock in ports
.clk_in1(sys_clk_200MHz)
);
// UART TX/RX module from https://github.com/ben-marshall/uart
uart_tx #(
.BIT_RATE(9600),
.CLK_HZ(83_333_333),
.CLK_HZ(200_000_000),
.PAYLOAD_BITS(8),
.STOP_BITS(1)
) uart_tx_inst (
@ -141,7 +156,7 @@
);
uart_rx #(
.BIT_RATE(9600),
.CLK_HZ(83_333_333),
.CLK_HZ(200_000_000),
.PAYLOAD_BITS(8),
.STOP_BITS(1)
) uart_rx_inst (
@ -173,8 +188,8 @@
// DDR3 Controller
ddr3_top #(
.CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.CONTROLLER_CLK_PERIOD(5_000), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(1_250), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.ROW_BITS(15), //width of row address
.COL_BITS(10), //width of column address
.BA_BITS(3), //width of bank address
@ -192,8 +207,8 @@
//clock and reset
.i_controller_clk(i_controller_clk),
.i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD
.i_ref_clk(i_ref_clk),
.i_ddr3_clk_90(i_ddr3_clk_90),
.i_ref_clk(i_ref_clk/*sys_clk_200MHz*/),
.i_ddr3_clk_90(),
.i_rst_n(i_rst_n && clk_locked),
// Wishbone inputs
.i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
@ -236,9 +251,7 @@
.io_ddr3_dqs_n(ddr3_dqs_n),
.o_ddr3_dm(ddr3_dm),
.o_ddr3_odt(ddr3_odt), // on-die termination
.o_debug1(o_debug1),
.o_debug2(),
.o_debug3()
.o_debug1(o_debug1)
);
endmodule

322
example_demo/enclustra_kx2_st1/enclustra_ddr3.xdc
View File

@ -2,733 +2,724 @@
# IO constraints
################################################################################
# cpu_reset_n:0
set_property LOC C22 [get_ports {i_rst_n}]
set_property IOSTANDARD LVCMOS18 [get_ports {i_rst_n}]
set_property PACKAGE_PIN C22 [get_ports i_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports i_rst_n]
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports btn]
# clk200:0.p
set_property LOC AB11 [get_ports {i_clk200_p}]
set_property IOSTANDARD LVDS [get_ports {i_clk200_p}]
set_property IOSTANDARD LVDS [get_ports i_clk200_p]
# clk200:0.n
set_property LOC AC11 [get_ports {i_clk200_n}]
set_property IOSTANDARD LVDS [get_ports {i_clk200_n}]
set_property PACKAGE_PIN AB11 [get_ports i_clk200_p]
set_property PACKAGE_PIN AC11 [get_ports i_clk200_n]
set_property IOSTANDARD LVDS [get_ports i_clk200_n]
# serial:0.tx
set_property LOC A20 [get_ports {tx}]
set_property IOSTANDARD LVCMOS18 [get_ports {tx}]
set_property PACKAGE_PIN A20 [get_ports tx]
set_property IOSTANDARD LVCMOS18 [get_ports tx]
# serial:0.rx
set_property LOC B20 [get_ports {rx}]
set_property IOSTANDARD LVCMOS18 [get_ports {rx}]
set_property PACKAGE_PIN B20 [get_ports rx]
set_property IOSTANDARD LVCMOS18 [get_ports rx]
# ddram:0.a
set_property LOC AE11 [get_ports {ddr3_addr[0]}]
set_property PACKAGE_PIN AE11 [get_ports {ddr3_addr[0]}]
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
# ddram:0.a
set_property LOC AF9 [get_ports {ddr3_addr[1]}]
set_property PACKAGE_PIN AF9 [get_ports {ddr3_addr[1]}]
set_property SLEW FAST [get_ports {ddr3_addr[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
# ddram:0.a
set_property LOC AD10 [get_ports {ddr3_addr[2]}]
set_property PACKAGE_PIN AD10 [get_ports {ddr3_addr[2]}]
set_property SLEW FAST [get_ports {ddr3_addr[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
# ddram:0.a
set_property LOC AB10 [get_ports {ddr3_addr[3]}]
set_property PACKAGE_PIN AB10 [get_ports {ddr3_addr[3]}]
set_property SLEW FAST [get_ports {ddr3_addr[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
# ddram:0.a
set_property LOC AA9 [get_ports {ddr3_addr[4]}]
set_property PACKAGE_PIN AA9 [get_ports {ddr3_addr[4]}]
set_property SLEW FAST [get_ports {ddr3_addr[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
# ddram:0.a
set_property LOC AB9 [get_ports {ddr3_addr[5]}]
set_property PACKAGE_PIN AB9 [get_ports {ddr3_addr[5]}]
set_property SLEW FAST [get_ports {ddr3_addr[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
# ddram:0.a
set_property LOC AA8 [get_ports {ddr3_addr[6]}]
set_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[6]}]
set_property SLEW FAST [get_ports {ddr3_addr[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
# ddram:0.a
set_property LOC AC8 [get_ports {ddr3_addr[7]}]
set_property PACKAGE_PIN AC8 [get_ports {ddr3_addr[7]}]
set_property SLEW FAST [get_ports {ddr3_addr[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
# ddram:0.a
set_property LOC AA7 [get_ports {ddr3_addr[8]}]
set_property PACKAGE_PIN AA7 [get_ports {ddr3_addr[8]}]
set_property SLEW FAST [get_ports {ddr3_addr[8]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
# ddram:0.a
set_property LOC AE8 [get_ports {ddr3_addr[9]}]
set_property PACKAGE_PIN AE8 [get_ports {ddr3_addr[9]}]
set_property SLEW FAST [get_ports {ddr3_addr[9]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
# ddram:0.a
set_property LOC AF10 [get_ports {ddr3_addr[10]}]
set_property PACKAGE_PIN AF10 [get_ports {ddr3_addr[10]}]
set_property SLEW FAST [get_ports {ddr3_addr[10]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
# ddram:0.a
set_property LOC AD8 [get_ports {ddr3_addr[11]}]
set_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[11]}]
set_property SLEW FAST [get_ports {ddr3_addr[11]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
# ddram:0.a
set_property LOC AE10 [get_ports {ddr3_addr[12]}]
set_property PACKAGE_PIN AE10 [get_ports {ddr3_addr[12]}]
set_property SLEW FAST [get_ports {ddr3_addr[12]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
# ddram:0.a
set_property LOC AF8 [get_ports {ddr3_addr[13]}]
set_property PACKAGE_PIN AF8 [get_ports {ddr3_addr[13]}]
set_property SLEW FAST [get_ports {ddr3_addr[13]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
# ddram:0.a
set_property LOC AC7 [get_ports {ddr3_addr[14]}]
set_property PACKAGE_PIN AC7 [get_ports {ddr3_addr[14]}]
set_property SLEW FAST [get_ports {ddr3_addr[14]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
# ddram:0.ba
set_property LOC AD11 [get_ports {ddr3_ba[0]}]
set_property PACKAGE_PIN AD11 [get_ports {ddr3_ba[0]}]
set_property SLEW FAST [get_ports {ddr3_ba[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
# ddram:0.ba
set_property LOC AA10 [get_ports {ddr3_ba[1]}]
set_property PACKAGE_PIN AA10 [get_ports {ddr3_ba[1]}]
set_property SLEW FAST [get_ports {ddr3_ba[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
# ddram:0.ba
set_property LOC AF12 [get_ports {ddr3_ba[2]}]
set_property PACKAGE_PIN AF12 [get_ports {ddr3_ba[2]}]
set_property SLEW FAST [get_ports {ddr3_ba[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
# ddram:0.ras_n
set_property LOC AE13 [get_ports {ddr3_ras_n}]
set_property SLEW FAST [get_ports {ddr3_ras_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_ras_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]
set_property PACKAGE_PIN AE13 [get_ports ddr3_ras_n]
set_property SLEW FAST [get_ports ddr3_ras_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_ras_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n]
# ddram:0.cas_n
set_property LOC AE12 [get_ports {ddr3_cas_n}]
set_property SLEW FAST [get_ports {ddr3_cas_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_cas_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]
set_property PACKAGE_PIN AE12 [get_ports ddr3_cas_n]
set_property SLEW FAST [get_ports ddr3_cas_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_cas_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n]
# ddram:0.we_n
set_property LOC AA12 [get_ports {ddr3_we_n}]
set_property SLEW FAST [get_ports {ddr3_we_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_we_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]
set_property PACKAGE_PIN AA12 [get_ports ddr3_we_n]
set_property SLEW FAST [get_ports ddr3_we_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_we_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n]
# ddram:0.cs_n
set_property LOC Y12 [get_ports {ddr3_cs_n}]
set_property SLEW FAST [get_ports {ddr3_cs_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_cs_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n}]
set_property PACKAGE_PIN Y12 [get_ports ddr3_cs_n]
set_property SLEW FAST [get_ports ddr3_cs_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_cs_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_cs_n]
# ddram:0.dm
set_property LOC Y3 [get_ports {ddr3_dm[0]}]
set_property PACKAGE_PIN Y3 [get_ports {ddr3_dm[0]}]
set_property SLEW FAST [get_ports {ddr3_dm[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
# ddram:0.dm
set_property LOC U5 [get_ports {ddr3_dm[1]}]
set_property PACKAGE_PIN U5 [get_ports {ddr3_dm[1]}]
set_property SLEW FAST [get_ports {ddr3_dm[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
# ddram:0.dm
set_property LOC AD4 [get_ports {ddr3_dm[2]}]
set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[2]}]
set_property SLEW FAST [get_ports {ddr3_dm[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
# ddram:0.dm
set_property LOC AC4 [get_ports {ddr3_dm[3]}]
set_property PACKAGE_PIN AC4 [get_ports {ddr3_dm[3]}]
set_property SLEW FAST [get_ports {ddr3_dm[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
# ddram:0.dm
set_property LOC AF19 [get_ports {ddr3_dm[4]}]
set_property PACKAGE_PIN AF19 [get_ports {ddr3_dm[4]}]
set_property SLEW FAST [get_ports {ddr3_dm[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[4]}]
# ddram:0.dm
set_property LOC AC16 [get_ports {ddr3_dm[5]}]
set_property PACKAGE_PIN AC16 [get_ports {ddr3_dm[5]}]
set_property SLEW FAST [get_ports {ddr3_dm[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[5]}]
# ddram:0.dm
set_property LOC AB19 [get_ports {ddr3_dm[6]}]
set_property PACKAGE_PIN AB19 [get_ports {ddr3_dm[6]}]
set_property SLEW FAST [get_ports {ddr3_dm[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[6]}]
# ddram:0.dm
set_property LOC V14 [get_ports {ddr3_dm[7]}]
set_property PACKAGE_PIN V14 [get_ports {ddr3_dm[7]}]
set_property SLEW FAST [get_ports {ddr3_dm[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[7]}]
# ddram:0.dq
set_property LOC AA2 [get_ports {ddr3_dq[0]}]
set_property PACKAGE_PIN AA2 [get_ports {ddr3_dq[0]}]
set_property SLEW FAST [get_ports {ddr3_dq[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
# ddram:0.dq
set_property LOC Y2 [get_ports {ddr3_dq[1]}]
set_property PACKAGE_PIN Y2 [get_ports {ddr3_dq[1]}]
set_property SLEW FAST [get_ports {ddr3_dq[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
# ddram:0.dq
set_property LOC AB2 [get_ports {ddr3_dq[2]}]
set_property PACKAGE_PIN AB2 [get_ports {ddr3_dq[2]}]
set_property SLEW FAST [get_ports {ddr3_dq[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
# ddram:0.dq
set_property LOC V1 [get_ports {ddr3_dq[3]}]
set_property PACKAGE_PIN V1 [get_ports {ddr3_dq[3]}]
set_property SLEW FAST [get_ports {ddr3_dq[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
# ddram:0.dq
set_property LOC Y1 [get_ports {ddr3_dq[4]}]
set_property PACKAGE_PIN Y1 [get_ports {ddr3_dq[4]}]
set_property SLEW FAST [get_ports {ddr3_dq[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
# ddram:0.dq
set_property LOC W1 [get_ports {ddr3_dq[5]}]
set_property PACKAGE_PIN W1 [get_ports {ddr3_dq[5]}]
set_property SLEW FAST [get_ports {ddr3_dq[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
# ddram:0.dq
set_property LOC AC2 [get_ports {ddr3_dq[6]}]
set_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[6]}]
set_property SLEW FAST [get_ports {ddr3_dq[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
# ddram:0.dq
set_property LOC V2 [get_ports {ddr3_dq[7]}]
set_property PACKAGE_PIN V2 [get_ports {ddr3_dq[7]}]
set_property SLEW FAST [get_ports {ddr3_dq[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
# ddram:0.dq
set_property LOC W3 [get_ports {ddr3_dq[8]}]
set_property PACKAGE_PIN W3 [get_ports {ddr3_dq[8]}]
set_property SLEW FAST [get_ports {ddr3_dq[8]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
# ddram:0.dq
set_property LOC V3 [get_ports {ddr3_dq[9]}]
set_property PACKAGE_PIN V3 [get_ports {ddr3_dq[9]}]
set_property SLEW FAST [get_ports {ddr3_dq[9]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
# ddram:0.dq
set_property LOC U1 [get_ports {ddr3_dq[10]}]
set_property PACKAGE_PIN U1 [get_ports {ddr3_dq[10]}]
set_property SLEW FAST [get_ports {ddr3_dq[10]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
# ddram:0.dq
set_property LOC U7 [get_ports {ddr3_dq[11]}]
set_property PACKAGE_PIN U7 [get_ports {ddr3_dq[11]}]
set_property SLEW FAST [get_ports {ddr3_dq[11]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
# ddram:0.dq
set_property LOC U6 [get_ports {ddr3_dq[12]}]
set_property PACKAGE_PIN U6 [get_ports {ddr3_dq[12]}]
set_property SLEW FAST [get_ports {ddr3_dq[12]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
# ddram:0.dq
set_property LOC V4 [get_ports {ddr3_dq[13]}]
set_property PACKAGE_PIN V4 [get_ports {ddr3_dq[13]}]
set_property SLEW FAST [get_ports {ddr3_dq[13]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
# ddram:0.dq
set_property LOC V6 [get_ports {ddr3_dq[14]}]
set_property PACKAGE_PIN V6 [get_ports {ddr3_dq[14]}]
set_property SLEW FAST [get_ports {ddr3_dq[14]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
# ddram:0.dq
set_property LOC U2 [get_ports {ddr3_dq[15]}]
set_property PACKAGE_PIN U2 [get_ports {ddr3_dq[15]}]
set_property SLEW FAST [get_ports {ddr3_dq[15]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
# ddram:0.dq
set_property LOC AE3 [get_ports {ddr3_dq[16]}]
set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[16]}]
set_property SLEW FAST [get_ports {ddr3_dq[16]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[16]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}]
# ddram:0.dq
set_property LOC AE6 [get_ports {ddr3_dq[17]}]
set_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[17]}]
set_property SLEW FAST [get_ports {ddr3_dq[17]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[17]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}]
# ddram:0.dq
set_property LOC AF3 [get_ports {ddr3_dq[18]}]
set_property PACKAGE_PIN AF3 [get_ports {ddr3_dq[18]}]
set_property SLEW FAST [get_ports {ddr3_dq[18]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[18]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}]
# ddram:0.dq
set_property LOC AD1 [get_ports {ddr3_dq[19]}]
set_property PACKAGE_PIN AD1 [get_ports {ddr3_dq[19]}]
set_property SLEW FAST [get_ports {ddr3_dq[19]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[19]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}]
# ddram:0.dq
set_property LOC AE1 [get_ports {ddr3_dq[20]}]
set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[20]}]
set_property SLEW FAST [get_ports {ddr3_dq[20]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[20]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}]
# ddram:0.dq
set_property LOC AE2 [get_ports {ddr3_dq[21]}]
set_property PACKAGE_PIN AE2 [get_ports {ddr3_dq[21]}]
set_property SLEW FAST [get_ports {ddr3_dq[21]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[21]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}]
# ddram:0.dq
set_property LOC AF2 [get_ports {ddr3_dq[22]}]
set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[22]}]
set_property SLEW FAST [get_ports {ddr3_dq[22]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[22]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}]
# ddram:0.dq
set_property LOC AE5 [get_ports {ddr3_dq[23]}]
set_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[23]}]
set_property SLEW FAST [get_ports {ddr3_dq[23]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[23]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}]
# ddram:0.dq
set_property LOC AD5 [get_ports {ddr3_dq[24]}]
set_property PACKAGE_PIN AD5 [get_ports {ddr3_dq[24]}]
set_property SLEW FAST [get_ports {ddr3_dq[24]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[24]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}]
# ddram:0.dq
set_property LOC Y5 [get_ports {ddr3_dq[25]}]
set_property PACKAGE_PIN Y5 [get_ports {ddr3_dq[25]}]
set_property SLEW FAST [get_ports {ddr3_dq[25]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[25]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}]
# ddram:0.dq
set_property LOC AC6 [get_ports {ddr3_dq[26]}]
set_property PACKAGE_PIN AC6 [get_ports {ddr3_dq[26]}]
set_property SLEW FAST [get_ports {ddr3_dq[26]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[26]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}]
# ddram:0.dq
set_property LOC Y6 [get_ports {ddr3_dq[27]}]
set_property PACKAGE_PIN Y6 [get_ports {ddr3_dq[27]}]
set_property SLEW FAST [get_ports {ddr3_dq[27]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[27]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}]
# ddram:0.dq
set_property LOC AB4 [get_ports {ddr3_dq[28]}]
set_property PACKAGE_PIN AB4 [get_ports {ddr3_dq[28]}]
set_property SLEW FAST [get_ports {ddr3_dq[28]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[28]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}]
# ddram:0.dq
set_property LOC AD6 [get_ports {ddr3_dq[29]}]
set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[29]}]
set_property SLEW FAST [get_ports {ddr3_dq[29]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[29]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}]
# ddram:0.dq
set_property LOC AB6 [get_ports {ddr3_dq[30]}]
set_property PACKAGE_PIN AB6 [get_ports {ddr3_dq[30]}]
set_property SLEW FAST [get_ports {ddr3_dq[30]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[30]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}]
# ddram:0.dq
set_property LOC AC3 [get_ports {ddr3_dq[31]}]
set_property PACKAGE_PIN AC3 [get_ports {ddr3_dq[31]}]
set_property SLEW FAST [get_ports {ddr3_dq[31]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[31]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}]
# ddram:0.dq
set_property LOC AD16 [get_ports {ddr3_dq[32]}]
set_property PACKAGE_PIN AD16 [get_ports {ddr3_dq[32]}]
set_property SLEW FAST [get_ports {ddr3_dq[32]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[32]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[32]}]
# ddram:0.dq
set_property LOC AE17 [get_ports {ddr3_dq[33]}]
set_property PACKAGE_PIN AE17 [get_ports {ddr3_dq[33]}]
set_property SLEW FAST [get_ports {ddr3_dq[33]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[33]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[33]}]
# ddram:0.dq
set_property LOC AF15 [get_ports {ddr3_dq[34]}]
set_property PACKAGE_PIN AF15 [get_ports {ddr3_dq[34]}]
set_property SLEW FAST [get_ports {ddr3_dq[34]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[34]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[34]}]
# ddram:0.dq
set_property LOC AF20 [get_ports {ddr3_dq[35]}]
set_property PACKAGE_PIN AF20 [get_ports {ddr3_dq[35]}]
set_property SLEW FAST [get_ports {ddr3_dq[35]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[35]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[35]}]
# ddram:0.dq
set_property LOC AD15 [get_ports {ddr3_dq[36]}]
set_property PACKAGE_PIN AD15 [get_ports {ddr3_dq[36]}]
set_property SLEW FAST [get_ports {ddr3_dq[36]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[36]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[36]}]
# ddram:0.dq
set_property LOC AF14 [get_ports {ddr3_dq[37]}]
set_property PACKAGE_PIN AF14 [get_ports {ddr3_dq[37]}]
set_property SLEW FAST [get_ports {ddr3_dq[37]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[37]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[37]}]
# ddram:0.dq
set_property LOC AE15 [get_ports {ddr3_dq[38]}]
set_property PACKAGE_PIN AE15 [get_ports {ddr3_dq[38]}]
set_property SLEW FAST [get_ports {ddr3_dq[38]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[38]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[38]}]
# ddram:0.dq
set_property LOC AF17 [get_ports {ddr3_dq[39]}]
set_property PACKAGE_PIN AF17 [get_ports {ddr3_dq[39]}]
set_property SLEW FAST [get_ports {ddr3_dq[39]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[39]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[39]}]
# ddram:0.dq
set_property LOC AA14 [get_ports {ddr3_dq[40]}]
set_property PACKAGE_PIN AA14 [get_ports {ddr3_dq[40]}]
set_property SLEW FAST [get_ports {ddr3_dq[40]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[40]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[40]}]
# ddram:0.dq
set_property LOC AA15 [get_ports {ddr3_dq[41]}]
set_property PACKAGE_PIN AA15 [get_ports {ddr3_dq[41]}]
set_property SLEW FAST [get_ports {ddr3_dq[41]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[41]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[41]}]
# ddram:0.dq
set_property LOC AC14 [get_ports {ddr3_dq[42]}]
set_property PACKAGE_PIN AC14 [get_ports {ddr3_dq[42]}]
set_property SLEW FAST [get_ports {ddr3_dq[42]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[42]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[42]}]
# ddram:0.dq
set_property LOC AD14 [get_ports {ddr3_dq[43]}]
set_property PACKAGE_PIN AD14 [get_ports {ddr3_dq[43]}]
set_property SLEW FAST [get_ports {ddr3_dq[43]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[43]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[43]}]
# ddram:0.dq
set_property LOC AB14 [get_ports {ddr3_dq[44]}]
set_property PACKAGE_PIN AB14 [get_ports {ddr3_dq[44]}]
set_property SLEW FAST [get_ports {ddr3_dq[44]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[44]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[44]}]
# ddram:0.dq
set_property LOC AB15 [get_ports {ddr3_dq[45]}]
set_property PACKAGE_PIN AB15 [get_ports {ddr3_dq[45]}]
set_property SLEW FAST [get_ports {ddr3_dq[45]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[45]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[45]}]
# ddram:0.dq
set_property LOC AA17 [get_ports {ddr3_dq[46]}]
set_property PACKAGE_PIN AA17 [get_ports {ddr3_dq[46]}]
set_property SLEW FAST [get_ports {ddr3_dq[46]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[46]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[46]}]
# ddram:0.dq
set_property LOC AA18 [get_ports {ddr3_dq[47]}]
set_property PACKAGE_PIN AA18 [get_ports {ddr3_dq[47]}]
set_property SLEW FAST [get_ports {ddr3_dq[47]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[47]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[47]}]
# ddram:0.dq
set_property LOC AB20 [get_ports {ddr3_dq[48]}]
set_property PACKAGE_PIN AB20 [get_ports {ddr3_dq[48]}]
set_property SLEW FAST [get_ports {ddr3_dq[48]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[48]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[48]}]
# ddram:0.dq
set_property LOC AD19 [get_ports {ddr3_dq[49]}]
set_property PACKAGE_PIN AD19 [get_ports {ddr3_dq[49]}]
set_property SLEW FAST [get_ports {ddr3_dq[49]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[49]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[49]}]
# ddram:0.dq
set_property LOC AC19 [get_ports {ddr3_dq[50]}]
set_property PACKAGE_PIN AC19 [get_ports {ddr3_dq[50]}]
set_property SLEW FAST [get_ports {ddr3_dq[50]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[50]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[50]}]
# ddram:0.dq
set_property LOC AA20 [get_ports {ddr3_dq[51]}]
set_property PACKAGE_PIN AA20 [get_ports {ddr3_dq[51]}]
set_property SLEW FAST [get_ports {ddr3_dq[51]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[51]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[51]}]
# ddram:0.dq
set_property LOC AA19 [get_ports {ddr3_dq[52]}]
set_property PACKAGE_PIN AA19 [get_ports {ddr3_dq[52]}]
set_property SLEW FAST [get_ports {ddr3_dq[52]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[52]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[52]}]
# ddram:0.dq
set_property LOC AC17 [get_ports {ddr3_dq[53]}]
set_property PACKAGE_PIN AC17 [get_ports {ddr3_dq[53]}]
set_property SLEW FAST [get_ports {ddr3_dq[53]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[53]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[53]}]
# ddram:0.dq
set_property LOC AD18 [get_ports {ddr3_dq[54]}]
set_property PACKAGE_PIN AD18 [get_ports {ddr3_dq[54]}]
set_property SLEW FAST [get_ports {ddr3_dq[54]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[54]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[54]}]
# ddram:0.dq
set_property LOC AB17 [get_ports {ddr3_dq[55]}]
set_property PACKAGE_PIN AB17 [get_ports {ddr3_dq[55]}]
set_property SLEW FAST [get_ports {ddr3_dq[55]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[55]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[55]}]
# ddram:0.dq
set_property LOC W15 [get_ports {ddr3_dq[56]}]
set_property PACKAGE_PIN W15 [get_ports {ddr3_dq[56]}]
set_property SLEW FAST [get_ports {ddr3_dq[56]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[56]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[56]}]
# ddram:0.dq
set_property LOC W16 [get_ports {ddr3_dq[57]}]
set_property PACKAGE_PIN W16 [get_ports {ddr3_dq[57]}]
set_property SLEW FAST [get_ports {ddr3_dq[57]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[57]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[57]}]
# ddram:0.dq
set_property LOC W14 [get_ports {ddr3_dq[58]}]
set_property PACKAGE_PIN W14 [get_ports {ddr3_dq[58]}]
set_property SLEW FAST [get_ports {ddr3_dq[58]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[58]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[58]}]
# ddram:0.dq
set_property LOC V16 [get_ports {ddr3_dq[59]}]
set_property PACKAGE_PIN V16 [get_ports {ddr3_dq[59]}]
set_property SLEW FAST [get_ports {ddr3_dq[59]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[59]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[59]}]
# ddram:0.dq
set_property LOC V19 [get_ports {ddr3_dq[60]}]
set_property PACKAGE_PIN V19 [get_ports {ddr3_dq[60]}]
set_property SLEW FAST [get_ports {ddr3_dq[60]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[60]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[60]}]
# ddram:0.dq
set_property LOC V17 [get_ports {ddr3_dq[61]}]
set_property PACKAGE_PIN V17 [get_ports {ddr3_dq[61]}]
set_property SLEW FAST [get_ports {ddr3_dq[61]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[61]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[61]}]
# ddram:0.dq
set_property LOC V18 [get_ports {ddr3_dq[62]}]
set_property PACKAGE_PIN V18 [get_ports {ddr3_dq[62]}]
set_property SLEW FAST [get_ports {ddr3_dq[62]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[62]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[62]}]
# ddram:0.dq
set_property LOC Y17 [get_ports {ddr3_dq[63]}]
set_property PACKAGE_PIN Y17 [get_ports {ddr3_dq[63]}]
set_property SLEW FAST [get_ports {ddr3_dq[63]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[63]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[63]}]
# ddram:0.dqs_p
set_property LOC AB1 [get_ports {ddr3_dqs_p[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}]
# ddram:0.dqs_p
set_property LOC W6 [get_ports {ddr3_dqs_p[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}]
# ddram:0.dqs_p
set_property LOC AF5 [get_ports {ddr3_dqs_p[2]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[2]}]
# ddram:0.dqs_p
set_property LOC AA5 [get_ports {ddr3_dqs_p[3]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[3]}]
# ddram:0.dqs_p
set_property LOC AE18 [get_ports {ddr3_dqs_p[4]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[4]}]
# ddram:0.dqs_p
set_property LOC Y15 [get_ports {ddr3_dqs_p[5]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[5]}]
# ddram:0.dqs_p
set_property LOC AD20 [get_ports {ddr3_dqs_p[6]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[6]}]
# ddram:0.dqs_p
set_property LOC W18 [get_ports {ddr3_dqs_p[7]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[7]}]
# ddram:0.dqs_n
set_property LOC AC1 [get_ports {ddr3_dqs_n[0]}]
set_property PACKAGE_PIN AB1 [get_ports {ddr3_dqs_p[0]}]
set_property PACKAGE_PIN AC1 [get_ports {ddr3_dqs_n[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}]
# ddram:0.dqs_n
set_property LOC W5 [get_ports {ddr3_dqs_n[1]}]
set_property PACKAGE_PIN W6 [get_ports {ddr3_dqs_p[1]}]
set_property PACKAGE_PIN W5 [get_ports {ddr3_dqs_n[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}]
# ddram:0.dqs_n
set_property LOC AF4 [get_ports {ddr3_dqs_n[2]}]
set_property PACKAGE_PIN AF5 [get_ports {ddr3_dqs_p[2]}]
set_property PACKAGE_PIN AF4 [get_ports {ddr3_dqs_n[2]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[2]}]
# ddram:0.dqs_n
set_property LOC AB5 [get_ports {ddr3_dqs_n[3]}]
set_property PACKAGE_PIN AA5 [get_ports {ddr3_dqs_p[3]}]
set_property PACKAGE_PIN AB5 [get_ports {ddr3_dqs_n[3]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[3]}]
# ddram:0.dqs_n
set_property LOC AF18 [get_ports {ddr3_dqs_n[4]}]
set_property PACKAGE_PIN AE18 [get_ports {ddr3_dqs_p[4]}]
set_property PACKAGE_PIN AF18 [get_ports {ddr3_dqs_n[4]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[4]}]
# ddram:0.dqs_n
set_property LOC Y16 [get_ports {ddr3_dqs_n[5]}]
set_property PACKAGE_PIN Y15 [get_ports {ddr3_dqs_p[5]}]
set_property PACKAGE_PIN Y16 [get_ports {ddr3_dqs_n[5]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[5]}]
# ddram:0.dqs_n
set_property LOC AE20 [get_ports {ddr3_dqs_n[6]}]
set_property PACKAGE_PIN AD20 [get_ports {ddr3_dqs_p[6]}]
set_property PACKAGE_PIN AE20 [get_ports {ddr3_dqs_n[6]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[6]}]
# ddram:0.dqs_n
set_property LOC W19 [get_ports {ddr3_dqs_n[7]}]
set_property PACKAGE_PIN W18 [get_ports {ddr3_dqs_p[7]}]
set_property PACKAGE_PIN W19 [get_ports {ddr3_dqs_n[7]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[7]}]
# ddram:0.clk_p
set_property LOC AB12 [get_ports {ddr3_clk_p}]
set_property SLEW FAST [get_ports {ddr3_clk_p}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_clk_p}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_clk_p}]
set_property SLEW FAST [get_ports ddr3_clk_p]
set_property VCCAUX_IO HIGH [get_ports ddr3_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr3_clk_p]
# ddram:0.clk_n
set_property LOC AC12 [get_ports {ddr3_clk_n}]
set_property SLEW FAST [get_ports {ddr3_clk_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_clk_n}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_clk_n}]
set_property PACKAGE_PIN AB12 [get_ports ddr3_clk_p]
set_property PACKAGE_PIN AC12 [get_ports ddr3_clk_n]
set_property SLEW FAST [get_ports ddr3_clk_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr3_clk_n]
# ddram:0.cke
set_property LOC AA13 [get_ports {ddr3_cke}]
set_property SLEW FAST [get_ports {ddr3_cke}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_cke}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke}]
set_property PACKAGE_PIN AA13 [get_ports ddr3_cke]
set_property SLEW FAST [get_ports ddr3_cke]
set_property VCCAUX_IO HIGH [get_ports ddr3_cke]
set_property IOSTANDARD SSTL15 [get_ports ddr3_cke]
# ddram:0.odt
set_property LOC AD13 [get_ports {ddr3_odt}]
set_property SLEW FAST [get_ports {ddr3_odt}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_odt}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt}]
set_property PACKAGE_PIN AD13 [get_ports ddr3_odt]
set_property SLEW FAST [get_ports ddr3_odt]
set_property VCCAUX_IO HIGH [get_ports ddr3_odt]
set_property IOSTANDARD SSTL15 [get_ports ddr3_odt]
# ddram:0.reset_n
set_property LOC AB7 [get_ports {ddr3_reset_n}]
set_property SLEW FAST [get_ports {ddr3_reset_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_reset_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_reset_n}]
set_property SLEW SLOW [get_ports {ddr3_reset_n}]
set_property PACKAGE_PIN AB7 [get_ports ddr3_reset_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_reset_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_reset_n]
set_property SLEW SLOW [get_ports ddr3_reset_n]
# user_led:0
set_property LOC U9 [get_ports {led[0]}]
set_property PACKAGE_PIN U9 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[0]}]
set_property SLEW SLOW [get_ports {led[0]}]
# user_led:1
set_property LOC V12 [get_ports {led[1]}]
set_property PACKAGE_PIN V12 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[1]}]
set_property SLEW SLOW [get_ports {led[1]}]
# user_led:2
set_property LOC V13 [get_ports {led[2]}]
set_property PACKAGE_PIN V13 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[2]}]
set_property SLEW SLOW [get_ports {led[2]}]
# user_led:3
set_property LOC W13 [get_ports {led[3]}]
set_property PACKAGE_PIN W13 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[3]}]
set_property SLEW SLOW [get_ports {led[3]}]
@ -747,4 +738,3 @@ set_property CFGBVS GND [current_design]
################################################################################
create_clock -name i_clk200_p -period 5.0 [get_ports i_clk200_p]

740
example_demo/enclustra_kx2_st1/enclustra_mb.xdc Executable file
View File

@ -0,0 +1,740 @@
################################################################################
# IO constraints
################################################################################
# cpu_reset_n:0
set_property PACKAGE_PIN C22 [get_ports i_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports i_rst_n]
# set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports btn]
# clk200:0.p
set_property IOSTANDARD LVDS [get_ports i_clk200_clk_p]
# clk200:0.n
set_property PACKAGE_PIN AB11 [get_ports i_clk200_clk_p]
set_property PACKAGE_PIN AC11 [get_ports i_clk200_clk_n]
set_property IOSTANDARD LVDS [get_ports i_clk200_clk_n]
# serial:0.tx
set_property PACKAGE_PIN A20 [get_ports uart_txd]
set_property IOSTANDARD LVCMOS18 [get_ports uart_txd]
# serial:0.rx
set_property PACKAGE_PIN B20 [get_ports uart_rxd]
set_property IOSTANDARD LVCMOS18 [get_ports uart_rxd]
# ddram:0.a
set_property PACKAGE_PIN AE11 [get_ports {ddr3_addr[0]}]
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
# ddram:0.a
set_property PACKAGE_PIN AF9 [get_ports {ddr3_addr[1]}]
set_property SLEW FAST [get_ports {ddr3_addr[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
# ddram:0.a
set_property PACKAGE_PIN AD10 [get_ports {ddr3_addr[2]}]
set_property SLEW FAST [get_ports {ddr3_addr[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
# ddram:0.a
set_property PACKAGE_PIN AB10 [get_ports {ddr3_addr[3]}]
set_property SLEW FAST [get_ports {ddr3_addr[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
# ddram:0.a
set_property PACKAGE_PIN AA9 [get_ports {ddr3_addr[4]}]
set_property SLEW FAST [get_ports {ddr3_addr[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
# ddram:0.a
set_property PACKAGE_PIN AB9 [get_ports {ddr3_addr[5]}]
set_property SLEW FAST [get_ports {ddr3_addr[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
# ddram:0.a
set_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[6]}]
set_property SLEW FAST [get_ports {ddr3_addr[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
# ddram:0.a
set_property PACKAGE_PIN AC8 [get_ports {ddr3_addr[7]}]
set_property SLEW FAST [get_ports {ddr3_addr[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
# ddram:0.a
set_property PACKAGE_PIN AA7 [get_ports {ddr3_addr[8]}]
set_property SLEW FAST [get_ports {ddr3_addr[8]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
# ddram:0.a
set_property PACKAGE_PIN AE8 [get_ports {ddr3_addr[9]}]
set_property SLEW FAST [get_ports {ddr3_addr[9]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
# ddram:0.a
set_property PACKAGE_PIN AF10 [get_ports {ddr3_addr[10]}]
set_property SLEW FAST [get_ports {ddr3_addr[10]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
# ddram:0.a
set_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[11]}]
set_property SLEW FAST [get_ports {ddr3_addr[11]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
# ddram:0.a
set_property PACKAGE_PIN AE10 [get_ports {ddr3_addr[12]}]
set_property SLEW FAST [get_ports {ddr3_addr[12]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
# ddram:0.a
set_property PACKAGE_PIN AF8 [get_ports {ddr3_addr[13]}]
set_property SLEW FAST [get_ports {ddr3_addr[13]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
# ddram:0.a
set_property PACKAGE_PIN AC7 [get_ports {ddr3_addr[14]}]
set_property SLEW FAST [get_ports {ddr3_addr[14]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
# ddram:0.ba
set_property PACKAGE_PIN AD11 [get_ports {ddr3_ba[0]}]
set_property SLEW FAST [get_ports {ddr3_ba[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
# ddram:0.ba
set_property PACKAGE_PIN AA10 [get_ports {ddr3_ba[1]}]
set_property SLEW FAST [get_ports {ddr3_ba[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
# ddram:0.ba
set_property PACKAGE_PIN AF12 [get_ports {ddr3_ba[2]}]
set_property SLEW FAST [get_ports {ddr3_ba[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
# ddram:0.ras_n
set_property PACKAGE_PIN AE13 [get_ports ddr3_ras_n]
set_property SLEW FAST [get_ports ddr3_ras_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_ras_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n]
# ddram:0.cas_n
set_property PACKAGE_PIN AE12 [get_ports ddr3_cas_n]
set_property SLEW FAST [get_ports ddr3_cas_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_cas_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n]
# ddram:0.we_n
set_property PACKAGE_PIN AA12 [get_ports ddr3_we_n]
set_property SLEW FAST [get_ports ddr3_we_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_we_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n]
# ddram:0.cs_n
set_property PACKAGE_PIN Y12 [get_ports ddr3_cs_n]
set_property SLEW FAST [get_ports ddr3_cs_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_cs_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_cs_n]
# ddram:0.dm
set_property PACKAGE_PIN Y3 [get_ports {ddr3_dm[0]}]
set_property SLEW FAST [get_ports {ddr3_dm[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
# ddram:0.dm
set_property PACKAGE_PIN U5 [get_ports {ddr3_dm[1]}]
set_property SLEW FAST [get_ports {ddr3_dm[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
# ddram:0.dm
set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[2]}]
set_property SLEW FAST [get_ports {ddr3_dm[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
# ddram:0.dm
set_property PACKAGE_PIN AC4 [get_ports {ddr3_dm[3]}]
set_property SLEW FAST [get_ports {ddr3_dm[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
# ddram:0.dm
set_property PACKAGE_PIN AF19 [get_ports {ddr3_dm[4]}]
set_property SLEW FAST [get_ports {ddr3_dm[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[4]}]
# ddram:0.dm
set_property PACKAGE_PIN AC16 [get_ports {ddr3_dm[5]}]
set_property SLEW FAST [get_ports {ddr3_dm[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[5]}]
# ddram:0.dm
set_property PACKAGE_PIN AB19 [get_ports {ddr3_dm[6]}]
set_property SLEW FAST [get_ports {ddr3_dm[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[6]}]
# ddram:0.dm
set_property PACKAGE_PIN V14 [get_ports {ddr3_dm[7]}]
set_property SLEW FAST [get_ports {ddr3_dm[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[7]}]
# ddram:0.dq
set_property PACKAGE_PIN AA2 [get_ports {ddr3_dq[0]}]
set_property SLEW FAST [get_ports {ddr3_dq[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
# ddram:0.dq
set_property PACKAGE_PIN Y2 [get_ports {ddr3_dq[1]}]
set_property SLEW FAST [get_ports {ddr3_dq[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
# ddram:0.dq
set_property PACKAGE_PIN AB2 [get_ports {ddr3_dq[2]}]
set_property SLEW FAST [get_ports {ddr3_dq[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
# ddram:0.dq
set_property PACKAGE_PIN V1 [get_ports {ddr3_dq[3]}]
set_property SLEW FAST [get_ports {ddr3_dq[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
# ddram:0.dq
set_property PACKAGE_PIN Y1 [get_ports {ddr3_dq[4]}]
set_property SLEW FAST [get_ports {ddr3_dq[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
# ddram:0.dq
set_property PACKAGE_PIN W1 [get_ports {ddr3_dq[5]}]
set_property SLEW FAST [get_ports {ddr3_dq[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
# ddram:0.dq
set_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[6]}]
set_property SLEW FAST [get_ports {ddr3_dq[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
# ddram:0.dq
set_property PACKAGE_PIN V2 [get_ports {ddr3_dq[7]}]
set_property SLEW FAST [get_ports {ddr3_dq[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
# ddram:0.dq
set_property PACKAGE_PIN W3 [get_ports {ddr3_dq[8]}]
set_property SLEW FAST [get_ports {ddr3_dq[8]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
# ddram:0.dq
set_property PACKAGE_PIN V3 [get_ports {ddr3_dq[9]}]
set_property SLEW FAST [get_ports {ddr3_dq[9]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
# ddram:0.dq
set_property PACKAGE_PIN U1 [get_ports {ddr3_dq[10]}]
set_property SLEW FAST [get_ports {ddr3_dq[10]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
# ddram:0.dq
set_property PACKAGE_PIN U7 [get_ports {ddr3_dq[11]}]
set_property SLEW FAST [get_ports {ddr3_dq[11]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
# ddram:0.dq
set_property PACKAGE_PIN U6 [get_ports {ddr3_dq[12]}]
set_property SLEW FAST [get_ports {ddr3_dq[12]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
# ddram:0.dq
set_property PACKAGE_PIN V4 [get_ports {ddr3_dq[13]}]
set_property SLEW FAST [get_ports {ddr3_dq[13]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
# ddram:0.dq
set_property PACKAGE_PIN V6 [get_ports {ddr3_dq[14]}]
set_property SLEW FAST [get_ports {ddr3_dq[14]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
# ddram:0.dq
set_property PACKAGE_PIN U2 [get_ports {ddr3_dq[15]}]
set_property SLEW FAST [get_ports {ddr3_dq[15]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
# ddram:0.dq
set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[16]}]
set_property SLEW FAST [get_ports {ddr3_dq[16]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[16]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}]
# ddram:0.dq
set_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[17]}]
set_property SLEW FAST [get_ports {ddr3_dq[17]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[17]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}]
# ddram:0.dq
set_property PACKAGE_PIN AF3 [get_ports {ddr3_dq[18]}]
set_property SLEW FAST [get_ports {ddr3_dq[18]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[18]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}]
# ddram:0.dq
set_property PACKAGE_PIN AD1 [get_ports {ddr3_dq[19]}]
set_property SLEW FAST [get_ports {ddr3_dq[19]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[19]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}]
# ddram:0.dq
set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[20]}]
set_property SLEW FAST [get_ports {ddr3_dq[20]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[20]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}]
# ddram:0.dq
set_property PACKAGE_PIN AE2 [get_ports {ddr3_dq[21]}]
set_property SLEW FAST [get_ports {ddr3_dq[21]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[21]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}]
# ddram:0.dq
set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[22]}]
set_property SLEW FAST [get_ports {ddr3_dq[22]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[22]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}]
# ddram:0.dq
set_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[23]}]
set_property SLEW FAST [get_ports {ddr3_dq[23]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[23]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}]
# ddram:0.dq
set_property PACKAGE_PIN AD5 [get_ports {ddr3_dq[24]}]
set_property SLEW FAST [get_ports {ddr3_dq[24]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[24]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}]
# ddram:0.dq
set_property PACKAGE_PIN Y5 [get_ports {ddr3_dq[25]}]
set_property SLEW FAST [get_ports {ddr3_dq[25]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[25]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}]
# ddram:0.dq
set_property PACKAGE_PIN AC6 [get_ports {ddr3_dq[26]}]
set_property SLEW FAST [get_ports {ddr3_dq[26]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[26]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}]
# ddram:0.dq
set_property PACKAGE_PIN Y6 [get_ports {ddr3_dq[27]}]
set_property SLEW FAST [get_ports {ddr3_dq[27]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[27]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}]
# ddram:0.dq
set_property PACKAGE_PIN AB4 [get_ports {ddr3_dq[28]}]
set_property SLEW FAST [get_ports {ddr3_dq[28]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[28]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}]
# ddram:0.dq
set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[29]}]
set_property SLEW FAST [get_ports {ddr3_dq[29]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[29]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}]
# ddram:0.dq
set_property PACKAGE_PIN AB6 [get_ports {ddr3_dq[30]}]
set_property SLEW FAST [get_ports {ddr3_dq[30]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[30]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}]
# ddram:0.dq
set_property PACKAGE_PIN AC3 [get_ports {ddr3_dq[31]}]
set_property SLEW FAST [get_ports {ddr3_dq[31]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[31]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}]
# ddram:0.dq
set_property PACKAGE_PIN AD16 [get_ports {ddr3_dq[32]}]
set_property SLEW FAST [get_ports {ddr3_dq[32]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[32]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[32]}]
# ddram:0.dq
set_property PACKAGE_PIN AE17 [get_ports {ddr3_dq[33]}]
set_property SLEW FAST [get_ports {ddr3_dq[33]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[33]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[33]}]
# ddram:0.dq
set_property PACKAGE_PIN AF15 [get_ports {ddr3_dq[34]}]
set_property SLEW FAST [get_ports {ddr3_dq[34]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[34]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[34]}]
# ddram:0.dq
set_property PACKAGE_PIN AF20 [get_ports {ddr3_dq[35]}]
set_property SLEW FAST [get_ports {ddr3_dq[35]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[35]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[35]}]
# ddram:0.dq
set_property PACKAGE_PIN AD15 [get_ports {ddr3_dq[36]}]
set_property SLEW FAST [get_ports {ddr3_dq[36]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[36]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[36]}]
# ddram:0.dq
set_property PACKAGE_PIN AF14 [get_ports {ddr3_dq[37]}]
set_property SLEW FAST [get_ports {ddr3_dq[37]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[37]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[37]}]
# ddram:0.dq
set_property PACKAGE_PIN AE15 [get_ports {ddr3_dq[38]}]
set_property SLEW FAST [get_ports {ddr3_dq[38]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[38]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[38]}]
# ddram:0.dq
set_property PACKAGE_PIN AF17 [get_ports {ddr3_dq[39]}]
set_property SLEW FAST [get_ports {ddr3_dq[39]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[39]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[39]}]
# ddram:0.dq
set_property PACKAGE_PIN AA14 [get_ports {ddr3_dq[40]}]
set_property SLEW FAST [get_ports {ddr3_dq[40]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[40]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[40]}]
# ddram:0.dq
set_property PACKAGE_PIN AA15 [get_ports {ddr3_dq[41]}]
set_property SLEW FAST [get_ports {ddr3_dq[41]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[41]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[41]}]
# ddram:0.dq
set_property PACKAGE_PIN AC14 [get_ports {ddr3_dq[42]}]
set_property SLEW FAST [get_ports {ddr3_dq[42]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[42]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[42]}]
# ddram:0.dq
set_property PACKAGE_PIN AD14 [get_ports {ddr3_dq[43]}]
set_property SLEW FAST [get_ports {ddr3_dq[43]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[43]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[43]}]
# ddram:0.dq
set_property PACKAGE_PIN AB14 [get_ports {ddr3_dq[44]}]
set_property SLEW FAST [get_ports {ddr3_dq[44]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[44]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[44]}]
# ddram:0.dq
set_property PACKAGE_PIN AB15 [get_ports {ddr3_dq[45]}]
set_property SLEW FAST [get_ports {ddr3_dq[45]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[45]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[45]}]
# ddram:0.dq
set_property PACKAGE_PIN AA17 [get_ports {ddr3_dq[46]}]
set_property SLEW FAST [get_ports {ddr3_dq[46]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[46]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[46]}]
# ddram:0.dq
set_property PACKAGE_PIN AA18 [get_ports {ddr3_dq[47]}]
set_property SLEW FAST [get_ports {ddr3_dq[47]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[47]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[47]}]
# ddram:0.dq
set_property PACKAGE_PIN AB20 [get_ports {ddr3_dq[48]}]
set_property SLEW FAST [get_ports {ddr3_dq[48]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[48]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[48]}]
# ddram:0.dq
set_property PACKAGE_PIN AD19 [get_ports {ddr3_dq[49]}]
set_property SLEW FAST [get_ports {ddr3_dq[49]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[49]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[49]}]
# ddram:0.dq
set_property PACKAGE_PIN AC19 [get_ports {ddr3_dq[50]}]
set_property SLEW FAST [get_ports {ddr3_dq[50]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[50]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[50]}]
# ddram:0.dq
set_property PACKAGE_PIN AA20 [get_ports {ddr3_dq[51]}]
set_property SLEW FAST [get_ports {ddr3_dq[51]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[51]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[51]}]
# ddram:0.dq
set_property PACKAGE_PIN AA19 [get_ports {ddr3_dq[52]}]
set_property SLEW FAST [get_ports {ddr3_dq[52]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[52]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[52]}]
# ddram:0.dq
set_property PACKAGE_PIN AC17 [get_ports {ddr3_dq[53]}]
set_property SLEW FAST [get_ports {ddr3_dq[53]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[53]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[53]}]
# ddram:0.dq
set_property PACKAGE_PIN AD18 [get_ports {ddr3_dq[54]}]
set_property SLEW FAST [get_ports {ddr3_dq[54]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[54]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[54]}]
# ddram:0.dq
set_property PACKAGE_PIN AB17 [get_ports {ddr3_dq[55]}]
set_property SLEW FAST [get_ports {ddr3_dq[55]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[55]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[55]}]
# ddram:0.dq
set_property PACKAGE_PIN W15 [get_ports {ddr3_dq[56]}]
set_property SLEW FAST [get_ports {ddr3_dq[56]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[56]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[56]}]
# ddram:0.dq
set_property PACKAGE_PIN W16 [get_ports {ddr3_dq[57]}]
set_property SLEW FAST [get_ports {ddr3_dq[57]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[57]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[57]}]
# ddram:0.dq
set_property PACKAGE_PIN W14 [get_ports {ddr3_dq[58]}]
set_property SLEW FAST [get_ports {ddr3_dq[58]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[58]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[58]}]
# ddram:0.dq
set_property PACKAGE_PIN V16 [get_ports {ddr3_dq[59]}]
set_property SLEW FAST [get_ports {ddr3_dq[59]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[59]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[59]}]
# ddram:0.dq
set_property PACKAGE_PIN V19 [get_ports {ddr3_dq[60]}]
set_property SLEW FAST [get_ports {ddr3_dq[60]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[60]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[60]}]
# ddram:0.dq
set_property PACKAGE_PIN V17 [get_ports {ddr3_dq[61]}]
set_property SLEW FAST [get_ports {ddr3_dq[61]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[61]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[61]}]
# ddram:0.dq
set_property PACKAGE_PIN V18 [get_ports {ddr3_dq[62]}]
set_property SLEW FAST [get_ports {ddr3_dq[62]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[62]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[62]}]
# ddram:0.dq
set_property PACKAGE_PIN Y17 [get_ports {ddr3_dq[63]}]
set_property SLEW FAST [get_ports {ddr3_dq[63]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[63]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[63]}]
# ddram:0.dqs_p
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}]
# ddram:0.dqs_p
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}]
# ddram:0.dqs_p
set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[2]}]
# ddram:0.dqs_p
set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[3]}]
# ddram:0.dqs_p
set_property SLEW FAST [get_ports {ddr3_dqs_p[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[4]}]
# ddram:0.dqs_p
set_property SLEW FAST [get_ports {ddr3_dqs_p[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[5]}]
# ddram:0.dqs_p
set_property SLEW FAST [get_ports {ddr3_dqs_p[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[6]}]
# ddram:0.dqs_p
set_property SLEW FAST [get_ports {ddr3_dqs_p[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[7]}]
# ddram:0.dqs_n
set_property PACKAGE_PIN AB1 [get_ports {ddr3_dqs_p[0]}]
set_property PACKAGE_PIN AC1 [get_ports {ddr3_dqs_n[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}]
# ddram:0.dqs_n
set_property PACKAGE_PIN W6 [get_ports {ddr3_dqs_p[1]}]
set_property PACKAGE_PIN W5 [get_ports {ddr3_dqs_n[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}]
# ddram:0.dqs_n
set_property PACKAGE_PIN AF5 [get_ports {ddr3_dqs_p[2]}]
set_property PACKAGE_PIN AF4 [get_ports {ddr3_dqs_n[2]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[2]}]
# ddram:0.dqs_n
set_property PACKAGE_PIN AA5 [get_ports {ddr3_dqs_p[3]}]
set_property PACKAGE_PIN AB5 [get_ports {ddr3_dqs_n[3]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[3]}]
# ddram:0.dqs_n
set_property PACKAGE_PIN AE18 [get_ports {ddr3_dqs_p[4]}]
set_property PACKAGE_PIN AF18 [get_ports {ddr3_dqs_n[4]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[4]}]
# ddram:0.dqs_n
set_property PACKAGE_PIN Y15 [get_ports {ddr3_dqs_p[5]}]
set_property PACKAGE_PIN Y16 [get_ports {ddr3_dqs_n[5]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[5]}]
# ddram:0.dqs_n
set_property PACKAGE_PIN AD20 [get_ports {ddr3_dqs_p[6]}]
set_property PACKAGE_PIN AE20 [get_ports {ddr3_dqs_n[6]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[6]}]
# ddram:0.dqs_n
set_property PACKAGE_PIN W18 [get_ports {ddr3_dqs_p[7]}]
set_property PACKAGE_PIN W19 [get_ports {ddr3_dqs_n[7]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[7]}]
# ddram:0.clk_p
set_property SLEW FAST [get_ports ddr3_ck_p]
set_property VCCAUX_IO HIGH [get_ports ddr3_ck_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr3_ck_p]
# ddram:0.clk_n
set_property PACKAGE_PIN AB12 [get_ports ddr3_ck_p]
set_property PACKAGE_PIN AC12 [get_ports ddr3_ck_n]
set_property SLEW FAST [get_ports ddr3_ck_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr3_ck_n]
# ddram:0.cke
set_property PACKAGE_PIN AA13 [get_ports ddr3_cke]
set_property SLEW FAST [get_ports ddr3_cke]
set_property VCCAUX_IO HIGH [get_ports ddr3_cke]
set_property IOSTANDARD SSTL15 [get_ports ddr3_cke]
# ddram:0.odt
set_property PACKAGE_PIN AD13 [get_ports ddr3_odt]
set_property SLEW FAST [get_ports ddr3_odt]
set_property VCCAUX_IO HIGH [get_ports ddr3_odt]
set_property IOSTANDARD SSTL15 [get_ports ddr3_odt]
# ddram:0.reset_n
set_property PACKAGE_PIN AB7 [get_ports ddr3_reset_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_reset_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_reset_n]
set_property SLEW SLOW [get_ports ddr3_reset_n]
## user_led:0
#set_property PACKAGE_PIN U9 [get_ports {led[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[0]}]
#set_property SLEW SLOW [get_ports {led[0]}]
## user_led:1
#set_property PACKAGE_PIN V12 [get_ports {led[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[1]}]
#set_property SLEW SLOW [get_ports {led[1]}]
## user_led:2
#set_property PACKAGE_PIN V13 [get_ports {led[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[2]}]
#set_property SLEW SLOW [get_ports {led[2]}]
## user_led:3
#set_property PACKAGE_PIN W13 [get_ports {led[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[3]}]
#set_property SLEW SLOW [get_ports {led[3]}]
################################################################################
# Design constraints
################################################################################
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
################################################################################
# Clock constraints
################################################################################

2
formal/ddr3_multiconfig_ecc.sby
View File

@ -13,7 +13,7 @@ prf8lanes_100MHz_ECC_3_err prf_ECC3 opt_8lanes opt_100MHz
prf: mode prove
prf: depth 7
prf_ECC3: mode prove
prf_ECC3: depth 5
prf_ECC3: depth 7
[engines]
prf: smtbmc

4
rtl/axi/ddr3_top_axi.v
View File

@ -45,7 +45,7 @@ module ddr3_top_axi #(
ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
SKIP_INTERNAL_TEST = 0, // skip built-in self test (would require >2 seconds of internal test right after calibration)
parameter[1:0] BIST_MODE = 2, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)
@ -166,7 +166,7 @@ ddr3_top #(
.WB2_ADDR_BITS(WB2_ADDR_BITS), //width of 2nd wishbone address bus
.WB2_DATA_BITS(WB2_DATA_BITS), //width of 2nd wishbone data bus
.WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
.SKIP_INTERNAL_TEST(SKIP_INTERNAL_TEST), // skip built-in self test (would require >2 seconds of internal test right after calibration)
.BIST_MODE(BIST_MODE), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
.ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
.DIC(DIC), // Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
.RTT_NOM(RTT_NOM), //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)

611
rtl/ddr3_controller.v
View File

@ -38,7 +38,7 @@
// Comments are continuously added on this RTL for better readability
//`define FORMAL_COVER //skip reset sequence during formal verification to fit in cover depth
`default_nettype none
// `default_nettype none
`timescale 1ps / 1ps
//
// speed bin
@ -69,7 +69,7 @@ module ddr3_controller #(
ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone is needed
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
SKIP_INTERNAL_TEST = 1, // skip built-in self test (would require >2 seconds of internal test right after calibration)
parameter[1:0] BIST_MODE = 1, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) (only change when you know what you are doing)
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
@ -135,7 +135,7 @@ module ddr3_controller #(
output reg o_phy_write_leveling_calib,
output wire o_phy_reset,
// Done Calibration pin
output wire o_calib_complete,
(* mark_debug = "true" *) output wire o_calib_complete,
// Debug port
output wire [31:0] o_debug1,
// output wire [31:0] o_debug2,
@ -269,6 +269,7 @@ module ddr3_controller #(
localparam[3:0] ACTIVATE_TO_PRECHARGE_DELAY = find_delay(ps_to_nCK(tRAS), ACTIVATE_SLOT, PRECHARGE_SLOT);
localparam[3:0] ACTIVATE_TO_WRITE_DELAY = find_delay(ps_to_nCK(tRCD), ACTIVATE_SLOT, WRITE_SLOT); //3
localparam[3:0] ACTIVATE_TO_READ_DELAY = find_delay(ps_to_nCK(tRCD), ACTIVATE_SLOT, READ_SLOT); //2
localparam[3:0] ACTIVATE_TO_ACTIVATE_DELAY = find_delay(ps_to_nCK(7500), ACTIVATE_SLOT, ACTIVATE_SLOT); //TRRD
localparam[3:0] READ_TO_WRITE_DELAY = find_delay((CL_nCK + tCCD + 2 - CWL_nCK), READ_SLOT, WRITE_SLOT); //2
localparam[3:0] READ_TO_READ_DELAY = 0;
localparam[3:0] READ_TO_PRECHARGE_DELAY = find_delay(ps_to_nCK(tRTP), READ_SLOT, PRECHARGE_SLOT); //1
@ -278,7 +279,7 @@ module ddr3_controller #(
/* verilator lint_on WIDTHEXPAND */
localparam PRE_REFRESH_DELAY = WRITE_TO_PRECHARGE_DELAY + 1;
`ifdef FORMAL
(*keep*) wire[3:0] f_PRECHARGE_TO_ACTIVATE_DELAY, f_ACTIVATE_TO_PRECHARGE_DELAY, f_ACTIVATE_TO_WRITE_DELAY, f_ACTIVATE_TO_READ_DELAY,
(*keep*) wire[3:0] f_PRECHARGE_TO_ACTIVATE_DELAY, f_ACTIVATE_TO_PRECHARGE_DELAY, f_ACTIVATE_TO_WRITE_DELAY, f_ACTIVATE_TO_READ_DELAY, f_ACTIVATE_TO_ACTIVATE_DELAY,
f_READ_TO_WRITE_DELAY, f_READ_TO_READ_DELAY, f_READ_TO_PRECHARGE_DELAY, f_WRITE_TO_WRITE_DELAY,
f_WRITE_TO_READ_DELAY, f_WRITE_TO_PRECHARGE_DELAY;
assign f_PRECHARGE_TO_ACTIVATE_DELAY = PRECHARGE_TO_ACTIVATE_DELAY;
@ -291,6 +292,7 @@ module ddr3_controller #(
assign f_WRITE_TO_WRITE_DELAY = WRITE_TO_WRITE_DELAY;
assign f_WRITE_TO_READ_DELAY = WRITE_TO_READ_DELAY;
assign f_WRITE_TO_PRECHARGE_DELAY = WRITE_TO_PRECHARGE_DELAY;
assign f_ACTIVATE_TO_ACTIVATE_DELAY = ACTIVATE_TO_ACTIVATE_DELAY;
`endif
//MARGIN_BEFORE_ANTICIPATE is the number of columns before the column
@ -321,6 +323,7 @@ module ddr3_controller #(
localparam DELAY_BEFORE_WRITE_LEVEL_FEEDBACK = STAGE2_DATA_DEPTH + ps_to_cycles(tWLO+tWLOE) + 10;
//plus 10 controller clocks for possible bus latency and the delay for receiving feedback DQ from IOBUF -> IDELAY -> ISERDES
localparam ECC_INFORMATION_BITS = (ECC_ENABLE == 2)? max_information_bits(wb_data_bits) : max_information_bits(wb_data_bits/8);
localparam SIM_ADDRESS_INCR_LOG2 = wb_addr_bits-2-7; // 2^(wb_addr_bits-2)/128
/*********************************************************************************************************************************************/
@ -551,13 +554,16 @@ module ddr3_controller #(
(* mark_debug = "true" *) reg calib_we = 0;
reg[wb_addr_bits-1:0] calib_addr = 0;
reg[wb_data_bits-1:0] calib_data = 0;
wire[wb_data_bits-1:0] calib_data_randomized;
reg write_calib_odt = 0;
reg write_calib_dqs = 0;
reg write_calib_dq = 0;
(* mark_debug = "true" *) reg prev_write_level_feedback = 1;
reg[wb_data_bits-1:0] read_data_store = 0;
reg[127:0] write_pattern = 0;
reg[$clog2(64):0] data_start_index[LANES-1:0];
reg[$clog2(64):0] data_start_index[LANES-1:0];
reg[LANES-1:0] lane_write_dq_late = 0;
reg[LANES-1:0] lane_read_dq_early = 0;
(* mark_debug = "true" *) reg[4:0] odelay_data_cntvaluein[LANES-1:0];
reg[4:0] odelay_dqs_cntvaluein[LANES-1:0];
reg[4:0] idelay_data_cntvaluein[LANES-1:0];
@ -593,9 +599,9 @@ module ddr3_controller #(
reg reset_after_rank_1 = 0; // reset after calibration rank 1 to switch to rank 2
reg current_rank = 0;
// test calibration
reg[wb_addr_bits-1:0] read_test_address_counter = 0, check_test_address_counter = 0; ////////////////////////////////////////////////////////
reg[31:0] write_test_address_counter = 0;
reg[31:0] correct_read_data = 0, wrong_read_data = 0;
(* mark_debug = "true" *) reg[wb_addr_bits:0] read_test_address_counter = 0, check_test_address_counter = 0; ////////////////////////////////////////////////////////
(* mark_debug = "true" *) reg[wb_addr_bits:0] write_test_address_counter = 0;
(* mark_debug = "true" *) reg[31:0] correct_read_data = 0, wrong_read_data = 0;
/* verilator lint_off UNDRIVEN */
(* mark_debug = "true" *) wire sb_err_o;
wire db_err_o;
@ -645,6 +651,7 @@ module ddr3_controller #(
idelay_data_cntvaluein[index] = DATA_INITIAL_IDELAY_TAP[4:0];
idelay_dqs_cntvaluein[index] = DQS_INITIAL_IDELAY_TAP[4:0];
dq_target_index[index] = 0;
data_start_index[index] = 0;
end
end
/*********************************************************************************************************************************************/
@ -1183,70 +1190,101 @@ module ddr3_controller #(
end
end
for(index = 0; index < LANES; index = index + 1) begin
/* verilator lint_off WIDTH */
// stage2_data_unaligned is the DQ_BITS*LANES*8 raw data from stage 1 so not yet aligned
// unaligned_data is 64 bits
{unaligned_data[index], {
stage2_data[0][((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*6 + 8*index) +: 8],
stage2_data[0][((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*4 + 8*index) +: 8],
stage2_data[0][((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*2 + 8*index) +: 8],
stage2_data[0][((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*0 + 8*index) +: 8] }}
<= ( { stage2_data_unaligned[((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*6 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*4 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*2 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*0 + 8*index) +: 8] }
<< data_start_index[index]) | unaligned_data[index];
/*
// Example with LANE 0:
// Burst_0 to burst_7 of unaligned LANE 0 will be extracted which will be shifted by data_start_index.
// Each 8 bits of shift means a burst will be moved to next ddr3_clk cycle, this is needed if for example
// the DQ trace is longer than the command trace where the DQ bits must be delayed by 1 ddr3_clk cycle
// to align the DQ data to the write command.
//
// Since 1 controller clk cycle will have 4 ddr3_clk cycle, and each ddr3_clk cycle is DDR:
// CONTROLLER CLK CYCLE 0: [burst0,burst1] [burst2,burst3] [burst4,burst5] [burst6,burst7]
// CONTROLLER CLK CYCLE 1: [burst0,burst1] [burst2,burst3] [burst4,burst5] [burst6,burst7]
// CONTROLLER CLK CYCLE 2: [burst0,burst1] [burst2,burst3] [burst4,burst5] [burst6,burst7]
//
// shifting by 1 burst means burst 7 will be sent on next controller clk cycle and EVERY BURST WILL SHIFT:
// CONTROLLER CLK CYCLE 0: [xxxxxx,xxxxxx] [burst0,burst1] [burst2,burst3] [burst4,burst5]
// CONTROLLER CLK CYCLE 1: [burst6,burst7] [burst0,burst1] [burst2,burst3] [burst4,burst5]
// CONTROLLER CLK CYCLE 2: [burst6,burst7] [burst0,burst1] [burst2,burst3] [burst4,burst5]
//
// the [burst6,burst7] which has to be stored and delayed until next clk cycle will be handled by unaligned_data
{unaligned_data[0], {
stage2_data[0][((64)*7 + 8*0) +: 8], stage2_data[0][((64)*6 + 8*0) +: 8],
stage2_data[0][((64)*5 + 8*0) +: 8], stage2_data[0][((64)*4 + 8*0) +: 8],
stage2_data[0][((64)*3 + 8*0) +: 8], stage2_data[0][((64)*2 + 8*0) +: 8],
stage2_data[0][((64)*1 + 8*0) +: 8], stage2_data[0][((64)*0 + 8*0) +: 8] }}
<= ( { stage2_data_unaligned[((64)*7 + 8*0) +: 8], stage2_data_unaligned[((64)*6 + 8*0) +: 8],
stage2_data_unaligned[((64)*5 + 8*0) +: 8], stage2_data_unaligned[((64)*4 + 8*0) +: 8],
stage2_data_unaligned[((64)*3 + 8*0) +: 8], stage2_data_unaligned[((64)*2 + 8*0) +: 8],
stage2_data_unaligned[((64)*1 + 8*0) +: 8], stage2_data_unaligned[((64)*0 + 8*0) +: 8] }
<< data_start_index[0]) | unaligned_data[0];
*/
// The same alignment logic is done with data mask
{unaligned_dm[index], {
stage2_dm[0][LANES*7 + index], stage2_dm[0][LANES*6 + index],
stage2_dm[0][LANES*5 + index], stage2_dm[0][LANES*4 + index],
stage2_dm[0][LANES*3 + index], stage2_dm[0][LANES*2 + index],
stage2_dm[0][LANES*1 + index], stage2_dm[0][LANES*0 + index] }}
<= ( { stage2_dm_unaligned[LANES*7 + index], stage2_dm_unaligned[LANES*6 + index],
stage2_dm_unaligned[LANES*5 + index], stage2_dm_unaligned[LANES*4 + index],
stage2_dm_unaligned[LANES*3 + index], stage2_dm_unaligned[LANES*2 + index],
stage2_dm_unaligned[LANES*1 + index], stage2_dm_unaligned[LANES*0 + index] }
<< (data_start_index[index]>>3)) | unaligned_dm[index];
/* verilator lint_on WIDTH */
end
// stage2 can have multiple pipelined stages inside it which acts as delay before issuing the write data (after issuing write command)
for(index = 0; index < STAGE2_DATA_DEPTH-1; index = index+1) begin
stage2_data[index+1] <= stage2_data[index];
stage2_data[index+1] <= stage2_data[index]; // 0->1, 1->2
stage2_dm[index+1] <= stage2_dm[index];
end
for(index = 0; index < LANES; index = index + 1) begin
/* verilator lint_off WIDTH */
// if DQ is too late (298cd0ad51c1XXXX is written) then we want to DQ to be early
// Thus, we will forward the stage2_data_unaligned directly to stage2_data[1] (instead of the usual stage2_data[0])
// checks if the DQ for this lane is late (index being zero while write_dq_late high means we will try 2nd assumption), if yes then we forward stage2_data_unaligned directly to stage2_data[1]
if(lane_write_dq_late[index] && (data_start_index[index] != 0)) begin
{unaligned_data[index], {
stage2_data[1][((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data[1][((DQ_BITS*LANES)*6 + 8*index) +: 8],
stage2_data[1][((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data[1][((DQ_BITS*LANES)*4 + 8*index) +: 8],
stage2_data[1][((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data[1][((DQ_BITS*LANES)*2 + 8*index) +: 8],
stage2_data[1][((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data[1][((DQ_BITS*LANES)*0 + 8*index) +: 8] }}
<= ( { stage2_data_unaligned[((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*6 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*4 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*2 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*0 + 8*index) +: 8] }
<< data_start_index[index]) | unaligned_data[index];
{unaligned_dm[index], {
stage2_dm[1][LANES*7 + index], stage2_dm[1][LANES*6 + index],
stage2_dm[1][LANES*5 + index], stage2_dm[1][LANES*4 + index],
stage2_dm[1][LANES*3 + index], stage2_dm[1][LANES*2 + index],
stage2_dm[1][LANES*1 + index], stage2_dm[1][LANES*0 + index] }}
<= ( { stage2_dm_unaligned[LANES*7 + index], stage2_dm_unaligned[LANES*6 + index],
stage2_dm_unaligned[LANES*5 + index], stage2_dm_unaligned[LANES*4 + index],
stage2_dm_unaligned[LANES*3 + index], stage2_dm_unaligned[LANES*2 + index],
stage2_dm_unaligned[LANES*1 + index], stage2_dm_unaligned[LANES*0 + index] }
<< (data_start_index[index]>>3)) | unaligned_dm[index];
/* verilator lint_on WIDTH */
end // end of if statement (dq for this lane is late)
else begin // DQ is not late so we will forward stage2_data_unaligned to stage2_data[0]
/* verilator lint_off WIDTH */
// stage2_data_unaligned is the DQ_BITS*LANES*8 raw data from stage 1 so not yet aligned
// unaligned_data is 64 bits
{unaligned_data[index], {
stage2_data[0][((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*6 + 8*index) +: 8],
stage2_data[0][((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*4 + 8*index) +: 8],
stage2_data[0][((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*2 + 8*index) +: 8],
stage2_data[0][((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*0 + 8*index) +: 8] }}
<= ( { stage2_data_unaligned[((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*6 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*4 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*2 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*0 + 8*index) +: 8] }
<< data_start_index[index]) | unaligned_data[index];
/*
// Example with LANE 0:
// Burst_0 to burst_7 of unaligned LANE 0 will be extracted which will be shifted by data_start_index.
// Each 8 bits of shift means a burst will be moved to next ddr3_clk cycle, this is needed if for example
// the DQ trace is longer than the command trace where the DQ bits must be delayed by 1 ddr3_clk cycle
// to align the DQ data to the write command.
//
// Since 1 controller clk cycle will have 4 ddr3_clk cycle, and each ddr3_clk cycle is DDR:
// CONTROLLER CLK CYCLE 0: [burst0,burst1] [burst2,burst3] [burst4,burst5] [burst6,burst7]
// CONTROLLER CLK CYCLE 1: [burst0,burst1] [burst2,burst3] [burst4,burst5] [burst6,burst7]
// CONTROLLER CLK CYCLE 2: [burst0,burst1] [burst2,burst3] [burst4,burst5] [burst6,burst7]
//
// shifting by 1 burst means burst 7 will be sent on next controller clk cycle and EVERY BURST WILL SHIFT:
// CONTROLLER CLK CYCLE 0: [xxxxxx,xxxxxx] [burst0,burst1] [burst2,burst3] [burst4,burst5]
// CONTROLLER CLK CYCLE 1: [burst6,burst7] [burst0,burst1] [burst2,burst3] [burst4,burst5]
// CONTROLLER CLK CYCLE 2: [burst6,burst7] [burst0,burst1] [burst2,burst3] [burst4,burst5]
//
// the [burst6,burst7] which has to be stored and delayed until next clk cycle will be handled by unaligned_data
{unaligned_data[0], {
stage2_data[0][((64)*7 + 8*0) +: 8], stage2_data[0][((64)*6 + 8*0) +: 8],
stage2_data[0][((64)*5 + 8*0) +: 8], stage2_data[0][((64)*4 + 8*0) +: 8],
stage2_data[0][((64)*3 + 8*0) +: 8], stage2_data[0][((64)*2 + 8*0) +: 8],
stage2_data[0][((64)*1 + 8*0) +: 8], stage2_data[0][((64)*0 + 8*0) +: 8] }}
<= ( { stage2_data_unaligned[((64)*7 + 8*0) +: 8], stage2_data_unaligned[((64)*6 + 8*0) +: 8],
stage2_data_unaligned[((64)*5 + 8*0) +: 8], stage2_data_unaligned[((64)*4 + 8*0) +: 8],
stage2_data_unaligned[((64)*3 + 8*0) +: 8], stage2_data_unaligned[((64)*2 + 8*0) +: 8],
stage2_data_unaligned[((64)*1 + 8*0) +: 8], stage2_data_unaligned[((64)*0 + 8*0) +: 8] }
<< data_start_index[0]) | unaligned_data[0];
*/
// The same alignment logic is done with data mask
{unaligned_dm[index], {
stage2_dm[0][LANES*7 + index], stage2_dm[0][LANES*6 + index],
stage2_dm[0][LANES*5 + index], stage2_dm[0][LANES*4 + index],
stage2_dm[0][LANES*3 + index], stage2_dm[0][LANES*2 + index],
stage2_dm[0][LANES*1 + index], stage2_dm[0][LANES*0 + index] }}
<= ( { stage2_dm_unaligned[LANES*7 + index], stage2_dm_unaligned[LANES*6 + index],
stage2_dm_unaligned[LANES*5 + index], stage2_dm_unaligned[LANES*4 + index],
stage2_dm_unaligned[LANES*3 + index], stage2_dm_unaligned[LANES*2 + index],
stage2_dm_unaligned[LANES*1 + index], stage2_dm_unaligned[LANES*0 + index] }
<< (data_start_index[index]>>3)) | unaligned_dm[index];
/* verilator lint_on WIDTH */
end // end for else statement (dq is not late for this lane)
end // end of for loop to forward stage2_unaligned to stage2 by lane
//abort any outgoing ack when cyc is low
if(!i_wb_cyc && final_calibration_done) begin
stage2_pending <= 0;
@ -1458,14 +1496,7 @@ module ddr3_controller #(
cmd_d[PRECHARGE_SLOT][10] = instruction[A10_CONTROL];
cmd_d[READ_SLOT][cmd_len-1-DUAL_RANK_DIMM:0] = {(!issue_read_command), CMD_RD[2:0] | {3{(!issue_read_command)}}, cmd_odt, cmd_ck_en, cmd_reset_n, {(ROW_BITS+BA_BITS){1'b0}}}; // issued during MPR reads (address does not matter)
cmd_d[ACTIVATE_SLOT][cmd_len-1-DUAL_RANK_DIMM:0] = {1'b0, 3'b111 , cmd_odt, cmd_ck_en, cmd_reset_n, {(ROW_BITS+BA_BITS){1'b0}}}; // always NOP by default
if(PRECHARGE_SLOT != 0) begin // if precharge slot is not the 0th slot, then all slots before precharge will have the previous value of cmd_ck_en
for(index = 0; index < PRECHARGE_SLOT; index=index+1) begin // slots before
if(DUAL_RANK_DIMM[0]) begin
cmd_d[index][CMD_CKE_2] = prev_cmd_ck_en[DUAL_RANK_DIMM];
end
cmd_d[index][CMD_CKE] = prev_cmd_ck_en[0];
end
end
// extra slot is created when READ and WRITE slots are the same
// this remaining slot should be NOP by default
if(WRITE_SLOT == READ_SLOT) begin
@ -1475,6 +1506,17 @@ module ddr3_controller #(
else begin
cmd_d[WRITE_SLOT][cmd_len-1-DUAL_RANK_DIMM:0] = {1'b0, 3'b111, cmd_odt, cmd_ck_en, cmd_reset_n, {(ROW_BITS+BA_BITS){1'b0}}}; // always NOP by default
end
// if precharge slot is not the 0th slot, then all slots before precharge will have the previous value of cmd_ck_en
if(PRECHARGE_SLOT != 0) begin
for(index = 0; index < PRECHARGE_SLOT; index=index+1) begin // slots before
if(DUAL_RANK_DIMM[0]) begin
cmd_d[index][CMD_CKE_2] = prev_cmd_ck_en[DUAL_RANK_DIMM];
end
cmd_d[index][CMD_CKE] = prev_cmd_ck_en[0];
end
end
/////////////////////////////////////////////////////////////////////////////////////////
// if dual rank is enabled, last 2 bits are {cs_2, cs_1}
if(DUAL_RANK_DIMM[0]) begin
@ -1652,7 +1694,15 @@ module ddr3_controller #(
//bank is idle so activate it
else if(!bank_status_q[stage2_bank] && delay_before_activate_counter_q[stage2_bank] == 0) begin
activate_slot_busy = 1'b1;
// must meet TRRD (activate to activate delay)
for(index=0; index < (1<<(BA_BITS+DUAL_RANK_DIMM)); index=index+1) begin //the activate to activate delay applies to all banks
if(delay_before_activate_counter_q[index] <= ACTIVATE_TO_ACTIVATE_DELAY) begin // if delay is > ACTIVATE_TO_ACTIVATE_DELAY, then updating it to the lower delay will cause the previous delay to be violated
delay_before_activate_counter_d[index] = ACTIVATE_TO_ACTIVATE_DELAY;
end
end
delay_before_precharge_counter_d[stage2_bank] = ACTIVATE_TO_PRECHARGE_DELAY;
//set-up delay before read and write
if(delay_before_read_counter_q[stage2_bank] <= ACTIVATE_TO_READ_DELAY) begin // if current delay is > ACTIVATE_TO_READ_DELAY, then updating it to the lower delay will cause the previous delay to be violated
delay_before_read_counter_d[stage2_bank] = ACTIVATE_TO_READ_DELAY;
@ -1688,53 +1738,64 @@ module ddr3_controller #(
end
end //end of stage 2 pending
//pending request on stage 1
if(stage1_pending && !((stage1_next_bank == stage2_bank) && stage2_pending)) begin
//stage 1 will mainly be for anticipation (if next requests need to jump to new bank then
//anticipate the precharging and activate of that next bank, BUT it can also handle
//precharge and activate of CURRENT wishbone request.
//Anticipate will depend if the request is on the end of the row
// and must start the anticipation. For example if we have 10 rows in a bank:
//[R][R][R][R][R][R][R][A][A][A] -> [next bank]
//
//R = Request, A = Anticipate
//Unless we are near the third to the last column, stage 1 will
//issue Activate and Precharge on the CURRENT bank. Else, stage
//1 will issue Activate and Precharge for the NEXT bank
// Thus stage 1 anticipate makes sure smooth burst operation that jumps banks
if(bank_status_q[stage1_next_bank] && bank_active_row_q[stage1_next_bank] != stage1_next_row && delay_before_precharge_counter_q[stage1_next_bank] ==0 && !precharge_slot_busy) begin
//set-up delay before read and write
delay_before_activate_counter_d[stage1_next_bank] = PRECHARGE_TO_ACTIVATE_DELAY;
if(DUAL_RANK_DIMM[0]) begin
cmd_d[PRECHARGE_SLOT] = {!stage1_next_bank[(DUAL_RANK_DIMM[0]? BA_BITS : 0)], stage1_next_bank[(DUAL_RANK_DIMM[0]? BA_BITS : 0)], CMD_PRE[2:0], cmd_odt, cmd_ck_en, cmd_reset_n, stage1_next_bank[BA_BITS-1:0], { {{ROW_BITS-32'd11}{1'b0}} , 1'b0 , stage1_next_row[(DUAL_RANK_DIMM[0]? 9 : 8):0] } };
end
else begin
cmd_d[PRECHARGE_SLOT] = {1'b0, CMD_PRE[2:0], cmd_odt, cmd_ck_en, cmd_reset_n, stage1_next_bank, { {{ROW_BITS-32'd11}{1'b0}} , 1'b0 , stage1_next_row[9:0] } };
end
bank_status_d[stage1_next_bank] = 1'b0;
end //end of anticipate precharge
//anticipated bank is idle so do activate
else if(!bank_status_q[stage1_next_bank] && delay_before_activate_counter_q[stage1_next_bank] == 0 && !activate_slot_busy) begin
delay_before_precharge_counter_d[stage1_next_bank] = ACTIVATE_TO_PRECHARGE_DELAY;
//set-up delay before read and write
if(delay_before_read_counter_d[stage1_next_bank] <= ACTIVATE_TO_READ_DELAY) begin // if current delay is > ACTIVATE_TO_READ_DELAY, then updating it to the lower delay will cause the previous delay to be violated
delay_before_read_counter_d[stage1_next_bank] = ACTIVATE_TO_READ_DELAY;
end
if(delay_before_write_counter_d[stage1_next_bank] <= ACTIVATE_TO_WRITE_DELAY) begin // if current delay is > ACTIVATE_TO_WRITE_DELAY, then updating it to the lower delay will cause the previous delay to be violated
delay_before_write_counter_d[stage1_next_bank] = ACTIVATE_TO_WRITE_DELAY;
end
if(DUAL_RANK_DIMM[0]) begin
cmd_d[ACTIVATE_SLOT] = {!stage1_next_bank[(DUAL_RANK_DIMM[0]? BA_BITS : 0)], stage1_next_bank[(DUAL_RANK_DIMM[0]? BA_BITS : 0)], CMD_ACT[2:0] , cmd_odt, cmd_ck_en, cmd_reset_n, stage1_next_bank[BA_BITS-1:0] , stage1_next_row[(DUAL_RANK_DIMM[0]? ROW_BITS-1 : ROW_BITS-2):0]};
end
else begin
cmd_d[ACTIVATE_SLOT] = {1'b0, CMD_ACT[2:0] , cmd_odt, cmd_ck_en, cmd_reset_n, stage1_next_bank , stage1_next_row};
end
bank_status_d[stage1_next_bank] = 1'b1;
bank_active_row_d[stage1_next_bank] = stage1_next_row;
end //end of anticipate activate
end //end of stage1 anticipate
// pending request on stage 1
// if DDR3_CLK_PERIOD == 1250, then remove this anticipate stage 1 to pass timing
if(DDR3_CLK_PERIOD != 1_250) begin
if(stage1_pending && !((stage1_next_bank == stage2_bank) && stage2_pending)) begin
//stage 1 will mainly be for anticipation (if next requests need to jump to new bank then
//anticipate the precharging and activate of that next bank, BUT it can also handle
//precharge and activate of CURRENT wishbone request.
//Anticipate will depend if the request is on the end of the row
// and must start the anticipation. For example if we have 10 rows in a bank:
//[R][R][R][R][R][R][R][A][A][A] -> [next bank]
//
//R = Request, A = Anticipate
//Unless we are near the third to the last column, stage 1 will
//issue Activate and Precharge on the CURRENT bank. Else, stage
//1 will issue Activate and Precharge for the NEXT bank
// Thus stage 1 anticipate makes sure smooth burst operation that jumps banks
if(bank_status_q[stage1_next_bank] && bank_active_row_q[stage1_next_bank] != stage1_next_row && delay_before_precharge_counter_q[stage1_next_bank] ==0 && !precharge_slot_busy) begin
//set-up delay before read and write
delay_before_activate_counter_d[stage1_next_bank] = PRECHARGE_TO_ACTIVATE_DELAY;
if(DUAL_RANK_DIMM[0]) begin
cmd_d[PRECHARGE_SLOT] = {!stage1_next_bank[(DUAL_RANK_DIMM[0]? BA_BITS : 0)], stage1_next_bank[(DUAL_RANK_DIMM[0]? BA_BITS : 0)], CMD_PRE[2:0], cmd_odt, cmd_ck_en, cmd_reset_n, stage1_next_bank[BA_BITS-1:0], { {{ROW_BITS-32'd11}{1'b0}} , 1'b0 , stage1_next_row[(DUAL_RANK_DIMM[0]? 9 : 8):0] } };
end
else begin
cmd_d[PRECHARGE_SLOT] = {1'b0, CMD_PRE[2:0], cmd_odt, cmd_ck_en, cmd_reset_n, stage1_next_bank, { {{ROW_BITS-32'd11}{1'b0}} , 1'b0 , stage1_next_row[9:0] } };
end
bank_status_d[stage1_next_bank] = 1'b0;
end //end of anticipate precharge
//anticipated bank is idle so do activate
else if(!bank_status_q[stage1_next_bank] && delay_before_activate_counter_q[stage1_next_bank] == 0 && !activate_slot_busy) begin
// must meet TRRD (activate to activate delay)
for(index=0; index < (1<<(BA_BITS+DUAL_RANK_DIMM)); index=index+1) begin //the activate to activate delay applies to all banks
if(delay_before_activate_counter_d[index] <= ACTIVATE_TO_ACTIVATE_DELAY) begin // if delay is > ACTIVATE_TO_ACTIVATE_DELAY, then updating it to the lower delay will cause the previous delay to be violated
delay_before_activate_counter_d[index] = ACTIVATE_TO_ACTIVATE_DELAY;
end
end
delay_before_precharge_counter_d[stage1_next_bank] = ACTIVATE_TO_PRECHARGE_DELAY;
//set-up delay before read and write
if(delay_before_read_counter_d[stage1_next_bank] <= ACTIVATE_TO_READ_DELAY) begin // if current delay is > ACTIVATE_TO_READ_DELAY, then updating it to the lower delay will cause the previous delay to be violated
delay_before_read_counter_d[stage1_next_bank] = ACTIVATE_TO_READ_DELAY;
end
if(delay_before_write_counter_d[stage1_next_bank] <= ACTIVATE_TO_WRITE_DELAY) begin // if current delay is > ACTIVATE_TO_WRITE_DELAY, then updating it to the lower delay will cause the previous delay to be violated
delay_before_write_counter_d[stage1_next_bank] = ACTIVATE_TO_WRITE_DELAY;
end
if(DUAL_RANK_DIMM[0]) begin
cmd_d[ACTIVATE_SLOT] = {!stage1_next_bank[(DUAL_RANK_DIMM[0]? BA_BITS : 0)], stage1_next_bank[(DUAL_RANK_DIMM[0]? BA_BITS : 0)], CMD_ACT[2:0] , cmd_odt, cmd_ck_en, cmd_reset_n, stage1_next_bank[BA_BITS-1:0] , stage1_next_row[(DUAL_RANK_DIMM[0]? ROW_BITS-1 : ROW_BITS-2):0]};
end
else begin
cmd_d[ACTIVATE_SLOT] = {1'b0, CMD_ACT[2:0] , cmd_odt, cmd_ck_en, cmd_reset_n, stage1_next_bank , stage1_next_row};
end
bank_status_d[stage1_next_bank] = 1'b1;
bank_active_row_d[stage1_next_bank] = stage1_next_row;
end //end of anticipate activate
end //end of stage1 anticipate
end
// control stage 1 stall
if(stage1_pending) begin //raise stall only if stage2 will still be busy next clock
@ -1931,6 +1992,9 @@ module ddr3_controller #(
// while the lane with added_read_pipe_max of delay (delay of 1) will be retrieved SECOND
if(delay_read_pipe[0][added_read_pipe_max != added_read_pipe[index]]) begin
/* verilator lint_on WIDTH */
// o_wb_data[63:0] = BURST0: {LANE7,LANE6,LANE5,LANE4,LANE3,LANE2,LANE1,LANE0}
// o_wb_data[127:64] = BURST1: {LANE7,LANE6,LANE5,LANE4,LANE3,LANE2,LANE1,LANE0}
// o_wb_data[191:128] = BURST2: {LANE7,LANE6,LANE5,LANE4,LANE3,LANE2,LANE1,LANE0}
o_wb_data_q[0][((DQ_BITS*LANES)*0 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*0 + 8*index) +: 8]; //update lane for burst 0
o_wb_data_q[0][((DQ_BITS*LANES)*1 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*1 + 8*index) +: 8]; //update lane for burst 1
o_wb_data_q[0][((DQ_BITS*LANES)*2 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*2 + 8*index) +: 8]; //update lane for burst 2
@ -2139,6 +2203,8 @@ module ddr3_controller #(
initial_calibration_done <= 1'b0;
final_calibration_done <= 1'b0;
reset_after_rank_1 <= 1'b0;
lane_write_dq_late <= 0;
lane_read_dq_early <= 0;
for(index = 0; index < LANES; index = index + 1) begin
added_read_pipe[index] <= 0;
data_start_index[index] <= 0;
@ -2202,7 +2268,7 @@ module ddr3_controller #(
if(idelay_data_cntvaluein[lane] == 0 && idelay_data_cntvaluein_prev == 31) begin //the DQ got past cntvalue of 31 (and goes back to zero) thus the target index should also go back (to previous odd)
dq_target_index[lane] <= dqs_target_index_orig - 2;
end
// FSM
case(state_calibrate)
IDLE: if(i_phy_idelayctrl_rdy && instruction_address == 13) begin //we are now inside instruction 15 with maximum delay
@ -2382,7 +2448,7 @@ module ddr3_controller #(
if(sample_clk_repeat == REPEAT_CLK_SAMPLING) begin
sample_clk_repeat <= 0;
prev_write_level_feedback <= stored_write_level_feedback;
if(({prev_write_level_feedback, stored_write_level_feedback} == 2'b01) || write_level_fail[lane]) begin
if(({prev_write_level_feedback, stored_write_level_feedback} == 2'b01) /*|| write_level_fail[lane]*/) begin
/* verilator lint_on WIDTH */
/* verilator lint_off WIDTH */
if(lane == LANES - 1) begin
@ -2405,10 +2471,10 @@ module ddr3_controller #(
o_phy_odelay_data_ld[lane] <= 1;
o_phy_odelay_dqs_ld[lane] <= 1;
write_level_fail[lane] <= odelay_cntvalue_halfway;
if(odelay_cntvalue_halfway) begin // if halfway cntvalue is reached which is illegal (or impossible to happen), then we load the original cntvalues
odelay_data_cntvaluein[lane] <= DATA_INITIAL_ODELAY_TAP[4:0];
odelay_dqs_cntvaluein[lane] <= DQS_INITIAL_ODELAY_TAP[4:0];
end
// if(odelay_cntvalue_halfway) begin // if halfway cntvalue is reached which is illegal (or impossible to happen), then we load the original cntvalues
// odelay_data_cntvaluein[lane] <= DATA_INITIAL_ODELAY_TAP[4:0];
// odelay_dqs_cntvaluein[lane] <= DQS_INITIAL_ODELAY_TAP[4:0];
// end
state_calibrate <= START_WRITE_LEVEL;
end
end
@ -2468,7 +2534,7 @@ module ddr3_controller #(
read_data_store <= o_wb_data_uncalibrated; // read data on address 0
calib_stb <= 0;
state_calibrate <= ANALYZE_DATA;
data_start_index[lane] <= 0;
// data_start_index[lane] <= 0; // dont set to zero since this may have been already set by previous CHECK_STARTING_DATA
// Possible Patterns (strong autocorrel stat)
//0x80dbcfd275f12c3d
//0x9177298cd0ad51c1
@ -2479,19 +2545,20 @@ module ddr3_controller #(
else if(!o_wb_stall_calib) begin
calib_stb <= 0;
end
// extract burst_0-to-burst_7 data for a specified lane then determine which byte in write_pattern does it starts
// extract burst_0-to-burst_7 data for a specified lane then determine which byte in write_pattern does it starts (ASSUMPTION: the DQ is too early [3d_9177298cd0ad51]c1 is written)
// NOTE TO SELF: all "8" here assume DQ_BITS are 8? parameterize this properly
// data_start_index for a specified lane determine how many bits are off the data from the write command
// so for every 1 ddr3 clk cycle delay of DQ from write command, each lane will be 1 burst off:
// e.g. LANE={burst7, burst6, burst5, burst4, burst3, burst2, burst1, burst0} then with 1 ddr3 cycle delay between DQ and command
// burst0 will not be written but only starting on burst1
ANALYZE_DATA: if(write_pattern[data_start_index[lane] +: 64] == {read_data_store[((DQ_BITS*LANES)*7 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*6 + 8*lane) +: 8],
// if lane_write_dq_late is already set to 1 for this lane, then current lane should already be fixed without changing the data_start_index
ANALYZE_DATA: if(write_pattern[ (lane_write_dq_late[lane]? 0 : data_start_index[lane]) +: 64] == {read_data_store[((DQ_BITS*LANES)*7 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*6 + 8*lane) +: 8],
read_data_store[((DQ_BITS*LANES)*5 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*4 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*3 + 8*lane) +: 8],
read_data_store[((DQ_BITS*LANES)*2 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*1 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*0 + 8*lane) +: 8] }) begin
/* verilator lint_off WIDTH */
if(lane == LANES - 1) begin
/* verilator lint_on WIDTH */
state_calibrate <= SKIP_INTERNAL_TEST? FINISH_READ : BURST_WRITE; // go straight to FINISH_READ if SKIP_INTERNAL_TEST high
state_calibrate <= BIST_MODE == 0? FINISH_READ : BURST_WRITE; // go straight to FINISH_READ if BIST_MODE == 0
initial_calibration_done <= 1'b1;
end
else begin
@ -2500,28 +2567,53 @@ module ddr3_controller #(
end
end
else begin
data_start_index[lane] <= data_start_index[lane] + 8; //skip by 8
if(data_start_index[lane] == 56) begin //reached the end but no byte in write-pattern matches the data read, issue might be reading at wrong DQS toggle
data_start_index[lane] <= 0; //so we need to recalibrate the bitslip
data_start_index[lane] <= data_start_index[lane] + 8; //skip by 8 (basically we want to delay DQ since it was too early)
if(lane_write_dq_late[lane] && lane_read_dq_early[lane]) begin // both assumption is wrong so we reset the controller
reset_from_calibrate <= 1;
end
// first assumption (write DQ is late) is wrong so we repeat write-read with data_start_index back to 0
else if(lane_write_dq_late[lane]) begin
data_start_index[lane] <= 0; // set delay to outgoing stage2_data back to zero
if(data_start_index[lane] == 0) begin // if already set to zero then we already did write-read with default zero data_start_index, so we go to CHECK_STARTING_DATA to try second assumtpion
state_calibrate <= CHECK_STARTING_DATA;
end
else begin // if not yet zero then we have to write-read again
state_calibrate <= ISSUE_WRITE_1;
end
end
//reached the end but STILL has error, issue might be WRITING TOO LATE (298cd0ad51c1XXXX is written) OR READING TOO EARLY ([9177]_298cd0ad51c1XXXX is read)
else if(data_start_index[lane] == 56) begin
data_start_index[lane] <= 0;
start_index_check <= 0;
state_calibrate <= CHECK_STARTING_DATA;
end
end
end
//check if the data starts not at bit 0 (happens if the DQS toggles early than DQ, this means we are calibrated to read at same
//time as DQS toggles but since DQ is late then we need to look which DQS toggle does DQ actually start)
// check when the 4 MSB of write_pattern {d0ad51c1} starts on read_lane_data (read_lane_data is just the concatenation of read_data_store of a specific lane)
// assumption here read_lane_data ~= 298cd0ad51c1XXXX is written: either because we write too late (thus we need to delay outgoing stage2_data) OR we read too early (thus we need to calibrate incoming iserdes_dq)
CHECK_STARTING_DATA: begin
if(read_lane_data[start_index_check +: 16] == write_pattern[0 +: 16]) begin //check if first
state_calibrate <= BITSLIP_DQS_TRAIN_3;
added_read_pipe[lane] <= { {( 4 - ($clog2(STORED_DQS_SIZE*8) - (3+1)) ){1'b0}} , dq_target_index[lane][$clog2(STORED_DQS_SIZE*8)-1:(3+1)] }
+ { 3'b0 , (dq_target_index[lane][3:0] >= (5+8)) };
dqs_bitslip_arrangement <= 16'b0011_1100_0011_1100 >> dq_target_index[lane][2:0];
state_calibrate <= BITSLIP_DQS_TRAIN_3;
/* verilator lint_off WIDTHTRUNC */
if(read_lane_data[start_index_check +: 32] == write_pattern[0 +: 32]) begin
/* verilator lint_on WIDTHTRUNC */
// first assumption: controller DQ is late WHEN WRITING(THUS WE NEED TO CALIBRATE data_start_index of outgoing stage2_data)
if(!lane_write_dq_late[lane]) begin // lane_write_dq_late is not yet set so we know this first assunmption is not yet tested
state_calibrate <= ISSUE_WRITE_1; // start writing again (the next write should fix the late DQ for this current lane)
data_start_index[lane] <= 64 - start_index_check; // stage2_data_unaligned is forwarded to stage[1] so we are now 8-bursts early, so we subtract from 64 so the burst we will be forwarded to the tip of stage2_data
lane_write_dq_late[lane] <= 1'b1;
end
// if first assumption is not the fix then second assmption: controller reads the DQ too early (THUS WE NEED TO CALIBRATE INCOMING DQ SIGNAL starting from bitslip training)
else begin
lane_read_dq_early[lane] <= 1'b1; // set to 1 to see later what lanes has this problem
state_calibrate <= BITSLIP_DQS_TRAIN_3;
added_read_pipe[lane] <= { {( 4 - ($clog2(STORED_DQS_SIZE*8) - (3+1)) ){1'b0}} , dq_target_index[lane][$clog2(STORED_DQS_SIZE*8)-1:(3+1)] }
+ { 3'b0 , (dq_target_index[lane][3:0] >= (5+8)) };
dqs_bitslip_arrangement <= 16'b0011_1100_0011_1100 >> dq_target_index[lane][2:0];
end
end
else begin
start_index_check <= start_index_check + 16;
start_index_check <= start_index_check + 16; // plus 16, we assume here that DQ will be late BY 1 DDR3 CLK CYCLE (if only +8, then it will be late by half DDR3 cycle, that should NOT happen)
dq_target_index[lane] <= dq_target_index[lane] + 2;
if(dq_target_index[lane][$clog2(STORED_DQS_SIZE*8)] )begin //if last bit goes high, we are outside the possible values so we need to reset now
if(start_index_check == 48)begin //if value is too high, we are outside the possible values so we need to reset now
reset_from_calibrate <= 1;
end
end
@ -2568,36 +2660,25 @@ BITSLIP_DQS_TRAIN_3: if(train_delay == 0) begin //train again the ISERDES to cap
end*/
BURST_WRITE: if(!o_wb_stall_calib) begin // Test 1: Burst write (per byte write to test datamask feature), then burst read
calib_stb <= 1;
calib_stb <= !write_test_address_counter[wb_addr_bits]; // create request only at the valid address space
calib_aux <= 2;
if(TDQS == 0 && ECC_ENABLE == 0) begin //Test datamask by writing 1 byte at a time
calib_sel <= 1 << write_by_byte_counter;
calib_we <= 1;
calib_addr <= write_test_address_counter[wb_addr_bits-1:0];
calib_data <= {wb_sel_bits{8'haa}};
calib_data[8*write_by_byte_counter +: 8] <= write_test_address_counter[7:0];
if(MICRON_SIM) begin
//if(write_test_address_counter[wb_addr_bits-1:0] == 500) begin //inject error at middle
// calib_data <= 1;
//end
if(write_by_byte_counter == {$clog2(wb_sel_bits){1'b1}}) begin
if(write_test_address_counter[wb_addr_bits-1:0] == 99 ) begin //MUST END AT ODD NUMBER
state_calibrate <= BURST_READ;
end
write_test_address_counter <= write_test_address_counter + 1;
end
end
else begin
//if(write_test_address_counter[wb_addr_bits-1:0] == { 2'b00 , 1'b0, {(wb_addr_bits-3){1'b1}} }) begin //inject error at middle
// calib_data <= 1;
// end
if(write_by_byte_counter == {$clog2(wb_sel_bits){1'b1}}) begin
if(write_test_address_counter[wb_addr_bits-1:0] == { 2'b00 , {(wb_addr_bits-2){1'b1}} } ) begin //MUST END AT ODD NUMBER
state_calibrate <= BURST_READ;
end
write_test_address_counter <= write_test_address_counter + 1;
end
// calib_data[8*write_by_byte_counter +: 8] <= write_test_address_counter[7:0];
calib_data[8*write_by_byte_counter +: 8] <= calib_data_randomized[8*write_by_byte_counter +: 8];
if(write_by_byte_counter == {$clog2(wb_sel_bits){1'b1}}) begin
write_test_address_counter <= MICRON_SIM? write_test_address_counter + (2**SIM_ADDRESS_INCR_LOG2) : write_test_address_counter + 1; // at BIST_MODE=1, this will create 128 writes
/* verilator lint_off WIDTHEXPAND */
if((write_test_address_counter[wb_addr_bits-1:0] - MICRON_SIM == { {2{BIST_MODE[1]}} , {(wb_addr_bits-2){1'b1}} }) && (MICRON_SIM? (write_test_address_counter != 0) : 1)) begin //MUST END AT ODD NUMBER
/* verilator lint_on WIDTHEXPAND */
if(BIST_MODE == 2) begin // mode 2 = burst write-read the WHOLE address space so always set the address counter back to zero
write_test_address_counter <= 0;
end
state_calibrate <= BURST_READ;
end
end
write_by_byte_counter <= write_by_byte_counter + 1;
@ -2606,49 +2687,38 @@ BITSLIP_DQS_TRAIN_3: if(train_delay == 0) begin //train again the ISERDES to cap
calib_sel <= {wb_sel_bits{1'b1}};
calib_we <= 1;
calib_addr <= write_test_address_counter[wb_addr_bits-1:0];
calib_data <= {wb_sel_bits{write_test_address_counter[7:0]}};
if(MICRON_SIM) begin
//if(write_test_address_counter[wb_addr_bits-1:0] == 500) begin //inject error at middle
// calib_data <= 1;
//end
if(write_test_address_counter[wb_addr_bits-1:0] == 99 ) begin //MUST END AT ODD NUMBER
state_calibrate <= BURST_READ;
end
end
else begin
//if(write_test_address_counter[wb_addr_bits-1:0] == { 2'b00 , 1'b0, {(wb_addr_bits-3){1'b1}} }) begin //inject error at middle
// calib_data <= 1;
//end
if(write_test_address_counter[wb_addr_bits-1:0] == { 2'b00 , {(wb_addr_bits-2){1'b1}} } ) begin //MUST END AT ODD NUMBER
state_calibrate <= BURST_READ;
end
end
write_test_address_counter <= write_test_address_counter + 1;
// calib_data <= {wb_sel_bits{write_test_address_counter[7:0]}};
calib_data <= calib_data_randomized;
write_test_address_counter <= MICRON_SIM? write_test_address_counter + (2**SIM_ADDRESS_INCR_LOG2) : write_test_address_counter + 1; // at BIST_MODE=1, this will create 128 writes
/* verilator lint_off WIDTHEXPAND */
if((write_test_address_counter[wb_addr_bits-1:0] - MICRON_SIM == { {2{BIST_MODE[1]}} , {(wb_addr_bits-2){1'b1}} }) && (MICRON_SIM? (write_test_address_counter != 0) : 1)) begin //MUST END AT ODD NUMBER
/* verilator lint_on WIDTHEXPAND */
if(BIST_MODE == 2) begin // mode 2 = burst write-read the WHOLE address space so always set the address counter back to zero
write_test_address_counter <= 0;
end
state_calibrate <= BURST_READ;
end
end
end
BURST_READ: if(!o_wb_stall_calib) begin
calib_stb <= 1;
calib_stb <= !read_test_address_counter[wb_addr_bits]; // create request only at the valid address space
calib_aux <= 3;
calib_we <= 0;
calib_addr <= read_test_address_counter;
read_test_address_counter <= read_test_address_counter + 1;
if(MICRON_SIM) begin
if(read_test_address_counter == 99) begin //MUST END AT ODD NUMBER
state_calibrate <= RANDOM_WRITE;
calib_addr <= read_test_address_counter[wb_addr_bits-1:0];
read_test_address_counter <= MICRON_SIM? read_test_address_counter + (2**SIM_ADDRESS_INCR_LOG2) : read_test_address_counter + 1; // at BIST_MODE=1, this will create 128 reads
/* verilator lint_off WIDTHEXPAND */
if((read_test_address_counter - MICRON_SIM == { {2{BIST_MODE[1]}} , {(wb_addr_bits-2){1'b1}} }) && (MICRON_SIM? (read_test_address_counter != 0) : 1)) begin //MUST END AT ODD NUMBER
/* verilator lint_on WIDTHEXPAND */
if(BIST_MODE == 2) begin // mode 2 = burst write-read the WHOLE address space so always set the address counter back to zero
read_test_address_counter <= 0;
end
end
else begin
if(read_test_address_counter == { 2'b00 , {(wb_addr_bits-2){1'b1}} }) begin //MUST END AT ODD NUMBER
state_calibrate <= RANDOM_WRITE;
end
end
state_calibrate <= RANDOM_WRITE;
end
end
RANDOM_WRITE: if(!o_wb_stall_calib) begin // Test 2: Random write (increments row address to force precharge-act-r/w) then random read
calib_stb <= 1;
calib_stb <= !write_test_address_counter[wb_addr_bits]; // create request only at the valid address space
calib_aux <= 2;
calib_sel <= {wb_sel_bits{1'b1}};
calib_we <= 1;
@ -2656,67 +2726,56 @@ BITSLIP_DQS_TRAIN_3: if(train_delay == 0) begin //train again the ISERDES to cap
<= write_test_address_counter[ROW_BITS-1:0]; // store row
calib_addr[(BA_BITS + COL_BITS- $clog2(serdes_ratio*2) - 1 + DUAL_RANK_DIMM) : 0]
<= write_test_address_counter[wb_addr_bits-1:ROW_BITS]; // store bank + col
calib_data <= {wb_sel_bits{write_test_address_counter[7:0]}};
if(MICRON_SIM) begin
//if(write_test_address_counter[wb_addr_bits-1:0] == 1500) begin //inject error
// calib_data <= 1;
//end
if(write_test_address_counter[wb_addr_bits-1:0] == 199) begin //MUST END AT ODD NUMBER since ALTERNATE_WRITE_READ must start at even
state_calibrate <= RANDOM_READ;
// calib_data <= {wb_sel_bits{write_test_address_counter[7:0]}};
calib_data <= calib_data_randomized;
write_test_address_counter <= MICRON_SIM? write_test_address_counter + (2**SIM_ADDRESS_INCR_LOG2) : write_test_address_counter + 1; // at BIST_MODE=1, this will create 128 writes
/* verilator lint_off WIDTHEXPAND */
if((write_test_address_counter[wb_addr_bits-1:0] - MICRON_SIM == { 1'b1, BIST_MODE[1] , {(wb_addr_bits-2){1'b1}} }) && (MICRON_SIM? (write_test_address_counter != 0) : 1)) begin //MUST END AT ODD NUMBER since ALTERNATE_WRITE_READ must start at even
/* verilator lint_on WIDTHEXPAND */
if(BIST_MODE == 2) begin // mode 2 = random write-read the WHOLE address space so always set the address counter back to zero
write_test_address_counter <= 0;
end
state_calibrate <= RANDOM_READ;
end
else begin
// if(write_test_address_counter[wb_addr_bits-1:0] == { 2'b01 , 1'b0, {(wb_addr_bits-3){1'b1}}} ) begin //inject error
// calib_data <= 1;
// end
if(write_test_address_counter[wb_addr_bits-1:0] == { 2'b01 , {(wb_addr_bits-2){1'b1}} } ) begin //MUST END AT ODD NUMBER since ALTERNATE_WRITE_READ must start at even
state_calibrate <= RANDOM_READ;
end
end
write_test_address_counter <= write_test_address_counter + 1;
end
RANDOM_READ: if(!o_wb_stall_calib) begin
calib_stb <= 1;
calib_stb <= !read_test_address_counter[wb_addr_bits]; // create request only at the valid address space
calib_aux <= 3;
calib_we <= 0;
calib_addr[ (ROW_BITS + BA_BITS + COL_BITS- $clog2(serdes_ratio*2) - 1 + DUAL_RANK_DIMM) : (BA_BITS + COL_BITS- $clog2(serdes_ratio*2) + DUAL_RANK_DIMM) ]
<= read_test_address_counter[ROW_BITS-1:0]; // row
calib_addr[(BA_BITS + COL_BITS- $clog2(serdes_ratio*2) - 1 + DUAL_RANK_DIMM) : 0]
<= read_test_address_counter[wb_addr_bits-1:ROW_BITS]; // bank + col
read_test_address_counter <= read_test_address_counter + 1;
if(MICRON_SIM) begin
if(read_test_address_counter == 199) begin //MUST END AT ODD NUMBER since ALTERNATE_WRITE_READ must start at even
state_calibrate <= ALTERNATE_WRITE_READ;
end
end
else begin
if(read_test_address_counter == { 2'b01 , {(wb_addr_bits-2){1'b1}} } ) begin //MUST END AT ODD NUMBER since ALTERNATE_WRITE_READ must start at even
state_calibrate <= ALTERNATE_WRITE_READ;
read_test_address_counter <= MICRON_SIM? read_test_address_counter + (2**SIM_ADDRESS_INCR_LOG2) : read_test_address_counter + 1; // at BIST_MODE=1, this will create 128 reads
/* verilator lint_off WIDTHEXPAND */
if((read_test_address_counter - MICRON_SIM == { 1'b1 , BIST_MODE[1], {(wb_addr_bits-2){1'b1}} }) && (MICRON_SIM? (read_test_address_counter != 0) : 1)) begin //MUST END AT ODD NUMBER since ALTERNATE_WRITE_READ must start at even
/* verilator lint_on WIDTHEXPAND */
if(BIST_MODE == 2) begin // mode 2 = random write-read the WHOLE address space so always set the address counter back to zero
read_test_address_counter <= 0;
end
state_calibrate <= ALTERNATE_WRITE_READ;
end
end
ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
calib_stb <= 1;
calib_aux <= 4 + { {(AUX_WIDTH-1){1'b0}} , write_test_address_counter[0]}; //4 (write), 5 (read)
calib_stb <= !write_test_address_counter[wb_addr_bits]; // create request only at the valid address space
calib_aux <= 2 + (calib_we? 1:0); //2 (write), 3 (read)
calib_sel <= {wb_sel_bits{1'b1}};
calib_we <= !write_test_address_counter[0]; //0(write) -> 1(read)
calib_addr <= {1'b0, write_test_address_counter[wb_addr_bits-1:1]}; //same address to be used for write and read ( so basically write then read instantly)
calib_data <= {wb_sel_bits{write_test_address_counter[7:0]}};
if(MICRON_SIM) begin
if(write_test_address_counter == 499) begin
train_delay <= 15;
state_calibrate <= FINISH_READ;
end
calib_we <= !calib_we; // alternating write-read
calib_addr <= write_test_address_counter[wb_addr_bits-1:0];
// calib_data <= {wb_sel_bits{write_test_address_counter[7:0]}};
calib_data <= calib_data_randomized;
if(calib_we) begin // if current operation is write, then dont increment address since we wil read the same address next
write_test_address_counter <= MICRON_SIM? write_test_address_counter + (2**SIM_ADDRESS_INCR_LOG2) : write_test_address_counter + 1; // at BIST_MODE=1, this will create 128 writes
end
else begin
if(write_test_address_counter[wb_addr_bits-1:0] == { 2'b11 , {(wb_addr_bits-2){1'b1}} } ) begin
train_delay <= 15;
state_calibrate <= FINISH_READ;
end
/* verilator lint_off WIDTHEXPAND */
if((write_test_address_counter[wb_addr_bits-1:0] - MICRON_SIM == { 2'b11 , {(wb_addr_bits-2){1'b1}} }) && (MICRON_SIM? (write_test_address_counter != 0) : 1)) begin
/* verilator lint_on WIDTHEXPAND */
train_delay <= 15;
state_calibrate <= FINISH_READ;
end
write_test_address_counter <= write_test_address_counter + 1;
end
FINISH_READ: begin
calib_stb <= 0;
@ -2776,6 +2835,19 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
end
end
end
// generate calib_data for BIST
// Uses different operations (XOR, addition, subtraction, bit rotation) to generate different values per byte.
// When MICRON_SIM=1, then we use the relevant bits (7:0 will be zero since during simulation the increment is a large number)
assign calib_data_randomized = {
{(wb_sel_bits/8){write_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'hA5, // Byte 7
write_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] | 8'h1A, // Byte 7
write_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] & 8'h33, // Byte 5
write_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h5A, // Byte 4
write_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] & 8'h21, // Byte 3
write_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] | 8'hC7, // Byte 1
write_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h7E, // Byte 1
write_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h3C}} // Byte 0
};
generate
if(DUAL_RANK_DIMM[0]) begin : dual_rank_mux
@ -2809,18 +2881,46 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
generate
if(ECC_ENABLE == 0 || ECC_ENABLE == 3) begin : ecc_enable_0_correct_data
assign correct_data = {wb_sel_bits{check_test_address_counter[7:0]}};
// assign correct_data = {wb_sel_bits{check_test_address_counter[7:0]}};
assign correct_data = {
{(wb_sel_bits/8){check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'hA5, // Byte 7
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] | 8'h1A, // Byte 7
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] & 8'h33, // Byte 5
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h5A, // Byte 4
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] & 8'h21, // Byte 3
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] | 8'hC7, // Byte 1
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h7E, // Byte 1
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h3C }} // Byte 0
};
end
else if(ECC_ENABLE == 1) begin : ecc_enable_1_correct_data
wire[wb_data_bits-1:0] correct_data_orig;
assign correct_data_orig = {wb_sel_bits{check_test_address_counter[7:0]}};
// assign correct_data_orig = {wb_sel_bits{check_test_address_counter[7:0]}};
assign correct_data_orig = {
{(wb_sel_bits/8){check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'hA5, // Byte 7
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] | 8'h1A, // Byte 7
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] & 8'h33, // Byte 5
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h5A, // Byte 4
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] & 8'h21, // Byte 3
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] | 8'hC7, // Byte 1
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h7E, // Byte 1
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h3C}} // Byte 0
};
assign correct_data = {{(wb_data_bits-ECC_INFORMATION_BITS*8){1'b0}} , correct_data_orig[ECC_INFORMATION_BITS*8 - 1 : 0]}; //only ECC_INFORMATION_BITS are valid in o_wb_data
end
else if(ECC_ENABLE == 2) begin : ecc_enable_2_correct_data
wire[wb_data_bits-1:0] correct_data_orig;
assign correct_data_orig = {wb_sel_bits{check_test_address_counter[7:0]}};
// assign correct_data_orig = {wb_sel_bits{check_test_address_counter[7:0]}};
assign correct_data_orig = {
{(wb_sel_bits/8){check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'hA5, // Byte 7
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] | 8'h1A, // Byte 7
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] & 8'h33, // Byte 5
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h5A, // Byte 4
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] & 8'h21, // Byte 3
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] | 8'hC7, // Byte 1
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h7E, // Byte 1
check_test_address_counter[(MICRON_SIM? SIM_ADDRESS_INCR_LOG2:0) +: 8] ^ 8'h3C}} // Byte 0
};
assign correct_data = {{(wb_data_bits-ECC_INFORMATION_BITS){1'b0}} , correct_data_orig[ECC_INFORMATION_BITS - 1 : 0]}; //only ECC_INFORMATION_BITS are valid in o_wb_data
end
endgenerate
@ -2835,7 +2935,7 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
else begin
reset_from_test <= 0;
if(state_calibrate != DONE_CALIBRATE) begin
if ( (o_aux[2:0] == 3'd3 || o_aux[2:0] == 3'd5) && o_wb_ack_uncalibrated ) begin
if ( o_aux[2:0] == 3'd3 && o_wb_ack_uncalibrated ) begin //o_aux = 3 is for read from calibration
if(o_wb_data == correct_data) begin
correct_read_data <= correct_read_data + 1;
end
@ -2845,7 +2945,7 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
reset_from_test <= !final_calibration_done; //reset controller when a wrong data is received (only when calibration is not yet done)
end
/* verilator lint_off WIDTHEXPAND */
check_test_address_counter <= check_test_address_counter + 1 + (o_aux[2:0] == 3'd5); // alternate write read when aux == 5
check_test_address_counter <= check_test_address_counter + (MICRON_SIM? (2**SIM_ADDRESS_INCR_LOG2) : 1);
/* verilator lint_on WIDTHEXPAND */
end
end
@ -3465,6 +3565,7 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
$display("ACTIVATE_TO_WRITE_DELAY = %0d", ACTIVATE_TO_WRITE_DELAY);
$display("ACTIVATE_TO_READ_DELAY = %0d", ACTIVATE_TO_READ_DELAY);
$display("ACTIVATE_TO_PRECHARGE_DELAY = %0d", ACTIVATE_TO_PRECHARGE_DELAY);
$display("ACTIVATE_TO_ACTIVATE_DELAY = %0d", ACTIVATE_TO_ACTIVATE_DELAY);
$display("READ_TO_WRITE_DELAY = %0d", READ_TO_WRITE_DELAY);
$display("READ_TO_READ_DELAY = %0d", READ_TO_READ_DELAY);
$display("READ_TO_PRECHARGE_DELAY = %0d", READ_TO_PRECHARGE_DELAY);
@ -3488,7 +3589,7 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
$display("ODELAY_SUPPORTED = %0d", ODELAY_SUPPORTED);
$display("SECOND_WISHBONE = %0d", SECOND_WISHBONE);
$display("WB_ERROR = %0d", WB_ERROR);
$display("SKIP_INTERNAL_TEST = %0d", SKIP_INTERNAL_TEST);
$display("BIST_MODE = %0d", BIST_MODE);
$display("ECC_ENABLE = %0d", ECC_ENABLE);
$display("DIC = %0d", DIC);
$display("RTT_NOM = %0d", RTT_NOM);
@ -4415,7 +4516,7 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
assert(stage1_pending == 0 && stage2_pending == 0);
end
if(state_calibrate <= ISSUE_READ) begin
if((state_calibrate <= ISSUE_READ) || (state_calibrate >= ANALYZE_DATA && state_calibrate <= BITSLIP_DQS_TRAIN_3)) begin // add ANALYZE_DATA and BITSLIP_DQS_TRAIN_3
for(f_index_1 = 0; f_index_1 < 1; f_index_1 = f_index_1 + 1) begin
assert(o_wb_ack_read_q[f_index_1] == 0);
end
@ -4432,7 +4533,7 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
assert(o_wb_ack == 0); //o_wb_ack must not go high before done calibration
end
if(state_calibrate > ISSUE_WRITE_1 && state_calibrate <= ANALYZE_DATA) begin
if(state_calibrate > ISSUE_WRITE_1 && state_calibrate <= READ_DATA) begin
if(stage1_pending) begin
assert(!stage1_we == stage1_aux[0]); //if write, then aux id must be 1 else 0
assert(stage1_aux[2:1] == 2'b00);

2
rtl/ddr3_phy.v
View File

@ -28,7 +28,7 @@
//
////////////////////////////////////////////////////////////////////////////////
`default_nettype none
// `default_nettype none
`timescale 1ps / 1ps
//`define DEBUG_DQS // uncomment to route the raw DQS to output port for debugging

54
rtl/ddr3_top.v
View File

@ -27,7 +27,7 @@
//
////////////////////////////////////////////////////////////////////////////////
`default_nettype none
//`default_nettype none
`timescale 1ps / 1ps
module ddr3_top #(
@ -51,7 +51,7 @@ module ddr3_top #(
ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
SKIP_INTERNAL_TEST = 0, // skip built-in self test (would require >2 seconds of internal test right after calibration)
parameter[1:0] BIST_MODE = 1, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)
@ -259,7 +259,7 @@ ddr3_top #(
.SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone is needed
.ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
.WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
.SKIP_INTERNAL_TEST(SKIP_INTERNAL_TEST), // skip built-in self test (would require >2 seconds of internal test right after calibration)
.BIST_MODE(BIST_MODE), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
.DIC(DIC), //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms)
.RTT_NOM(RTT_NOM), //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
.DUAL_RANK_DIMM(DUAL_RANK_DIMM), // enable dual rank DIMM (1 = enable, 0 = disable)
@ -386,29 +386,29 @@ ddr3_top #(
.o_ddr3_debug_read_dqs_n(/*o_ddr3_debug_read_dqs_n*/)
);
// display value of parameters for easy debugging
initial begin
$display("\nDDR3 TOP PARAMETERS:\n-----------------------------");
$display("CONTROLLER_CLK_PERIOD = %0d", CONTROLLER_CLK_PERIOD);
$display("DDR3_CLK_PERIOD = %0d", DDR3_CLK_PERIOD);
$display("ROW_BITS = %0d", ROW_BITS);
$display("COL_BITS = %0d", COL_BITS);
$display("BA_BITS = %0d", BA_BITS);
$display("BYTE_LANES = %0d", BYTE_LANES);
$display("AUX_WIDTH = %0d", AUX_WIDTH);
$display("WB2_ADDR_BITS = %0d", WB2_ADDR_BITS);
$display("WB2_DATA_BITS = %0d", WB2_DATA_BITS);
$display("MICRON_SIM = %0d", MICRON_SIM);
$display("ODELAY_SUPPORTED = %0d", ODELAY_SUPPORTED);
$display("SECOND_WISHBONE = %0d", SECOND_WISHBONE);
$display("WB_ERROR = %0d", WB_ERROR);
$display("SKIP_INTERNAL_TEST = %0d", SKIP_INTERNAL_TEST);
$display("ECC_ENABLE = %0d", ECC_ENABLE);
$display("DIC = %0d", DIC);
$display("RTT_NOM = %0d", RTT_NOM);
$display("SELF_REFRESH = %0d", SELF_REFRESH);
$display("DUAL_RANK_DIMM = %0d", DUAL_RANK_DIMM);
$display("End of DDR3 TOP PARAMETERS\n-----------------------------");
end
// // display value of parameters for easy debugging
// initial begin
// $display("\nDDR3 TOP PARAMETERS:\n-----------------------------");
// $display("CONTROLLER_CLK_PERIOD = %0d", CONTROLLER_CLK_PERIOD);
// $display("DDR3_CLK_PERIOD = %0d", DDR3_CLK_PERIOD);
// $display("ROW_BITS = %0d", ROW_BITS);
// $display("COL_BITS = %0d", COL_BITS);
// $display("BA_BITS = %0d", BA_BITS);
// $display("BYTE_LANES = %0d", BYTE_LANES);
// $display("AUX_WIDTH = %0d", AUX_WIDTH);
// $display("WB2_ADDR_BITS = %0d", WB2_ADDR_BITS);
// $display("WB2_DATA_BITS = %0d", WB2_DATA_BITS);
// $display("MICRON_SIM = %0d", MICRON_SIM);
// $display("ODELAY_SUPPORTED = %0d", ODELAY_SUPPORTED);
// $display("SECOND_WISHBONE = %0d", SECOND_WISHBONE);
// $display("WB_ERROR = %0d", WB_ERROR);
// $display("BIST_MODE = %0d", BIST_MODE);
// $display("ECC_ENABLE = %0d", ECC_ENABLE);
// $display("DIC = %0d", DIC);
// $display("RTT_NOM = %0d", RTT_NOM);
// $display("SELF_REFRESH = %0d", SELF_REFRESH);
// $display("DUAL_RANK_DIMM = %0d", DUAL_RANK_DIMM);
// $display("End of DDR3 TOP PARAMETERS\n-----------------------------");
// end
endmodule

18
testbench/8192Mb_ddr3_parameters.vh
View File

@ -425,15 +425,15 @@
parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
parameter DEBUG = 0; // Turn on Debug messages
parameter BUS_DELAY = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_0 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_1 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_2 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_3 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_4 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_5 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_6 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_7 = 0; // delay in picoseconds
parameter BUS_DELAY = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_0 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_1 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_2 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_3 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_4 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_5 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_6 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_7 = 0; // delay in picoseconds
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
parameter RANDOM_SEED = 31913; //seed value for random generator.

83
testbench/README.txt Normal file
View File

@ -0,0 +1,83 @@
################################################################################
# Vivado (TM) v2022.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "xcelium", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.

4
testbench/ddr3.sv
View File

@ -94,9 +94,6 @@
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
`define den8192Mb
`define sg125
`define x16
`default_nettype wire
module ddr3 (
@ -117,6 +114,7 @@ module ddr3 (
tdqs_n,
odt
);
`include "sim_defines.vh"
`ifdef den1024Mb
`include "1024Mb_ddr3_parameters.vh"

23
testbench/ddr3_dimm_micron_sim.sv
View File

@ -27,16 +27,11 @@
////////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
`define den8192Mb
`define sg125
`define x16
//`define USE_CLOCK_WIZARD
`define TWO_LANES_x8
//`define EIGHT_LANES_x8
`define RAM_8Gb
//`define XADC
module ddr3_dimm_micron_sim;
`include "sim_defines.vh" // contains defines for simulation
`ifdef den1024Mb
`include "1024Mb_ddr3_parameters.vh"
`elsif den2048Mb
@ -53,22 +48,23 @@ module ddr3_dimm_micron_sim;
`ifdef TWO_LANES_x8
localparam BYTE_LANES = 2,
ODELAY_SUPPORTED = 0;
ODELAY_SUPPORTED = 1;
`endif
`ifdef EIGHT_LANES_x8
localparam BYTE_LANES = 8,
ODELAY_SUPPORTED = 0;
ODELAY_SUPPORTED = 1;
`endif
localparam CONTROLLER_CLK_PERIOD = 10_000, //ps, period of clock input to this DDR3 controller module
DDR3_CLK_PERIOD = 2500,//ps, period of clock input to DDR3 RAM device
localparam CONTROLLER_CLK_PERIOD = 12_000, //ps, period of clock input to this DDR3 controller module
DDR3_CLK_PERIOD = 3_000, //ps, period of clock input to DDR3 RAM device
AUX_WIDTH = 16, // AUX lines
ECC_ENABLE = 0, // ECC enable
SELF_REFRESH = 2'b00,
DUAL_RANK_DIMM = 0,
TEST_SELF_REFRESH = 0;
TEST_SELF_REFRESH = 0,
BIST_MODE = 1; // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
@ -118,7 +114,6 @@ module ddr3_dimm_micron_sim;
// temperature
wire user_temp_alarm_out;
`ifdef USE_CLOCK_WIZARD
// Use clock wizard
reg i_clk;
@ -173,7 +168,7 @@ ddr3_top #(
.SECOND_WISHBONE(0), //set to 1 if 2nd wishbone for debugging is needed
.ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
.WB_ERROR(1), // set to 1 to support Wishbone error (asserts at ECC double bit error)
.SKIP_INTERNAL_TEST(0), // skip built-in self test (would require >2 seconds of internal test right after calibration)
.BIST_MODE(BIST_MODE), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
.SELF_REFRESH(SELF_REFRESH), // 0 = use i_user_self_refresh input, 1 = Self-refresh mode is enabled after 64 controller clock cycles of no requests, 2 = 128 cycles, 3 = 256 cycles
.DUAL_RANK_DIMM(DUAL_RANK_DIMM) // enable dual rank DIMM (1 = enable, 0 = disable)
) ddr3_top
@ -286,6 +281,8 @@ ddr3_top #(
.dclk_in(i_controller_clk), // Clock input for the dynamic reconfiguration port
.user_temp_alarm_out(user_temp_alarm_out) // Temperature-sensor alarm output
);
`else
assign user_temp_alarm_out = 0;
`endif

642
testbench/ddr3_dimm_micron_sim_behav.wcfg
View File

@ -11,15 +11,20 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0.000000 us"></ZoomStartTime>
<ZoomEndTime time="55.000001 us"></ZoomEndTime>
<Cursor1Time time="33.460000 us"></Cursor1Time>
<ZoomStartTime time="60.369478 us"></ZoomStartTime>
<ZoomEndTime time="168.769479 us"></ZoomEndTime>
<Cursor1Time time="150.702812 us"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="272"></NameColumnWidth>
<ValueColumnWidth column_width="125"></ValueColumnWidth>
<ValueColumnWidth column_width="113"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="52" />
<WVObjectSize size="69" />
<wave_markers>
<marker label="" time="37605000" />
<marker label="" time="37825000" />
<marker label="" time="35865000" />
</wave_markers>
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">Clocks and Reset</obj_property>
<obj_property name="DisplayName">label</obj_property>
@ -44,6 +49,14 @@
<obj_property name="ElementShortName">i_ref_clk</obj_property>
<obj_property name="ObjectShortName">i_ref_clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_rst_n">
<obj_property name="ElementShortName">i_rst_n</obj_property>
<obj_property name="ObjectShortName">i_rst_n</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/sync_rst">
<obj_property name="ElementShortName">sync_rst</obj_property>
<obj_property name="ObjectShortName">sync_rst</obj_property>
</wvobject>
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">Self-refresh</obj_property>
<obj_property name="DisplayName">label</obj_property>
@ -56,9 +69,10 @@
<obj_property name="ElementShortName">user_self_refresh_q</obj_property>
<obj_property name="ObjectShortName">user_self_refresh_q</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cke">
<obj_property name="ElementShortName">o_ddr3_cke</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cke</obj_property>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cke">
<obj_property name="ElementShortName">o_ddr3_cke[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cke[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/refresh_counter">
<obj_property name="ElementShortName">refresh_counter[8:0]</obj_property>
@ -73,14 +87,493 @@
<obj_property name="ElementShortName">i_wb_stb</obj_property>
<obj_property name="ObjectShortName">i_wb_stb</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/cmd_ck_en">
<obj_property name="ElementShortName">cmd_ck_en[0:0]</obj_property>
<obj_property name="ObjectShortName">cmd_ck_en[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/cmd_ck_en[0]">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">[0]</obj_property>
<obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/prev_cmd_ck_en">
<obj_property name="ElementShortName">prev_cmd_ck_en[0:0]</obj_property>
<obj_property name="ObjectShortName">prev_cmd_ck_en[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/prev_cmd_ck_en[0]">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">[0]</obj_property>
<obj_property name="CustomSignalColor">#FFA500</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd">
<obj_property name="ElementShortName">i_controller_cmd[103:0]</obj_property>
<obj_property name="ObjectShortName">i_controller_cmd[103:0]</obj_property>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[103]">
<obj_property name="ElementShortName">[103]</obj_property>
<obj_property name="ObjectShortName">[103]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[102]">
<obj_property name="ElementShortName">[102]</obj_property>
<obj_property name="ObjectShortName">[102]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[101]">
<obj_property name="ElementShortName">[101]</obj_property>
<obj_property name="ObjectShortName">[101]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[100]">
<obj_property name="ElementShortName">[100]</obj_property>
<obj_property name="ObjectShortName">[100]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[99]">
<obj_property name="ElementShortName">[99]</obj_property>
<obj_property name="ObjectShortName">[99]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[98]">
<obj_property name="ElementShortName">[98]</obj_property>
<obj_property name="ObjectShortName">[98]</obj_property>
<obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[97]">
<obj_property name="ElementShortName">[97]</obj_property>
<obj_property name="ObjectShortName">[97]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[96]">
<obj_property name="ElementShortName">[96]</obj_property>
<obj_property name="ObjectShortName">[96]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[95]">
<obj_property name="ElementShortName">[95]</obj_property>
<obj_property name="ObjectShortName">[95]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[94]">
<obj_property name="ElementShortName">[94]</obj_property>
<obj_property name="ObjectShortName">[94]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[93]">
<obj_property name="ElementShortName">[93]</obj_property>
<obj_property name="ObjectShortName">[93]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[92]">
<obj_property name="ElementShortName">[92]</obj_property>
<obj_property name="ObjectShortName">[92]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[91]">
<obj_property name="ElementShortName">[91]</obj_property>
<obj_property name="ObjectShortName">[91]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[90]">
<obj_property name="ElementShortName">[90]</obj_property>
<obj_property name="ObjectShortName">[90]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[89]">
<obj_property name="ElementShortName">[89]</obj_property>
<obj_property name="ObjectShortName">[89]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[88]">
<obj_property name="ElementShortName">[88]</obj_property>
<obj_property name="ObjectShortName">[88]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[87]">
<obj_property name="ElementShortName">[87]</obj_property>
<obj_property name="ObjectShortName">[87]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[86]">
<obj_property name="ElementShortName">[86]</obj_property>
<obj_property name="ObjectShortName">[86]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[85]">
<obj_property name="ElementShortName">[85]</obj_property>
<obj_property name="ObjectShortName">[85]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[84]">
<obj_property name="ElementShortName">[84]</obj_property>
<obj_property name="ObjectShortName">[84]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[83]">
<obj_property name="ElementShortName">[83]</obj_property>
<obj_property name="ObjectShortName">[83]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[82]">
<obj_property name="ElementShortName">[82]</obj_property>
<obj_property name="ObjectShortName">[82]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[81]">
<obj_property name="ElementShortName">[81]</obj_property>
<obj_property name="ObjectShortName">[81]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[80]">
<obj_property name="ElementShortName">[80]</obj_property>
<obj_property name="ObjectShortName">[80]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[79]">
<obj_property name="ElementShortName">[79]</obj_property>
<obj_property name="ObjectShortName">[79]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[78]">
<obj_property name="ElementShortName">[78]</obj_property>
<obj_property name="ObjectShortName">[78]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[77]">
<obj_property name="ElementShortName">[77]</obj_property>
<obj_property name="ObjectShortName">[77]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[76]">
<obj_property name="ElementShortName">[76]</obj_property>
<obj_property name="ObjectShortName">[76]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[75]">
<obj_property name="ElementShortName">[75]</obj_property>
<obj_property name="ObjectShortName">[75]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[74]">
<obj_property name="ElementShortName">[74]</obj_property>
<obj_property name="ObjectShortName">[74]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[73]">
<obj_property name="ElementShortName">[73]</obj_property>
<obj_property name="ObjectShortName">[73]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[72]">
<obj_property name="ElementShortName">[72]</obj_property>
<obj_property name="ObjectShortName">[72]</obj_property>
<obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[71]">
<obj_property name="ElementShortName">[71]</obj_property>
<obj_property name="ObjectShortName">[71]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[70]">
<obj_property name="ElementShortName">[70]</obj_property>
<obj_property name="ObjectShortName">[70]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[69]">
<obj_property name="ElementShortName">[69]</obj_property>
<obj_property name="ObjectShortName">[69]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[68]">
<obj_property name="ElementShortName">[68]</obj_property>
<obj_property name="ObjectShortName">[68]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[67]">
<obj_property name="ElementShortName">[67]</obj_property>
<obj_property name="ObjectShortName">[67]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[66]">
<obj_property name="ElementShortName">[66]</obj_property>
<obj_property name="ObjectShortName">[66]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[65]">
<obj_property name="ElementShortName">[65]</obj_property>
<obj_property name="ObjectShortName">[65]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[64]">
<obj_property name="ElementShortName">[64]</obj_property>
<obj_property name="ObjectShortName">[64]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[63]">
<obj_property name="ElementShortName">[63]</obj_property>
<obj_property name="ObjectShortName">[63]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[62]">
<obj_property name="ElementShortName">[62]</obj_property>
<obj_property name="ObjectShortName">[62]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[61]">
<obj_property name="ElementShortName">[61]</obj_property>
<obj_property name="ObjectShortName">[61]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[60]">
<obj_property name="ElementShortName">[60]</obj_property>
<obj_property name="ObjectShortName">[60]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[59]">
<obj_property name="ElementShortName">[59]</obj_property>
<obj_property name="ObjectShortName">[59]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[58]">
<obj_property name="ElementShortName">[58]</obj_property>
<obj_property name="ObjectShortName">[58]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[57]">
<obj_property name="ElementShortName">[57]</obj_property>
<obj_property name="ObjectShortName">[57]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[56]">
<obj_property name="ElementShortName">[56]</obj_property>
<obj_property name="ObjectShortName">[56]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[55]">
<obj_property name="ElementShortName">[55]</obj_property>
<obj_property name="ObjectShortName">[55]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[54]">
<obj_property name="ElementShortName">[54]</obj_property>
<obj_property name="ObjectShortName">[54]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[53]">
<obj_property name="ElementShortName">[53]</obj_property>
<obj_property name="ObjectShortName">[53]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[52]">
<obj_property name="ElementShortName">[52]</obj_property>
<obj_property name="ObjectShortName">[52]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[51]">
<obj_property name="ElementShortName">[51]</obj_property>
<obj_property name="ObjectShortName">[51]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[50]">
<obj_property name="ElementShortName">[50]</obj_property>
<obj_property name="ObjectShortName">[50]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[49]">
<obj_property name="ElementShortName">[49]</obj_property>
<obj_property name="ObjectShortName">[49]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[48]">
<obj_property name="ElementShortName">[48]</obj_property>
<obj_property name="ObjectShortName">[48]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[47]">
<obj_property name="ElementShortName">[47]</obj_property>
<obj_property name="ObjectShortName">[47]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[46]">
<obj_property name="ElementShortName">[46]</obj_property>
<obj_property name="ObjectShortName">[46]</obj_property>
<obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[45]">
<obj_property name="ElementShortName">[45]</obj_property>
<obj_property name="ObjectShortName">[45]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[44]">
<obj_property name="ElementShortName">[44]</obj_property>
<obj_property name="ObjectShortName">[44]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[43]">
<obj_property name="ElementShortName">[43]</obj_property>
<obj_property name="ObjectShortName">[43]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[42]">
<obj_property name="ElementShortName">[42]</obj_property>
<obj_property name="ObjectShortName">[42]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[41]">
<obj_property name="ElementShortName">[41]</obj_property>
<obj_property name="ObjectShortName">[41]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[40]">
<obj_property name="ElementShortName">[40]</obj_property>
<obj_property name="ObjectShortName">[40]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[39]">
<obj_property name="ElementShortName">[39]</obj_property>
<obj_property name="ObjectShortName">[39]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[38]">
<obj_property name="ElementShortName">[38]</obj_property>
<obj_property name="ObjectShortName">[38]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[37]">
<obj_property name="ElementShortName">[37]</obj_property>
<obj_property name="ObjectShortName">[37]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[36]">
<obj_property name="ElementShortName">[36]</obj_property>
<obj_property name="ObjectShortName">[36]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[35]">
<obj_property name="ElementShortName">[35]</obj_property>
<obj_property name="ObjectShortName">[35]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[34]">
<obj_property name="ElementShortName">[34]</obj_property>
<obj_property name="ObjectShortName">[34]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[33]">
<obj_property name="ElementShortName">[33]</obj_property>
<obj_property name="ObjectShortName">[33]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[32]">
<obj_property name="ElementShortName">[32]</obj_property>
<obj_property name="ObjectShortName">[32]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[31]">
<obj_property name="ElementShortName">[31]</obj_property>
<obj_property name="ObjectShortName">[31]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[30]">
<obj_property name="ElementShortName">[30]</obj_property>
<obj_property name="ObjectShortName">[30]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[29]">
<obj_property name="ElementShortName">[29]</obj_property>
<obj_property name="ObjectShortName">[29]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[28]">
<obj_property name="ElementShortName">[28]</obj_property>
<obj_property name="ObjectShortName">[28]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[27]">
<obj_property name="ElementShortName">[27]</obj_property>
<obj_property name="ObjectShortName">[27]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[26]">
<obj_property name="ElementShortName">[26]</obj_property>
<obj_property name="ObjectShortName">[26]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[25]">
<obj_property name="ElementShortName">[25]</obj_property>
<obj_property name="ObjectShortName">[25]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[24]">
<obj_property name="ElementShortName">[24]</obj_property>
<obj_property name="ObjectShortName">[24]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[23]">
<obj_property name="ElementShortName">[23]</obj_property>
<obj_property name="ObjectShortName">[23]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[22]">
<obj_property name="ElementShortName">[22]</obj_property>
<obj_property name="ObjectShortName">[22]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[21]">
<obj_property name="ElementShortName">[21]</obj_property>
<obj_property name="ObjectShortName">[21]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[20]">
<obj_property name="ElementShortName">[20]</obj_property>
<obj_property name="ObjectShortName">[20]</obj_property>
<obj_property name="CustomSignalColor">#FF00FF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[19]">
<obj_property name="ElementShortName">[19]</obj_property>
<obj_property name="ObjectShortName">[19]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[18]">
<obj_property name="ElementShortName">[18]</obj_property>
<obj_property name="ObjectShortName">[18]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[17]">
<obj_property name="ElementShortName">[17]</obj_property>
<obj_property name="ObjectShortName">[17]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[16]">
<obj_property name="ElementShortName">[16]</obj_property>
<obj_property name="ObjectShortName">[16]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[15]">
<obj_property name="ElementShortName">[15]</obj_property>
<obj_property name="ObjectShortName">[15]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[14]">
<obj_property name="ElementShortName">[14]</obj_property>
<obj_property name="ObjectShortName">[14]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[13]">
<obj_property name="ElementShortName">[13]</obj_property>
<obj_property name="ObjectShortName">[13]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[12]">
<obj_property name="ElementShortName">[12]</obj_property>
<obj_property name="ObjectShortName">[12]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[11]">
<obj_property name="ElementShortName">[11]</obj_property>
<obj_property name="ObjectShortName">[11]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[10]">
<obj_property name="ElementShortName">[10]</obj_property>
<obj_property name="ObjectShortName">[10]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[9]">
<obj_property name="ElementShortName">[9]</obj_property>
<obj_property name="ObjectShortName">[9]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[8]">
<obj_property name="ElementShortName">[8]</obj_property>
<obj_property name="ObjectShortName">[8]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[7]">
<obj_property name="ElementShortName">[7]</obj_property>
<obj_property name="ObjectShortName">[7]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[6]">
<obj_property name="ElementShortName">[6]</obj_property>
<obj_property name="ObjectShortName">[6]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[5]">
<obj_property name="ElementShortName">[5]</obj_property>
<obj_property name="ObjectShortName">[5]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[4]">
<obj_property name="ElementShortName">[4]</obj_property>
<obj_property name="ObjectShortName">[4]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[3]">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">[3]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[2]">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">[2]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[1]">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">[1]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[0]">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">[0]</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">Calibration</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/odelay_cntvalue_halfway">
<obj_property name="ElementShortName">odelay_cntvalue_halfway</obj_property>
<obj_property name="ObjectShortName">odelay_cntvalue_halfway</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/write_level_fail">
<obj_property name="ElementShortName">write_level_fail[7:0]</obj_property>
<obj_property name="ObjectShortName">write_level_fail[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/prev_write_level_feedback">
<obj_property name="ElementShortName">prev_write_level_feedback</obj_property>
<obj_property name="ObjectShortName">prev_write_level_feedback</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/stored_write_level_feedback">
<obj_property name="ElementShortName">stored_write_level_feedback</obj_property>
<obj_property name="ObjectShortName">stored_write_level_feedback</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/sample_clk_repeat">
<obj_property name="ElementShortName">sample_clk_repeat[3:0]</obj_property>
<obj_property name="ObjectShortName">sample_clk_repeat[3:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/initial_calibration_done">
<obj_property name="ElementShortName">initial_calibration_done</obj_property>
<obj_property name="ObjectShortName">initial_calibration_done</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/state_calibrate">
<obj_property name="ElementShortName">state_calibrate[4:0]</obj_property>
<obj_property name="ObjectShortName">state_calibrate[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/instruction_address">
<obj_property name="ElementShortName">instruction_address[4:0]</obj_property>
<obj_property name="ObjectShortName">instruction_address[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/calibration_state">
<obj_property name="ElementShortName">calibration_state[319:0]</obj_property>
<obj_property name="ObjectShortName">calibration_state[319:0]</obj_property>
@ -93,26 +586,94 @@
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/o_phy_odelay_dqs_cntvaluein">
<obj_property name="ElementShortName">o_phy_odelay_dqs_cntvaluein[4:0]</obj_property>
<obj_property name="ObjectShortName">o_phy_odelay_dqs_cntvaluein[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/o_phy_idelay_dqs_cntvaluein">
<obj_property name="ElementShortName">o_phy_idelay_dqs_cntvaluein[4:0]</obj_property>
<obj_property name="ObjectShortName">o_phy_idelay_dqs_cntvaluein[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ddr3_clk">
<obj_property name="ElementShortName">i_ddr3_clk</obj_property>
<obj_property name="ObjectShortName">i_ddr3_clk</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dq">
<obj_property name="ElementShortName">io_ddr3_dq[15:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dq[15:0]</obj_property>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_clk_n">
<obj_property name="ElementShortName">o_ddr3_clk_n[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_clk_n[0:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_clk_p">
<obj_property name="ElementShortName">o_ddr3_clk_p[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_clk_p[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_clk_p[0]">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">[0]</obj_property>
<obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs">
<obj_property name="ElementShortName">io_ddr3_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs[1:0]</obj_property>
<obj_property name="ElementShortName">io_ddr3_dqs[7:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs[7:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[7]">
<obj_property name="ElementShortName">[7]</obj_property>
<obj_property name="ObjectShortName">[7]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[6]">
<obj_property name="ElementShortName">[6]</obj_property>
<obj_property name="ObjectShortName">[6]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[5]">
<obj_property name="ElementShortName">[5]</obj_property>
<obj_property name="ObjectShortName">[5]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[4]">
<obj_property name="ElementShortName">[4]</obj_property>
<obj_property name="ObjectShortName">[4]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[3]">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">[3]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[2]">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">[2]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[1]">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">[1]</obj_property>
<obj_property name="CustomSignalColor">#FFFF00</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[0]">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">[0]</obj_property>
<obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs_n">
<obj_property name="ElementShortName">io_ddr3_dqs_n[7:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs_n[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dq">
<obj_property name="ElementShortName">io_ddr3_dq[63:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dq[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/idelay_dqs">
<obj_property name="ElementShortName">idelay_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">idelay_dqs[1:0]</obj_property>
<obj_property name="ElementShortName">idelay_dqs[7:0]</obj_property>
<obj_property name="ObjectShortName">idelay_dqs[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/lane">
<obj_property name="ElementShortName">lane[0:0]</obj_property>
<obj_property name="ObjectShortName">lane[0:0]</obj_property>
<obj_property name="ElementShortName">lane[2:0]</obj_property>
<obj_property name="ObjectShortName">lane[2:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="CustomSignalColor">#FF00FF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/instruction_address">
<obj_property name="ElementShortName">instruction_address[4:0]</obj_property>
@ -169,12 +730,12 @@
<obj_property name="ObjectShortName">i_wb_addr[25:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_data">
<obj_property name="ElementShortName">i_wb_data[127:0]</obj_property>
<obj_property name="ObjectShortName">i_wb_data[127:0]</obj_property>
<obj_property name="ElementShortName">i_wb_data[511:0]</obj_property>
<obj_property name="ObjectShortName">i_wb_data[511:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_sel">
<obj_property name="ElementShortName">i_wb_sel[15:0]</obj_property>
<obj_property name="ObjectShortName">i_wb_sel[15:0]</obj_property>
<obj_property name="ElementShortName">i_wb_sel[63:0]</obj_property>
<obj_property name="ObjectShortName">i_wb_sel[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_wb_stall">
<obj_property name="ElementShortName">o_wb_stall</obj_property>
@ -185,20 +746,20 @@
<obj_property name="ObjectShortName">o_wb_ack</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_wb_data">
<obj_property name="ElementShortName">o_wb_data[127:0]</obj_property>
<obj_property name="ObjectShortName">o_wb_data[127:0]</obj_property>
<obj_property name="ElementShortName">o_wb_data[511:0]</obj_property>
<obj_property name="ObjectShortName">o_wb_data[511:0]</obj_property>
</wvobject>
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">DDR3 Interface</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cke">
<obj_property name="ElementShortName">o_ddr3_cke</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cke</obj_property>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cke">
<obj_property name="ElementShortName">o_ddr3_cke[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cke[0:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cs_n">
<obj_property name="ElementShortName">o_ddr3_cs_n</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cs_n</obj_property>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cs_n">
<obj_property name="ElementShortName">o_ddr3_cs_n[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cs_n[0:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_ras_n">
<obj_property name="ElementShortName">o_ddr3_ras_n</obj_property>
@ -221,23 +782,24 @@
<obj_property name="ObjectShortName">o_ddr3_ba_addr[2:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dq">
<obj_property name="ElementShortName">io_ddr3_dq[15:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dq[15:0]</obj_property>
<obj_property name="ElementShortName">io_ddr3_dq[63:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dq[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs">
<obj_property name="ElementShortName">io_ddr3_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs[1:0]</obj_property>
<obj_property name="ElementShortName">io_ddr3_dqs[7:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs[7:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs_n">
<obj_property name="ElementShortName">io_ddr3_dqs_n[1:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs_n[1:0]</obj_property>
<obj_property name="ElementShortName">io_ddr3_dqs_n[7:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs_n[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_dm">
<obj_property name="ElementShortName">o_ddr3_dm[1:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_dm[1:0]</obj_property>
<obj_property name="ElementShortName">o_ddr3_dm[7:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_dm[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_odt">
<obj_property name="ElementShortName">o_ddr3_odt</obj_property>
<obj_property name="ObjectShortName">o_ddr3_odt</obj_property>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_odt">
<obj_property name="ElementShortName">o_ddr3_odt[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_odt[0:0]</obj_property>
</wvobject>
</wave_config>

24
testbench/sim_defines.vh Normal file
View File

@ -0,0 +1,24 @@
// Define either TWO_LANES_x8 or EIGHT_LANES_x8
//`define TWO_LANES_x8
`define EIGHT_LANES_x8
`ifdef EIGHT_LANES_x8
`ifdef TWO_LANES_x8
ERROR: Display compilation error here
`endif
`define x8
`endif
`ifdef TWO_LANES_x8
`define x16
`endif
// Check if neither is defined
`ifndef EIGHT_LANES_x8
`ifndef TWO_LANES_x8
ERROR: Display compilation error here
`endif
`endif
`define den8192Mb
`define sg125

2
testbench/xsim/README.txt
View File

@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sat Jul 27 15:51:00 PST 2024
# Generated by export_simulation on Sun Jan 26 11:59:04 PST 2025
#
################################################################################

90
testbench/xsim/test_ecc_1.sh → testbench/xsim/ddr3_dimm_micron_sim.sh
View File

@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Jul 27 15:51:00 PST 2024
# Generated by Vivado on Sun Jan 26 11:32:37 PST 2025
# SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
#
# Tool Version Limit: 2022.04
@ -46,7 +46,7 @@ compile()
# RUN_STEP: <elaborate>
elaborate()
{
xelab -generic_top "ECC_ENABLE=1" --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
}
# RUN_STEP: <simulate>
@ -64,6 +64,7 @@ setup()
echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
exit 1
fi
copy_setup_file $2
;;
"-reset_run" )
reset_run
@ -74,6 +75,7 @@ setup()
# do not remove previous data
;;
* )
copy_setup_file $2
esac
# Add any setup/initialization commands here:-
@ -82,6 +84,90 @@ setup()
}
# Copy xsim.ini file
copy_setup_file()
{
file="xsim.ini"
lib_map_path="/tools/Xilinx/Vivado/2022.1/data/xsim"
if [[ ($1 != "") ]]; then
lib_map_path="$1"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
cp $src_file .
fi
# Map local design libraries to xsim.ini
map_local_libs
fi
}
# Map local design libraries
map_local_libs()
{
updated_mappings=()
local_mappings=()
# Local design libraries
local_libs=()
if [[ 0 == ${#local_libs[@]} ]]; then
return
fi
file="xsim.ini"
file_backup="xsim.ini.bak"
if [[ -e $file ]]; then
rm -f $file_backup
# Create a backup copy of the xsim.ini file
cp $file $file_backup
# Read libraries from backup file and search in local library collection
while read -r line
do
IN=$line
# Split mapping entry with '=' delimiter to fetch library name and mapping
read lib_name mapping <<<$(IFS="="; echo $IN)
# If local library found, then construct the local mapping and add to local mapping collection
if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
line="$lib_name=xsim.dir/$lib_name"
local_mappings+=("$lib_name")
fi
# Add to updated library mapping collection
updated_mappings+=("$line")
done < "$file_backup"
# Append local libraries not found originally from xsim.ini
for (( i=0; i<${#local_libs[*]}; i++ )); do
lib_name="${local_libs[i]}"
if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
line="$lib_name=xsim.dir/$lib_name"
updated_mappings+=("$line")
fi
done
# Write updated mappings in xsim.ini
rm -f $file
for (( i=0; i<${#updated_mappings[*]}; i++ )); do
lib_name="${updated_mappings[i]}"
echo $lib_name >> $file
done
else
for (( i=0; i<${#local_libs[*]}; i++ )); do
lib_name="${local_libs[i]}"
mapping="$lib_name=xsim.dir/$lib_name"
echo $mapping >> $file
done
fi
}
# Delete generated data from the previous run
reset_run()
{

16
testbench/xsim/file_info.txt
View File

@ -1,9 +1,7 @@
ddr3_controller.v,verilog,xil_defaultlib,../Desktop/UberDDR3/rtl/ddr3_controller.v,incdir="../"
ddr3_phy.v,verilog,xil_defaultlib,../Desktop/UberDDR3/rtl/ddr3_phy.v,incdir="../"
ddr3_top.v,verilog,xil_defaultlib,../Desktop/UberDDR3/rtl/ddr3_top.v,incdir="../"
ddr3.sv,systemverilog,xil_defaultlib,../Desktop/UberDDR3/testbench/ddr3.sv,incdir="../"
ddr3.sv,systemverilog,xil_defaultlib,../Desktop/UberDDR3/testbench/ddr3_module.sv,incdir="../"
ecc_dec.sv,systemverilog,xil_defaultlib,../Desktop/UberDDR3/rtl/ecc/ecc_dec.sv,incdir="../"
ecc_enc.sv,systemverilog,xil_defaultlib,../Desktop/UberDDR3/rtl/ecc/ecc_enc.sv,incdir="../"
ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,../Desktop/UberDDR3/testbench/ddr3_dimm_micron_sim.sv,incdir="../"
glbl.v,Verilog,xil_defaultlib,glbl.v
ddr3_controller.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_controller.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
ddr3_phy.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_phy.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
ddr3_top.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_top.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
ddr3.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
ddr3_module.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_module.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_dimm_micron_sim.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
glbl.v,Verilog,xil_defaultlib,/home/ajacobo/incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"/glbl.v

0
testbench/xsim/glbl.v Normal file → Executable file
View File

145
testbench/xsim/regression_test.sh Executable file
View File

@ -0,0 +1,145 @@
#!/bin/bash
#################################################################################################################
# Define the test configurations (CONTROLLER_CLK_PERIOD, DDR3_CLK_PERIOD, ODELAY_SUPPORTED, LANES_OPTION, ADD_BUS_DELAY, BIST_MODE)
TESTS=(
# with bus delay
"12_000 3_000 1 EIGHT_LANES 1 1" # DDR3-666
"10_000 2_500 1 EIGHT_LANES 1 1" # DDR3-800
"6_000 1_500 1 EIGHT_LANES 1 2" # DDR3-1333 write dm is weird (two happens at same time???)
"5_000 1_250 1 EIGHT_LANES 1 2" # DDR3-1600
# No bus delays
"12_000 3_000 1 EIGHT_LANES 0 2"
"10_000 2_500 1 EIGHT_LANES 0 2"
"6_000 1_500 1 EIGHT_LANES 0 1"
"5_000 1_250 1 EIGHT_LANES 0 1"
# x16
"12_000 3_000 1 TWO_LANES 1 1"
"10_000 2_500 1 TWO_LANES 1 1"
"6_000 1_500 1 TWO_LANES 1 2"
"5_000 1_250 1 TWO_LANES 1 2"
# no odelay
"12_000 3_000 0 TWO_LANES 0 2"
"10_000 2_500 0 TWO_LANES 0 2"
"6_000 1_500 0 TWO_LANES 0 1"
"5_000 1_250 0 TWO_LANES 0 1"
)
#################################################################################################################
# Define the files to modify
FILENAME="../ddr3_dimm_micron_sim.sv"
DEFINES_FILE="../sim_defines.vh"
PARAMETERS_FILE="../8192Mb_ddr3_parameters.vh"
# Check if the main file exists
if [[ ! -f "$FILENAME" ]]; then
echo "Error: File '$FILENAME' does not exist."
exit 1
fi
# Check if the defines file exists
if [[ ! -f "$DEFINES_FILE" ]]; then
echo "Error: File '$DEFINES_FILE' does not exist."
exit 1
fi
# Check if the parameters file exists
if [[ ! -f "$PARAMETERS_FILE" ]]; then
echo "Error: File '$PARAMETERS_FILE' does not exist."
exit 1
fi
#################################################################################################################
# Loop over each test configuration
index=1
for TEST in "${TESTS[@]}"; do
# Parse the test configuration into individual variables
read -r CONTROLLER_CLK_PERIOD DDR3_CLK_PERIOD ODELAY_SUPPORTED LANES_OPTION ADD_BUS_DELAY BIST_MODE <<< "$TEST"
# Record the start time
start_time=$(date +%s)
start_time_am_pm=$(date +"%I:%M %p") # Time in AM-PM format
# Print the current test configuration with the start time
echo "$index. Running test with CONTROLLER_CLK_PERIOD=$CONTROLLER_CLK_PERIOD, DDR3_CLK_PERIOD=$DDR3_CLK_PERIOD, ODELAY_SUPPORTED=$ODELAY_SUPPORTED, LANES_OPTION=$LANES_OPTION, ADD_BUS_DELAY=$ADD_BUS_DELAY, BIST_MODE=$BIST_MODE"
echo " Test started at: $start_time_am_pm"
# Use sed to perform the replacements in the main file
sed -i \
-e "s/CONTROLLER_CLK_PERIOD = [0-9_]\+/CONTROLLER_CLK_PERIOD = $CONTROLLER_CLK_PERIOD/" \
-e "s/DDR3_CLK_PERIOD = [0-9_]\+/DDR3_CLK_PERIOD = $DDR3_CLK_PERIOD/" \
-e "s/ODELAY_SUPPORTED = [01]/ODELAY_SUPPORTED = $ODELAY_SUPPORTED/" \
-e "s/BIST_MODE = [0-2]/BIST_MODE = $BIST_MODE/" \
"$FILENAME"
# Modify the sim_defines.vh file based on LANES_OPTION
if [[ "$LANES_OPTION" == "TWO_LANES" ]]; then
sed -i \
-e "s|^//\(\`define TWO_LANES_x8\)|\1|" \
-e "s|^\(\`define EIGHT_LANES_x8\)|//\1|" \
"$DEFINES_FILE"
elif [[ "$LANES_OPTION" == "EIGHT_LANES" ]]; then
sed -i \
-e "s|^//\(\`define EIGHT_LANES_x8\)|\1|" \
-e "s|^\(\`define TWO_LANES_x8\)|//\1|" \
"$DEFINES_FILE"
else
echo "Error: Invalid LANES_OPTION value. Choose either 'TWO_LANES' or 'EIGHT_LANES'."
exit 1
fi
# Modify the parameters file based on ADD_BUS_DELAY
if [[ "$ADD_BUS_DELAY" == "1" ]]; then
sed -i \
-e "s|BUS_DELAY = [0-9]\+|BUS_DELAY = 100|" \
-e "s|FLY_BY_DELAY_LANE_0 = [0-9]\+|FLY_BY_DELAY_LANE_0 = 0|" \
-e "s|FLY_BY_DELAY_LANE_1 = [0-9]\+|FLY_BY_DELAY_LANE_1 = 50|" \
-e "s|FLY_BY_DELAY_LANE_2 = [0-9]\+|FLY_BY_DELAY_LANE_2 = 100|" \
-e "s|FLY_BY_DELAY_LANE_3 = [0-9]\+|FLY_BY_DELAY_LANE_3 = 150|" \
-e "s|FLY_BY_DELAY_LANE_4 = [0-9]\+|FLY_BY_DELAY_LANE_4 = 200|" \
-e "s|FLY_BY_DELAY_LANE_5 = [0-9]\+|FLY_BY_DELAY_LANE_5 = 250|" \
-e "s|FLY_BY_DELAY_LANE_6 = [0-9]\+|FLY_BY_DELAY_LANE_6 = 300|" \
-e "s|FLY_BY_DELAY_LANE_7 = [0-9]\+|FLY_BY_DELAY_LANE_7 = 350|" \
"$PARAMETERS_FILE"
else
sed -i \
-e "s|BUS_DELAY = [0-9]\+|BUS_DELAY = 0|" \
-e "s|FLY_BY_DELAY_LANE_0 = [0-9]\+|FLY_BY_DELAY_LANE_0 = 0|" \
-e "s|FLY_BY_DELAY_LANE_1 = [0-9]\+|FLY_BY_DELAY_LANE_1 = 0|" \
-e "s|FLY_BY_DELAY_LANE_2 = [0-9]\+|FLY_BY_DELAY_LANE_2 = 0|" \
-e "s|FLY_BY_DELAY_LANE_3 = [0-9]\+|FLY_BY_DELAY_LANE_3 = 0|" \
-e "s|FLY_BY_DELAY_LANE_4 = [0-9]\+|FLY_BY_DELAY_LANE_4 = 0|" \
-e "s|FLY_BY_DELAY_LANE_5 = [0-9]\+|FLY_BY_DELAY_LANE_5 = 0|" \
-e "s|FLY_BY_DELAY_LANE_6 = [0-9]\+|FLY_BY_DELAY_LANE_6 = 0|" \
-e "s|FLY_BY_DELAY_LANE_7 = [0-9]\+|FLY_BY_DELAY_LANE_7 = 0|" \
"$PARAMETERS_FILE"
fi
# Run the simulation script with the respective log file
LOG_FILE="./test_${CONTROLLER_CLK_PERIOD}_ddr3_${DDR3_CLK_PERIOD}_odelay_${ODELAY_SUPPORTED}_lanes_${LANES_OPTION,,}_bus_delay_${ADD_BUS_DELAY}_bist_${BIST_MODE}.log"
# ./ddr3_dimm_micron_sim.sh >> "$LOG_FILE"
# add timeout if simulation takes too long
timeout 3h ./ddr3_dimm_micron_sim.sh >> "$LOG_FILE" 2>&1
EXIT_CODE=$? # Capture exit code immediately
if [ $EXIT_CODE -eq 124 ]; then
echo " Error: Simulation timed out after 1 hour!" | tee -a "$LOG_FILE"
fi
# Record the end time and calculate the duration in minutes
end_time=$(date +%s)
duration=$((end_time - start_time))
minutes=$((duration / 60))
seconds=$((duration % 60))
# Report the results
echo " Test completed. Duration: ${minutes}m ${seconds}s. Results saved to '$LOG_FILE'."
echo ""
# Increment the index
((index++))
done
#################################################################################################################

26
testbench/xsim/run_batch.sh
View File

@ -1,26 +0,0 @@
rm -rf *backup*
rm -rf *test_ecc*.log*
echo -e "\e[32mRun test: test_ecc_0 \e[0m"
./test_ecc_0.sh -reset_run
./test_ecc_0.sh >> ./test_ecc_0.log
./test_ecc_0.sh -reset_run
echo ""
echo ""
echo -e "\e[32mRun test: test_ecc_1 \e[0m"
./test_ecc_1.sh >> ./test_ecc_1.log
./test_ecc_1.sh -reset_run
echo ""
echo ""
echo -e "\e[32mRun test: test_ecc_2 \e[0m"
./test_ecc_2.sh >> ./test_ecc_2.log
./test_ecc_2.sh -reset_run
echo ""
echo ""
echo -e "\e[32mRun test: test_ecc_3 \e[0m"
./test_ecc_3.sh >> ./test_ecc_3.log
./test_ecc_3.sh -reset_run
rm -rf *backup*

11319
testbench/xsim/test_10_000_ddr3_2_500_odelay_0_lanes_two_lanes_bus_delay_0.log Normal file
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File diff suppressed because it is too large Load Diff

12438
testbench/xsim/test_ecc_0.log → testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_eight_lanes_bus_delay_0.log
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File diff suppressed because it is too large Load Diff

22058
testbench/xsim/test_ecc_2.log → testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_eight_lanes_bus_delay_1.log
View File

File diff suppressed because it is too large Load Diff

12751
testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_two_lanes_bus_delay_0.log Normal file
View File

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12015
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testbench/xsim/test_ecc_0.sh
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@ -1,129 +0,0 @@
#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2022.1 (64-bit)
#
# Filename : ddr3_dimm_micron_sim.sh
# Simulator : Xilinx Vivado Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Jul 27 15:51:00 PST 2024
# SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
#
# Tool Version Limit: 2022.04
#
# usage: ddr3_dimm_micron_sim.sh [-help]
# usage: ddr3_dimm_micron_sim.sh [-lib_map_path]
# usage: ddr3_dimm_micron_sim.sh [-noclean_files]
# usage: ddr3_dimm_micron_sim.sh [-reset_run]
#
#*********************************************************************************************************
# Set xvlog options
xvlog_opts="--incr --relax -L uvm"
# Script info
echo -e "ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2022.1 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
elaborate
simulate
}
# RUN_STEP: <compile>
compile()
{
xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
}
# RUN_STEP: <elaborate>
elaborate()
{
xelab -generic_top "ECC_ENABLE=0" --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
}
# RUN_STEP: <simulate>
simulate()
{
xsim ddr3_dimm_micron_sim -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -tclbatch cmd.tcl -log simulate.log
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
exit 1
fi
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
esac
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ddr3_dimm_micron_sim.wdb xsim.dir)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ddr3_dimm_micron_sim.sh [-help]\n\
Usage: ddr3_dimm_micron_sim.sh [-lib_map_path]\n\
Usage: ddr3_dimm_micron_sim.sh [-reset_run]\n\
Usage: ddr3_dimm_micron_sim.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2

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testbench/xsim/test_ecc_2.sh
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#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2022.1 (64-bit)
#
# Filename : ddr3_dimm_micron_sim.sh
# Simulator : Xilinx Vivado Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Jul 27 15:51:00 PST 2024
# SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
#
# Tool Version Limit: 2022.04
#
# usage: ddr3_dimm_micron_sim.sh [-help]
# usage: ddr3_dimm_micron_sim.sh [-lib_map_path]
# usage: ddr3_dimm_micron_sim.sh [-noclean_files]
# usage: ddr3_dimm_micron_sim.sh [-reset_run]
#
#*********************************************************************************************************
# Set xvlog options
xvlog_opts="--incr --relax -L uvm"
# Script info
echo -e "ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2022.1 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
elaborate
simulate
}
# RUN_STEP: <compile>
compile()
{
xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
}
# RUN_STEP: <elaborate>
elaborate()
{
xelab -generic_top "ECC_ENABLE=2" --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
}
# RUN_STEP: <simulate>
simulate()
{
xsim ddr3_dimm_micron_sim -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -tclbatch cmd.tcl -log simulate.log
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
exit 1
fi
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
esac
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ddr3_dimm_micron_sim.wdb xsim.dir)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ddr3_dimm_micron_sim.sh [-help]\n\
Usage: ddr3_dimm_micron_sim.sh [-lib_map_path]\n\
Usage: ddr3_dimm_micron_sim.sh [-reset_run]\n\
Usage: ddr3_dimm_micron_sim.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2

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testbench/xsim/test_ecc_3.sh
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@ -1,129 +0,0 @@
#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2022.1 (64-bit)
#
# Filename : ddr3_dimm_micron_sim.sh
# Simulator : Xilinx Vivado Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Jul 27 15:51:00 PST 2024
# SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
#
# Tool Version Limit: 2022.04
#
# usage: ddr3_dimm_micron_sim.sh [-help]
# usage: ddr3_dimm_micron_sim.sh [-lib_map_path]
# usage: ddr3_dimm_micron_sim.sh [-noclean_files]
# usage: ddr3_dimm_micron_sim.sh [-reset_run]
#
#*********************************************************************************************************
# Set xvlog options
xvlog_opts="--incr --relax -L uvm"
# Script info
echo -e "ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2022.1 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
elaborate
simulate
}
# RUN_STEP: <compile>
compile()
{
xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
}
# RUN_STEP: <elaborate>
elaborate()
{
xelab -generic_top "ECC_ENABLE=3" --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
}
# RUN_STEP: <simulate>
simulate()
{
xsim ddr3_dimm_micron_sim -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -tclbatch cmd.tcl -log simulate.log
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
exit 1
fi
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
esac
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ddr3_dimm_micron_sim.wdb xsim.dir)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ddr3_dimm_micron_sim.sh [-help]\n\
Usage: ddr3_dimm_micron_sim.sh [-lib_map_path]\n\
Usage: ddr3_dimm_micron_sim.sh [-reset_run]\n\
Usage: ddr3_dimm_micron_sim.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2

20
testbench/xsim/vlog.prj
View File

@ -1,15 +1,13 @@
verilog xil_defaultlib --include "../" \
"../../rtl/ddr3_controller.v" \
"../../rtl/ddr3_phy.v" \
"../../rtl/ddr3_top.v" \
verilog xil_defaultlib --include "/home/ajacobo/Desktop/UberDDR3/testbench" --include "/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" \
"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_controller.v" \
"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_phy.v" \
"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_top.v" \
sv xil_defaultlib --include "../" \
"../ddr3.sv" \
"../../rtl/ecc/ecc_dec.sv" \
"../../rtl/ecc/ecc_enc.sv" \
"../ddr3_dimm_micron_sim.sv" \
"../ddr3_module.sv" \
sv xil_defaultlib --include "/home/ajacobo/Desktop/UberDDR3/testbench" --include "/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" \
"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3.sv" \
"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_module.sv" \
"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_dimm_micron_sim.sv" \
verilog xil_defaultlib "glbl.v"
verilog xil_defaultlib "/home/ajacobo/Desktop/UberDDR3/testbench/xsim/glbl.v"
nosort

481
testbench/xsim/xsim.ini Normal file → Executable file
View File

@ -1 +1,480 @@
xil_defaultlib=xsim.dir/xil_defaultlib
std=$RDI_DATADIR/xsim/vhdl/std
ieee=$RDI_DATADIR/xsim/vhdl/ieee
ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
vl=$RDI_DATADIR/xsim/vhdl/vl
synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
uvm=$RDI_DATADIR/xsim/system_verilog/uvm
secureip=$RDI_DATADIR/xsim/verilog/secureip
unisim=$RDI_DATADIR/xsim/vhdl/unisim
unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
unifast=$RDI_DATADIR/xsim/vhdl/unifast
unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4
emb_mem_gen_v1_0_6=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_6
common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
ptp_1588_timer_syncer_v2_0_3=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_3
tcc_decoder_3gppmm_v2_0_23=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_23
v_warp_filter_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_0_2
fc32_rs_fec_v1_0_21=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_21
vid_phy_controller_v2_1_13=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_13
aurora_8b10b_versal_v1_0_1=$RDI_DATADIR/xsim/ip/aurora_8b10b_versal_v1_0_1
axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16
axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0
noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
v_smpte_uhdsdi_v1_0_9=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_9
axi_firewall_v1_2_1=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_1
xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4
axi_mm2s_mapper_v1_1_25=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_25
v_tpg_v8_1_5=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_5
ll_compress_v1_1_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_1_0
cpm4_v1_0_7=$RDI_DATADIR/xsim/ip/cpm4_v1_0_7
axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0
convolution_v9_0_16=$RDI_DATADIR/xsim/ip/convolution_v9_0_16
tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16
axi_timebase_wdt_v3_0_18=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_18
xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
axi_epc_v2_0_29=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_29
dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16
axi_interconnect_v1_7_20=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_20
gmii_to_rgmii_v4_1_4=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_4
clk_gen_sim_v1_0_2=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_2
ieee802d3_50g_rs_fec_v2_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_11
axi_datamover_v5_1_28=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_28
zynq_ultra_ps_e_vip_v1_0_12=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_12
xscl=$RDI_DATADIR/xsim/ip/xscl
bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0
vby1hs_v1_0_2=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_2
tmr_manager_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_9
polar_v1_1_0=$RDI_DATADIR/xsim/ip/polar_v1_1_0
vitis_net_p4_v1_1_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v1_1_0
timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4
mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11
fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6
vid_phy_controller_v2_2_13=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_13
noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
xpm_cdc_gen_v1_0_1=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_1
ethernet_1_10_25g_v2_7_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_5
axi_register_slice_v2_1_26=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_26
hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0
v_smpte_uhdsdi_rx_v1_0_1=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_1
axi_ethernet_buffer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_24
axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
zynq_ultra_ps_e_v3_3_7=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_7
axi_sg_v4_1_15=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_15
xdma_v4_1_17=$RDI_DATADIR/xsim/ip/xdma_v4_1_17
axi_uartlite_v2_0_30=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_30
bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0
shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0
noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7
uram_rd_back_v1_0_2=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_2
amm_axi_bridge_v1_0_12=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_12
rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0
remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10
noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
ieee802d3_50g_rs_fec_v1_0_19=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_19
pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11
axis_dwidth_converter_v1_1_25=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_25
ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
v_vcresampler_v1_1_5=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_5
xdfe_resampler_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_4
v_axi4s_remap_v1_0_19=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_19
xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4
axi_timer_v2_0_28=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_28
xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6
xdfe_equalizer_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_4
gtwizard_ultrascale_v1_6_13=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_13
axis_clock_converter_v1_1_27=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_27
tsn_endpoint_ethernet_mac_block_v1_0_11=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_11
axis_vio_v1_0_6=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_6
dfx_controller_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_3
axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0
ahblite_axi_bridge_v3_0_21=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_21
v_smpte_uhdsdi_tx_v1_0_1=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_1
viterbi_v9_1_13=$RDI_DATADIR/xsim/ip/viterbi_v9_1_13
axi4stream_vip_v1_1_12=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_12
etrnic_v1_1_5=$RDI_DATADIR/xsim/ip/etrnic_v1_1_5
adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
axi_data_fifo_v2_1_25=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_25
axi_dwidth_converter_v2_1_26=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_26
cordic_v6_0_18=$RDI_DATADIR/xsim/ip/cordic_v6_0_18
axi_lmb_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_0
g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18
c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14
trace_s2mm_v1_2_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_2_0
axis_broadcaster_v1_1_25=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_25
axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0
v_tc_v6_2_4=$RDI_DATADIR/xsim/ip/v_tc_v6_2_4
icap_arb_v1_0_1=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_1
dsp_macro_v1_0_2=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_2
v_dp_axi4s_vid_out_v1_0_4=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_4
v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9
qdriv_pl_v1_0_7=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_7
proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13
v_axi4s_remap_v1_1_5=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_5
pr_decoupler_v1_0_10=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_10
fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6
mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0
axi_hwicap_v3_0_30=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_30
hdmi_gt_controller_v1_0_7=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_7
axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0
iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6
ta_dma_v1_0_10=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_10
xdfe_common_v1_0_0=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_0
canfd_v3_0_5=$RDI_DATADIR/xsim/ip/canfd_v3_0_5
dcmac_v2_0_0=$RDI_DATADIR/xsim/ip/dcmac_v2_0_0
axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
axi_msg_v1_0_8=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_8
axi_vdma_v6_3_14=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_14
v_vid_in_axi4s_v5_0_1=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_1
debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
lmb_bram_if_cntlr_v4_0_21=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_21
axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib
v_scenechange_v1_1_4=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_4
in_system_ibert_v1_0_16=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_16
tmr_sem_v1_0_22=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_22
pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12
axi_iic_v2_1_2=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_2
xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
g709_fec_v2_4_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_5
high_speed_selectio_wiz_v3_6_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_3
xtlm=$RDI_DATADIR/xsim/ip/xtlm
v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1
xdfe_fft_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_4
axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
v_warp_filter_v1_1_0=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_0
c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6
axi_fifo_mm_s_v4_2_8=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_8
util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2
usxgmii_v1_2_7=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_7
blk_mem_gen_v8_4_5=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_5
ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7
axi_traffic_gen_v3_0_12=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_12
dfx_decoupler_v1_0_4=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_4
util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4
emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5
lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0
rama_v1_1_12_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_12_lib
hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3
xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6
xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6
ieee802d3_400g_rs_fec_v2_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v2_0_7
lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2
v_hdmi_phy1_v1_0_6=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_6
axis_data_fifo_v2_0_8=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_8
ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
picxo=$RDI_DATADIR/xsim/ip/picxo
axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6
v_hdmi_tx1_v1_0_3=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_3
axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
axi_sideband_util_v1_0_10=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_10
v_demosaic_v1_1_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_5
lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2
cmac_v2_6_7=$RDI_DATADIR/xsim/ip/cmac_v2_6_7
fifo_generator_v13_2_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_7
pc_cfr_v7_0_1=$RDI_DATADIR/xsim/ip/pc_cfr_v7_0_1
gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
video_frame_crc_v1_0_4=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_4
axi_usb2_device_v5_0_27=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_27
shell_utils_addr_remap_v1_0_5=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_5
xbip_multadd_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_17
axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0
axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
axi_mcdma_v1_1_7=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_7
xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
pc_cfr_v6_4_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_2
lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
i2s_transmitter_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_5
xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2
xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6
noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0
c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6
processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
rld3_pl_v1_0_9=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_9
versal_cips_ps_vip_v1_0_4=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_4
multi_channel_25g_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_18
v_letterbox_v1_1_5=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_5
axis_interconnect_v1_1_20=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_20
axi_uart16550_v2_0_28=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_28
roe_framer_v3_0_3=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_3
ddr4_pl_v1_0_8=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_8
sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2
i2s_receiver_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_5
axi_crossbar_v2_1_27=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_27
axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0
compact_gt_v1_0_12=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_12
v_mix_v5_2_3=$RDI_DATADIR/xsim/ip/v_mix_v5_2_3
div_gen_v5_1_19=$RDI_DATADIR/xsim/ip/div_gen_v5_1_19
interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4
zynq_ultra_ps_e_v3_4_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_4_0
hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3
pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0
mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4
axi_mmu_v2_1_24=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_24
can_v5_0_29=$RDI_DATADIR/xsim/ip/can_v5_0_29
v_tpg_v8_2_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_1
sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
v_csc_v1_1_5=$RDI_DATADIR/xsim/ip/v_csc_v1_1_5
v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9
v_warp_init_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_init_v1_0_2
axis_register_slice_v1_1_26=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_26
c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14
trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
fast_adapter_v1_0_3=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_3
system_cache_v5_0_8=$RDI_DATADIR/xsim/ip/system_cache_v5_0_8
v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0
ieee802d3_rs_fec_v2_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_15
v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0
perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8
sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8
ilknf_v1_1_0=$RDI_DATADIR/xsim/ip/ilknf_v1_1_0
rs_decoder_v9_0_18=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_18
axi_chip2chip_v5_0_15=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_15
qdma_v4_0_11=$RDI_DATADIR/xsim/ip/qdma_v4_0_11
ldpc_v2_0_10=$RDI_DATADIR/xsim/ip/ldpc_v2_0_10
axi_c2c_v1_0_3=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_3
av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1
pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1
xxv_ethernet_v4_1_0=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_0
vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0
rs_toolbox_v9_0_9=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_9
axis_data_fifo_v1_1_27=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_27
audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0
c_counter_binary_v12_0_15=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_15
axi_dma_v7_1_27=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_27
emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0
dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1
axi_gpio_v2_0_28=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_28
v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13
axi_emc_v3_0_26=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_26
dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0
axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0
microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6
mdm_v3_2_23=$RDI_DATADIR/xsim/ip/mdm_v3_2_23
mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7
noc_nmu_phydir_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_phydir_v1_0_0
v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0
axi_vfifo_ctrl_v2_0_28=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_28
stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0
axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0
cic_compiler_v4_0_16=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_16
mailbox_v2_1_15=$RDI_DATADIR/xsim/ip/mailbox_v2_1_15
stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
ieee802d3_200g_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_5
xdfe_cc_filter_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_0_4
advanced_io_wizard_v1_0_7=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_7
nvmeha_v1_0_7=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_7
axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0
smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
mrmac_v1_6_0=$RDI_DATADIR/xsim/ip/mrmac_v1_6_0
jesd204c_v4_2_8=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_8
axi_firewall_v1_1_5=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_5
an_lt_v1_0_6=$RDI_DATADIR/xsim/ip/an_lt_v1_0_6
lmb_v10_v3_0_12=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_12
ats_switch_v1_0_5=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_5
switch_core_top_v1_0_11=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_11
axi_tft_v2_0_25=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_25
xdfe_cc_mixer_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v1_0_4
hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
floating_point_v7_0_20=$RDI_DATADIR/xsim/ip/floating_point_v7_0_20
microblaze_v11_0_9=$RDI_DATADIR/xsim/ip/microblaze_v11_0_9
tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6
v_hcresampler_v1_1_5=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_5
interlaken_v2_4_11=$RDI_DATADIR/xsim/ip/interlaken_v2_4_11
sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6
fir_compiler_v7_2_18=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_18
spdif_v2_0_26=$RDI_DATADIR/xsim/ip/spdif_v2_0_26
hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0
v_vid_gt_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_5
noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
axi_ahblite_bridge_v3_0_23=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_23
v_multi_scaler_v1_2_3=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_3
axis_protocol_checker_v2_0_10=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_10
mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0
ten_gig_eth_mac_v15_1_10=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_10
ptp_1588_timer_syncer_v1_0_2=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_2
vitis_deadlock_detector_v1_0_1=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_1
lib_fifo_v1_0_16=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_16
util_vector_logic_v2_0_2=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_2
floating_point_v7_1_14=$RDI_DATADIR/xsim/ip/floating_point_v7_1_14
c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6
dds_compiler_v6_0_22=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_22
srio_gen2_v4_1_14=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_14
axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0
vfb_v1_0_20=$RDI_DATADIR/xsim/ip/vfb_v1_0_20
v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0
noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0
xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0
advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0
xpm=$RDI_DATADIR/xsim/ip/xpm
hdmi_acr_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_0
quadsgmii_v3_5_8=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_8
xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6
axi_vip_v1_1_12=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_12
av_pat_gen_v2_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_0
axi_protocol_checker_v2_0_12=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_12
sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
axi4svideo_bridge_v1_0_14=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_14
tsn_temac_v1_0_7=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_7
dfx_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_1
axi_bram_ctrl_v4_1_6=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_6
jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
dprx_fec_8b10b_v1_0_1=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_1
ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0
ll_compress_v2_1_0=$RDI_DATADIR/xsim/ip/ll_compress_v2_1_0
ieee802d3_25g_rs_fec_v1_0_23=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_23
hbm2e_pl_v1_0_0=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_0
flexo_100g_rs_fec_v1_0_21=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_21
cpm5_v1_0_7=$RDI_DATADIR/xsim/ip/cpm5_v1_0_7
lte_fft_v2_0_22=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_22
v_frmbuf_rd_v2_4_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_0
xfft_v9_1_8=$RDI_DATADIR/xsim/ip/xfft_v9_1_8
axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
lib_bmg_v1_0_14=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_14
axi_quad_spi_v3_2_25=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_25
pcie_qdma_mailbox_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_0
cpri_v8_11_12=$RDI_DATADIR/xsim/ip/cpri_v8_11_12
axi_apb_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_17
tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4
jesd204_v7_2_15=$RDI_DATADIR/xsim/ip/jesd204_v7_2_15
v_hscaler_v1_1_5=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_5
axis_switch_v1_1_26=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_26
accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0
noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
tri_mode_ethernet_mac_v9_0_22=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_22
generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0
v_warp_init_v1_1_0=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_0
rs_encoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_17
v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9
xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6
nvme_tc_v3_0_1=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_1
v_frmbuf_wr_v2_2_5=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_5
sd_fec_v1_1_9=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_9
cmac_usplus_v3_1_9=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_9
ll_compress_v2_0_1=$RDI_DATADIR/xsim/ip/ll_compress_v2_0_1
g709_rs_encoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_8
processing_system7_vip_v1_0_14=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_14
c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6
axi_amm_bridge_v1_0_16=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_16
lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2
audio_formatter_v1_0_8=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_8
xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6
bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0
audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2
videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5
lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
pc_cfr_v7_1_0=$RDI_DATADIR/xsim/ip/pc_cfr_v7_1_0
v_vscaler_v1_1_5=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_5
rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4
v_frmbuf_rd_v2_3_1=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_3_1
v_axi4s_vid_out_v4_0_14=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_14
v_tpg_v8_0_9=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_9
v_frmbuf_wr_v2_4_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_4_0
fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1
fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4
axi_protocol_converter_v2_1_26=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_26
hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1
axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0
ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13
axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0
mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6
xdfe_nlf_v1_0_0=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_0_0
soft_ecc_proxy_v1_0_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_1
axi_pcie_v2_9_7=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_7
c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14
xdfe_nr_prach_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v1_0_4
axi_clock_converter_v2_1_25=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_25
gtwizard_ultrascale_v1_7_13=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_13
common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
displayport_v8_1_5=$RDI_DATADIR/xsim/ip/displayport_v8_1_5
blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6
ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0
displayport_v9_0_5=$RDI_DATADIR/xsim/ip/displayport_v9_0_5
sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13
axi_perf_mon_v5_0_28=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_28
uhdsdi_gt_v2_0_8=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_8
oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2
sem_ultra_v3_1_23=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_23
v_mix_v5_1_5=$RDI_DATADIR/xsim/ip/v_mix_v5_1_5
ten_gig_eth_pcs_pma_v6_0_22=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_22
xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
gig_ethernet_pcs_pma_v16_2_8=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_8
ieee802d3_clause74_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_13
noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
v_frmbuf_rd_v2_2_5=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_5
l_ethernet_v3_3_0=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_0
rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0
xfft_v7_2_13=$RDI_DATADIR/xsim/ip/xfft_v7_2_13
axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0
v_frmbuf_wr_v2_3_1=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_3_1
axi_cdma_v4_1_26=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_26
emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2
cmpy_v6_0_21=$RDI_DATADIR/xsim/ip/cmpy_v6_0_21
cam_v2_3_0=$RDI_DATADIR/xsim/ip/cam_v2_3_0
g975_efec_i4_v1_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_18
dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
tmr_voter_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_4
mpegtsmux_v1_1_4=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_4
xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7
lte_fft_v2_1_6=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_6
axi_intc_v4_1_17=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_17
ernic_v3_1_2=$RDI_DATADIR/xsim/ip/ernic_v3_1_2
c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6
tcc_encoder_3gpp_v5_0_18=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_18
axi_pcie3_v3_0_22=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_22
g709_rs_decoder_v2_2_10=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_10
axis_combiner_v1_1_24=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_24
clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2
aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
v_uhdsdi_audio_v2_0_6=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_6
remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
polar_v1_0_10=$RDI_DATADIR/xsim/ip/polar_v1_0_10
v_hdmi_rx1_v1_0_3=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_3
v_gamma_lut_v1_1_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_5
sid_v8_0_17=$RDI_DATADIR/xsim/ip/sid_v8_0_17
axis_subset_converter_v1_1_26=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_26
axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14
oran_radio_if_v2_2_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v2_2_0
xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10
axi_hbicap_v1_0_4=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_4
sim_clk_gen_v1_0_3=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_3
sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13
versal_cips_v3_2_0=$RDI_DATADIR/xsim/ip/versal_cips_v3_2_0
mipi_dphy_v4_3_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_4
mult_gen_v12_0_18=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_18
xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2
iomodule_v3_1_8=$RDI_DATADIR/xsim/ip/iomodule_v3_1_8
util_ff_v1_0_0=$RDI_DATADIR/xsim/ip/util_ff_v1_0_0
mem_tg_v1_0_8=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_8
ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0
sim_trig_v1_0_7=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_7
tmr_comparator_v1_0_5=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_5
pcie_dma_versal_v2_0_9=$RDI_DATADIR/xsim/ip/pcie_dma_versal_v2_0_9
axi_ethernetlite_v3_0_25=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_25
axi_memory_init_v1_0_7=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_7
v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0
dft_v4_2_3=$RDI_DATADIR/xsim/ip/dft_v4_2_3
qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0

54
vivado_custom_ip/component.xml
View File

@ -561,7 +561,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>1dea7b87</spirit:value>
<spirit:value>407441e6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@ -577,7 +577,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>1dea7b87</spirit:value>
<spirit:value>407441e6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@ -591,7 +591,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>ce7b9cf6</spirit:value>
<spirit:value>5c3337af</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@ -1596,7 +1596,7 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.i_user_self_refresh" xilinx:dependency="$SELF_REFRESH = 0">true</xilinx:isEnabled>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.i_user_self_refresh" xilinx:dependency="$SELF_REFRESH = 0">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
@ -1668,11 +1668,6 @@
<spirit:displayName>Wb Error</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WB_ERROR">0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>SKIP_INTERNAL_TEST</spirit:name>
<spirit:displayName>Skip Internal Test</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SKIP_INTERNAL_TEST">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>ECC_ENABLE</spirit:name>
<spirit:displayName>Ecc Enable</spirit:displayName>
@ -1681,7 +1676,7 @@
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>SELF_REFRESH</spirit:name>
<spirit:displayName>Self-Refresh</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SELF_REFRESH">0</spirit:value>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SELF_REFRESH" spirit:bitStringLength="2">&quot;00&quot;</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>DIC</spirit:name>
@ -1743,6 +1738,11 @@
<spirit:displayName>Axi Data Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.AXI_DATA_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.wb_data_bits&apos;))">128</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>BIST_MODE</spirit:name>
<spirit:displayName>Bist Mode</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BIST_MODE">0</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
@ -1751,6 +1751,12 @@
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_3f983004</spirit:name>
<spirit:enumeration spirit:text="0 (No BIST)">0</spirit:enumeration>
<spirit:enumeration spirit:text="1 (Run through all address space once)">1</spirit:enumeration>
<spirit:enumeration spirit:text="2 (Run through all address space for every test)">2</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_933dc0fc</spirit:name>
<spirit:enumeration spirit:text="0 (ECC DIsabled)">0</spirit:enumeration>
@ -1820,7 +1826,7 @@
<spirit:file>
<spirit:name>../rtl/axi/ddr3_top_axi.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_f4e2d855</spirit:userFileType>
<spirit:userFileType>CHECKSUM_f9ca4d9d</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@ -1883,7 +1889,7 @@
<spirit:file>
<spirit:name>xgui/uberddr3_axi_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_ce7b9cf6</spirit:userFileType>
<spirit:userFileType>CHECKSUM_5c3337af</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
@ -1969,11 +1975,6 @@
<spirit:displayName>Wb Error</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WB_ERROR">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>SKIP_INTERNAL_TEST</spirit:name>
<spirit:displayName>Skip Internal Test</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SKIP_INTERNAL_TEST">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ECC_ENABLE</spirit:name>
<spirit:displayName>ECC Enable</spirit:displayName>
@ -2102,7 +2103,12 @@
<spirit:parameter>
<spirit:name>SELF_REFRESH</spirit:name>
<spirit:displayName>Self-Refresh</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SELF_REFRESH" spirit:choiceRef="choice_pairs_96a879b9">0</spirit:value>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SELF_REFRESH" spirit:choiceRef="choice_pairs_96a879b9" spirit:bitStringLength="2">&quot;00&quot;</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>BIST_MODE</spirit:name>
<spirit:displayName>BIST Mode</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BIST_MODE" spirit:choiceRef="choice_pairs_3f983004">0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
@ -2137,8 +2143,8 @@
<xilinx:displayName>uberddr3_axi_v1_0</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:vendorURL>https://github.com/AngeloJacobo/UberDDR3</xilinx:vendorURL>
<xilinx:coreRevision>11</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-11-24T08:00:34Z</xilinx:coreCreationDateTime>
<xilinx:coreRevision>12</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-02-16T03:52:36Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags>
@ -2147,10 +2153,10 @@
<xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6c0c2bc0"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="cd65c31e"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ba5aba03"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="abd96048"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="86f21185"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="5574e240"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="de319895"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="4c100aa3"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a0261d6d"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="ab77e269"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>

32
vivado_custom_ip/xgui/uberddr3_axi_v1_0.tcl
View File

@ -23,8 +23,8 @@ proc init_gui { IPINST } {
set_property tooltip {Type of ECC (0,1,2,3)} ${ECC_ENABLE}
set SELF_REFRESH [ipgui::add_param $IPINST -name "SELF_REFRESH" -parent ${Page_0} -widget comboBox]
set_property tooltip {Enable option for self-refresh} ${SELF_REFRESH}
set SKIP_INTERNAL_TEST [ipgui::add_param $IPINST -name "SKIP_INTERNAL_TEST" -parent ${Page_0}]
set_property tooltip {Check to skip built-in self-test (check this if UberDDR3 will be connected to Microblaze)} ${SKIP_INTERNAL_TEST}
set BIST_MODE [ipgui::add_param $IPINST -name "BIST_MODE" -parent ${Page_0} -widget comboBox]
set_property tooltip {Type of Built-In Self Test (BIST)} ${BIST_MODE}
set ODELAY_SUPPORTED [ipgui::add_param $IPINST -name "ODELAY_SUPPORTED" -parent ${Page_0}]
set_property tooltip {Check if FPGA supports ODELAYE2 primitive (e.g. FPGA with HP banks like Kintex-7)} ${ODELAY_SUPPORTED}
set MICRON_SIM [ipgui::add_param $IPINST -name "MICRON_SIM" -parent ${Page_0}]
@ -187,6 +187,15 @@ proc validate_PARAM_VALUE.BA_BITS { PARAM_VALUE.BA_BITS } {
return true
}
proc update_PARAM_VALUE.BIST_MODE { PARAM_VALUE.BIST_MODE } {
# Procedure called to update BIST_MODE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BIST_MODE { PARAM_VALUE.BIST_MODE } {
# Procedure called to validate BIST_MODE
return true
}
proc update_PARAM_VALUE.BYTE_LANES { PARAM_VALUE.BYTE_LANES } {
# Procedure called to update BYTE_LANES when any of the dependent parameters in the arguments change
}
@ -295,15 +304,6 @@ proc validate_PARAM_VALUE.SELF_REFRESH { PARAM_VALUE.SELF_REFRESH } {
return true
}
proc update_PARAM_VALUE.SKIP_INTERNAL_TEST { PARAM_VALUE.SKIP_INTERNAL_TEST } {
# Procedure called to update SKIP_INTERNAL_TEST when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SKIP_INTERNAL_TEST { PARAM_VALUE.SKIP_INTERNAL_TEST } {
# Procedure called to validate SKIP_INTERNAL_TEST
return true
}
proc update_PARAM_VALUE.WB2_ADDR_BITS { PARAM_VALUE.WB2_ADDR_BITS } {
# Procedure called to update WB2_ADDR_BITS when any of the dependent parameters in the arguments change
}
@ -406,11 +406,6 @@ proc update_MODELPARAM_VALUE.WB_ERROR { MODELPARAM_VALUE.WB_ERROR PARAM_VALUE.WB
set_property value [get_property value ${PARAM_VALUE.WB_ERROR}] ${MODELPARAM_VALUE.WB_ERROR}
}
proc update_MODELPARAM_VALUE.SKIP_INTERNAL_TEST { MODELPARAM_VALUE.SKIP_INTERNAL_TEST PARAM_VALUE.SKIP_INTERNAL_TEST } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SKIP_INTERNAL_TEST}] ${MODELPARAM_VALUE.SKIP_INTERNAL_TEST}
}
proc update_MODELPARAM_VALUE.ECC_ENABLE { MODELPARAM_VALUE.ECC_ENABLE PARAM_VALUE.ECC_ENABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ECC_ENABLE}] ${MODELPARAM_VALUE.ECC_ENABLE}
@ -481,3 +476,8 @@ proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PA
set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.BIST_MODE { MODELPARAM_VALUE.BIST_MODE PARAM_VALUE.BIST_MODE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BIST_MODE}] ${MODELPARAM_VALUE.BIST_MODE}
}