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UberDDR3
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run @ 133MHz with yosys

This commit is contained in:
AngeloJacobo 2025-12-31 14:40:04 +08:00
parent ad50f79695
commit 31b3642fbe
4 changed files with 15 additions and 14 deletions
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11
example_demo/alinx_ax7325b/ax7325b_ddr3.v
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@ -164,13 +164,13 @@
// DDR3 Controller
ddr3_top #(
.CONTROLLER_CLK_PERIOD(8_000), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(2_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.CONTROLLER_CLK_PERIOD(10_000), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(2_500), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.ROW_BITS(15), //width of row address
.COL_BITS(10), //width of column address
.BA_BITS(3), //width of bank address
.BYTE_LANES(2), //number of DDR3 modules to be controlled
.AUX_WIDTH(16), //width of aux line (must be >= 4)
.AUX_WIDTH(4), //width of aux line (must be >= 4)
.WB2_ADDR_BITS(32), //width of 2nd wishbone address bus
.WB2_DATA_BITS(32), //width of 2nd wishbone data bus
.MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
@ -178,7 +178,8 @@
.SECOND_WISHBONE(0), //set to 1 if 2nd wishbone is needed
.ECC_ENABLE(0), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
.WB_ERROR(0), // set to 1 to support Wishbone error (asserts at ECC double bit error)
.BIST_MODE(1)
.BIST_MODE(1), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
.SPEED_BIN(1) // 0 = Use top-level parameters , 1 = DDR3-1066 (7-7-7) , 2 = DR3-1333 (9-9-9) , 3 = DDR3-1600 (11-11-11)
) ddr3_top
(
//clock and reset
@ -217,7 +218,7 @@
.o_ddr3_clk_n(ddr3_ck_n),
.o_ddr3_reset_n(ddr3_reset_n),
.o_ddr3_cke(ddr3_cke), // CKE
.o_ddr3_cs_n(ddr3_cs_n[0]), // chip select signal (controls rank 1 only)
.o_ddr3_cs_n(ddr3_cs_n), // chip select signal (controls rank 1 only)
.o_ddr3_ras_n(ddr3_ras_n), // RAS#
.o_ddr3_cas_n(ddr3_cas_n), // CAS#
.o_ddr3_we_n(ddr3_we_n), // WE#

8
example_demo/alinx_ax7325b/ax7325b_ddr3.xdc
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@ -632,25 +632,25 @@ set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[7]}]
# PadFunction: IO_L15P_T2_DQS_32
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}]
set_property PACKAGE_PIN Y19 [get_ports {ddr3_dqs_p[0]}]
# PadFunction: IO_L15N_T2_DQS_32
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}]
set_property PACKAGE_PIN Y18 [get_ports {ddr3_dqs_n[0]}]
# PadFunction: IO_L9P_T1_DQS_32
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_p[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}]
set_property PACKAGE_PIN AJ18 [get_ports {ddr3_dqs_p[1]}]
# PadFunction: IO_L9N_T1_DQS_32
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}]
set_property PACKAGE_PIN AK18 [get_ports {ddr3_dqs_n[1]}]
# PadFunction: IO_L3P_T0_DQS_32

BIN
example_demo/alinx_ax7325b/ax7325b_ddr3_openxc7.bit
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10
example_demo/alinx_ax7325b/clk_wiz.v
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@ -23,18 +23,18 @@ module clk_wiz
.COMPENSATION ("INTERNAL"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (5), // 200 MHz * 5 = 1000 MHz
.CLKFBOUT_MULT (8), // 200 MHz * 8 = 1600 MHz
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (8), // 1000 MHz / 8 = 125 MHz
.CLKOUT0_DIVIDE (12), // 1600 MHz / 12 = 133.333 MHz
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (2), // 1000 MHz / 2 = 500 MHz, 0 phase
.CLKOUT1_DIVIDE (3), // 1600 MHz / 3 = 533.333 MHz, 0 phase
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (5), // 1000 MHz / 5 = 200 MHz
.CLKOUT2_DIVIDE (8), // 1600 MHz / 8 = 200 MHz
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DIVIDE (2), // 1000 MHz / 2 = 500 MHz, 90 phase
.CLKOUT3_DIVIDE (3), // 1600 MHz / 3 = 533.333 MHz, 90 phase
.CLKOUT3_PHASE (90.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (5.000) // 200 MHz input