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modified vivado simulation files

This commit is contained in:
AngeloJacobo 2025-05-24 17:33:49 +08:00
parent 972506bb4b
commit cb5f78b057
3 changed files with 22 additions and 11 deletions
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22
testbench/xsim/file_info.txt
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@ -1,14 +1,14 @@
IDELAYCTRL_model.v,verilog,xil_defaultlib,../../testbench/IDELAYCTRL_model.v,incdir="../../testbench"
IDELAYE2_model.v,verilog,xil_defaultlib,../../testbench/IDELAYE2_model.v,incdir="../../testbench"
IOBUF_DCIEN.v,verilog,xil_defaultlib,../../testbench/IOBUF_DCIEN.v,incdir="../../testbench"
IOBUF_model.v,verilog,xil_defaultlib,../../testbench/IOBUF_model.v,incdir="../../testbench"
IOBUFDS_DCIEN_model.v,verilog,xil_defaultlib,../../testbench/IOBUFDS_DCIEN_model.v,incdir="../../testbench"
IOBUFDS_model.v,verilog,xil_defaultlib,../../testbench/IOBUFDS_model.v,incdir="../../testbench"
ISERDESE2_model.v,verilog,xil_defaultlib,../../testbench/ISERDESE2_model.v,incdir="../../testbench"
OBUFDS_model.v,verilog,xil_defaultlib,../../testbench/OBUFDS_model.v,incdir="../../testbench"
ODELAYE2_model.v,verilog,xil_defaultlib,../../testbench/ODELAYE2_model.v,incdir="../../testbench"
OSERDESE2_model.v,verilog,xil_defaultlib,../../testbench/OSERDESE2_model.v,incdir="../../testbench"
OBUF_model.v,verilog,xil_defaultlib,../../testbench/OBUF_model.v,incdir="../../testbench"
IDELAYCTRL_model.v,verilog,xil_defaultlib,../../testbench/models/IDELAYCTRL_model.v,incdir="../../testbench"
IDELAYE2_model.v,verilog,xil_defaultlib,../../testbench/models/IDELAYE2_model.v,incdir="../../testbench"
IOBUF_DCIEN.v,verilog,xil_defaultlib,../../testbench/models/IOBUF_DCIEN.v,incdir="../../testbench"
IOBUF_model.v,verilog,xil_defaultlib,../../testbench/models/IOBUF_model.v,incdir="../../testbench"
IOBUFDS_DCIEN_model.v,verilog,xil_defaultlib,../../testbench/models/IOBUFDS_DCIEN_model.v,incdir="../../testbench"
IOBUFDS_model.v,verilog,xil_defaultlib,../../testbench/models/IOBUFDS_model.v,incdir="../../testbench"
ISERDESE2_model.v,verilog,xil_defaultlib,../../testbench/models/ISERDESE2_model.v,incdir="../../testbench"
OBUFDS_model.v,verilog,xil_defaultlib,../../testbench/models/OBUFDS_model.v,incdir="../../testbench"
ODELAYE2_model.v,verilog,xil_defaultlib,../../testbench/models/ODELAYE2_model.v,incdir="../../testbench"
OSERDESE2_model.v,verilog,xil_defaultlib,../../testbench/models/OSERDESE2_model.v,incdir="../../testbench"
OBUF_model.v,verilog,xil_defaultlib,../../testbench/models/OBUF_model.v,incdir="../../testbench"
ddr3_controller.v,verilog,xil_defaultlib,../../rtl/ddr3_controller.v,incdir="../../testbench"
ddr3_phy.v,verilog,xil_defaultlib,../../rtl/ddr3_phy.v,incdir="../../testbench"

0
testbench/xsim/regression_test.sh → testbench/xsim/regression_test_vivado.sh
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11
testbench/xsim/vlog.prj
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@ -1,4 +1,15 @@
verilog xil_defaultlib --include "../../testbench" \
"../../testbench/models/IDELAYCTRL_model.v" \
"../../testbench/models/IDELAYE2_model.v" \
"../../testbench/models/IOBUF_DCIEN.v" \
"../../testbench/models/IOBUF_model.v" \
"../../testbench/models/IOBUFDS_DCIEN_model.v" \
"../../testbench/models/IOBUFDS_model.v" \
"../../testbench/models/ISERDESE2_model.v" \
"../../testbench/models/OBUFDS_model.v" \
"../../testbench/models/ODELAYE2_model.v" \
"../../testbench/models/OSERDESE2_model.v" \
"../../testbench/models/OBUF_model.v" \
"../../rtl/ddr3_controller.v" \
"../../rtl/ddr3_phy.v" \
"../../rtl/ddr3_top.v" \