added simulation for DLL Off (low frequency ddr3 clk)
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AngeloJacobo
parent
baaa2a2482
commit
73431cdd82
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@ -137,6 +137,7 @@ module ddr3 (
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parameter feature_odt_hi = 0;
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parameter PERTCKAVG=TDLLK;
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parameter FLY_BY_DELAY = 0, DQ_DELAY = 0;
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parameter[0:0] DLL_OFF = 0;
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// text macros
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`define DQ_PER_DQS DQ_BITS/DQS_BITS
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@ -1662,7 +1663,7 @@ module ddr3 (
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$display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time);
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tm_txpr <= $time;
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ck_txpr <= ck_cntr;
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init_step = init_step + 1;
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init_step = init_step + 2;
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end
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1 : begin
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if (dll_en) init_step = init_step + 1;
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@ -1770,7 +1771,7 @@ module ddr3 (
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for (i=0; i<64; i=i+1) begin
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if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
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$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/32], i%32);
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if (check_write_dqs_high[i])
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if (check_write_dqs_high[i] && !DLL_OFF)
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$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/32], i%32);
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end
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check_write_dqs_high <= 0;
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@ -1781,7 +1782,7 @@ module ddr3 (
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if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
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$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/32], i%32);
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end
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if (check_write_dqs_low[i])
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if (check_write_dqs_low[i] && !DLL_OFF)
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$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/32], i%32);
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end
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check_write_preamble <= 0;
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@ -2249,8 +2250,8 @@ module ddr3 (
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$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
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if (TCK_MIN - tck_avg >= 1.0)
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$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
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if (tck_avg - TCK_MAX >= 1.0)
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$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
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if ((tck_avg - TCK_MAX >= 1.0) && !DLL_OFF)
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$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
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// check tCL
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if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg)
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@ -2800,7 +2801,7 @@ module ddr3 (
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check_write_postamble[i] <= 1'b0;
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check_write_dqs_low[i] <= 1'b0;
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tm_dqs[i%32] <= $time;
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end else begin
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end else if(!DLL_OFF) begin
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$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/32], i%32);
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end
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end
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@ -2906,7 +2907,7 @@ module ddr3 (
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end
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check_dm_tdipw[i%32] <= 1'b1;
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tm_dqs[i%32] <= $time;
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end else begin
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end else if(!DLL_OFF) begin
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$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/32], i%32);
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end
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end
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@ -57,16 +57,16 @@ module ddr3_dimm_micron_sim;
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`endif
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localparam CONTROLLER_CLK_PERIOD = 5_000, //ps, period of clock input to this DDR3 controller module
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DDR3_CLK_PERIOD = 1_250, //ps, period of clock input to DDR3 RAM device
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localparam CONTROLLER_CLK_PERIOD = 12_000, //ps, period of clock input to this DDR3 controller module
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DDR3_CLK_PERIOD = 3_000, //ps, period of clock input to DDR3 RAM device
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AUX_WIDTH = 16, // AUX lines
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ECC_ENABLE = 0, // ECC enable
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SELF_REFRESH = 2'b00,
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DUAL_RANK_DIMM = 0,
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TEST_SELF_REFRESH = 0,
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SECOND_WISHBONE = 0,
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BIST_MODE = 1; // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
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BIST_MODE = 2, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
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DLL_OFF = 1;
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reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
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reg i_rst_n;
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@ -171,7 +171,8 @@ ddr3_top #(
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.WB_ERROR(1), // set to 1 to support Wishbone error (asserts at ECC double bit error)
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.BIST_MODE(BIST_MODE), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
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.SELF_REFRESH(SELF_REFRESH), // 0 = use i_user_self_refresh input, 1 = Self-refresh mode is enabled after 64 controller clock cycles of no requests, 2 = 128 cycles, 3 = 256 cycles
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.DUAL_RANK_DIMM(DUAL_RANK_DIMM) // enable dual rank DIMM (1 = enable, 0 = disable)
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.DUAL_RANK_DIMM(DUAL_RANK_DIMM), // enable dual rank DIMM (1 = enable, 0 = disable)
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.DLL_OFF(DLL_OFF) // 1 = DLL off for low frequency ddr3 clock
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) ddr3_top
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(
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//clock and reset
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@ -227,7 +228,7 @@ ddr3_top #(
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`ifdef TWO_LANES_x8
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// 1 lane DDR3
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ddr3 ddr3_0(
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ddr3 #(.DLL_OFF(DLL_OFF)) ddr3_0(
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.rst_n(reset_n),
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.ck(o_ddr3_clk_p[0]),
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.ck_n(o_ddr3_clk_n[0]),
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@ -249,7 +250,7 @@ ddr3_top #(
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`ifdef EIGHT_LANES_x8
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// DDR3 Device
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ddr3_module ddr3_module(
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ddr3_module #(.DLL_OFF(DLL_OFF)) ddr3_module(
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.reset_n(reset_n),
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.ck(o_ddr3_clk_p), //[1:0]
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.ck_n(o_ddr3_clk_n), //[1:0]
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@ -87,6 +87,8 @@ module ddr3_module (
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input scl ; // no connect
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inout sda ; // no connect
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parameter DLL_OFF = 0;
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`ifdef QUAD_RANK
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initial if (DEBUG) $display("%m: Quad Rank");
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`elsif DUAL_RANK
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@ -304,14 +306,14 @@ module ddr3_module (
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`endif
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`elsif x8
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initial if (DEBUG) $display("%m: Component Width = x8");
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_0)) U1R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[ 0] , dqs_n[ 0] , dqs_n[ 9], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_1)) U2R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[ 1] , dqs_n[ 1] , dqs_n[10], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_2)) U3R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[ 2] , dqs_n[ 2] , dqs_n[11], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_3)) U4R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[ 3] , dqs_n[ 3] , dqs_n[12], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_4)) U6R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[ 4] , dqs_n[ 4] , dqs_n[13], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_5)) U7R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[ 5] , dqs_n[ 5] , dqs_n[14], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_6)) U8R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[ 6] , dqs_n[ 6] , dqs_n[15], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_7)) U9R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[ 7] , dqs_n[ 7] , dqs_n[16], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_0), .DLL_OFF(DLL_OFF)) U1R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[ 0] , dqs_n[ 0] , dqs_n[ 9], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_1), .DLL_OFF(DLL_OFF)) U2R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[ 1] , dqs_n[ 1] , dqs_n[10], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_2), .DLL_OFF(DLL_OFF)) U3R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[ 2] , dqs_n[ 2] , dqs_n[11], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_3), .DLL_OFF(DLL_OFF)) U4R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[ 3] , dqs_n[ 3] , dqs_n[12], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_4), .DLL_OFF(DLL_OFF)) U6R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[ 4] , dqs_n[ 4] , dqs_n[13], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_5), .DLL_OFF(DLL_OFF)) U7R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[ 5] , dqs_n[ 5] , dqs_n[14], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_6), .DLL_OFF(DLL_OFF)) U8R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[ 6] , dqs_n[ 6] , dqs_n[15], rodt[0]);
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ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_7), .DLL_OFF(DLL_OFF)) U9R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[ 7] , dqs_n[ 7] , dqs_n[16], rodt[0]);
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`ifdef ECC
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ddr3 U5R0 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[17] , rba, raddr[ADDR_BITS-1:0], rcb[ 7: 0], dqs[ 8] , dqs_n[ 8] , dqs_n[17], rodt[0]);
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`endif
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