fix flagged errors from openxc7 (shiftin grounded, iodelay_group string)
This commit is contained in:
AngeloJacobo
parent
0c484d54f6
commit
e8444fb379
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@ -211,8 +211,10 @@ module ddr3_phy #(
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.D7(),
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.D8(),
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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`ifndef YOSYS // openxc7 run fails if this is connected to ground
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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`endif
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T1(0),
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.T2(0),
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@ -261,8 +263,10 @@ module ddr3_phy #(
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.D7(),
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.D8(),
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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`ifndef YOSYS // openxc7 run fails if this is connected to ground
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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`endif
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T1(0),
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.T2(0),
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@ -335,8 +339,10 @@ module ddr3_phy #(
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.TFB(), // 1-bit output: 3-state control
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.TQ(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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`ifndef YOSYS // openxc7 run fails if this is connected to ground
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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`endif
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T1(0),
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.T2(0),
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@ -351,7 +357,7 @@ module ddr3_phy #(
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//Delay the DQ
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// Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
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(* IODELAY_GROUP="DDR3-GROUP" *)
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(* IODELAY_GROUP = 0 *)
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ODELAYE2 #(
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.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
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.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
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@ -477,8 +483,10 @@ module ddr3_phy #(
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.TBYTEOUT(), // 1-bit output: Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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`ifndef YOSYS // openxc7 run fails if this is connected to ground
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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`endif
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T2(0),
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.T3(0),
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@ -494,7 +502,7 @@ module ddr3_phy #(
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//odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US
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//Delay the DQ
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// Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
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(* IODELAY_GROUP="DDR3-GROUP" *)
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(* IODELAY_GROUP = 0 *)
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ODELAYE2 #(
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.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
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.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
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@ -593,8 +601,10 @@ module ddr3_phy #(
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.TBYTEOUT(), // 1-bit output: Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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`ifndef YOSYS // openxc7 run fails if this is connected to ground
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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`endif
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T2(0),
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.T3(0),
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@ -623,7 +633,7 @@ module ddr3_phy #(
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// IDELAYE2: Input Fixed or Variable Delay Element
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// 7 Series
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// Xilinx HDL Libraries Guide, version 13.4
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(* IODELAY_GROUP="DDR3-GROUP" *)
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(* IODELAY_GROUP = 0 *)
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IDELAYE2 #(
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.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
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.HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
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@ -757,8 +767,10 @@ module ddr3_phy #(
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.TFB(), // 1-bit output: 3-state control
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.TQ(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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`ifndef YOSYS // openxc7 run fails if this is connected to ground
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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`endif
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T1(0),
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.T2(0),
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@ -775,7 +787,7 @@ module ddr3_phy #(
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//odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US
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//Delay the DQ
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// Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
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(* IODELAY_GROUP="DDR3-GROUP" *)
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(* IODELAY_GROUP = 0 *)
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ODELAYE2 #(
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.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
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.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
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@ -847,8 +859,10 @@ module ddr3_phy #(
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.TFB(), // 1-bit output: 3-state control
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.TQ(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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`ifndef YOSYS // openxc7 run fails if this is connected to ground
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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`endif
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T1(0),
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.T2(0),
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@ -913,8 +927,10 @@ module ddr3_phy #(
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.TBYTEOUT(), // 1-bit output: Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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`ifndef YOSYS // openxc7 run fails if this is connected to ground
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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`endif
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T2(0),
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.T3(0),
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@ -929,7 +945,7 @@ module ddr3_phy #(
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// 7 Series
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// Xilinx HDL Libraries Guide, version 13.4
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//Delay the DQ
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(* IODELAY_GROUP="DDR3-GROUP" *)
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(* IODELAY_GROUP = 0 *)
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ODELAYE2 #(
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.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
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.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
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@ -1032,8 +1048,10 @@ module ddr3_phy #(
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.TBYTEOUT(), // 1-bit output: Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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`ifndef YOSYS // openxc7 run fails if this is connected to ground
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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`endif
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T2(0),
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.T3(0),
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@ -1064,7 +1082,7 @@ module ddr3_phy #(
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// IDELAYE2: Input Fixed or Variable Delay Element
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// 7 Series
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// Xilinx HDL Libraries Guide, version 13.4
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(* IODELAY_GROUP="DDR3-GROUP" *)
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(* IODELAY_GROUP = 0 *)
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IDELAYE2 #(
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.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
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.HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
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@ -1282,8 +1300,10 @@ module ddr3_phy #(
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.TFB(), // 1-bit output: 3-state control
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.TQ(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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`ifndef YOSYS // openxc7 run fails if this is connected to ground
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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`endif
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T1(0),
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.T2(0),
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@ -1304,7 +1324,7 @@ module ddr3_phy #(
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// IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
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// 7 Series
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// Xilinx HDL Libraries Guide, version 13.4
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(* IODELAY_GROUP="DDR3-GROUP" *)
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(* IODELAY_GROUP = 0 *)
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IDELAYCTRL IDELAYCTRL_inst (
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.RDY(idelayctrl_rdy), // 1-bit output: Ready output
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.REFCLK(i_ref_clk), // 1-bit input: Reference clock input.The frequency of REFCLK must be 200 MHz to guarantee the tap-delay value specified in the applicable data sheet.
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