run @ 125MHz with yosys

example_demo/qmtech_kintex_7/clk_wiz.v

@@ -24,16 +24,16 @@ module clk_wiz
     .DIVCLK_DIVIDE        (1),
     .CLKFBOUT_MULT        (20), // 50 MHz * 20 = 1000 MHz
     .CLKFBOUT_PHASE       (0.000),
-    .CLKOUT0_DIVIDE       (12), // 1000 MHz / 12 = 83.333 MHz
+    .CLKOUT0_DIVIDE       (8), // 1000 MHz / 8 = 125 MHz
     .CLKOUT0_PHASE        (0.000),
     .CLKOUT0_DUTY_CYCLE   (0.500),
-    .CLKOUT1_DIVIDE       (3), // 1000 MHz / 3 = 333.333 MHz
+    .CLKOUT1_DIVIDE       (2), // 1000 MHz / 2 = 500 MHz
     .CLKOUT1_PHASE        (0.000),
     .CLKOUT1_DUTY_CYCLE   (0.500),
     .CLKOUT2_DIVIDE       (5), // 1000 MHz / 5 = 200 MHz
     .CLKOUT2_PHASE        (0.000),
     .CLKOUT2_DUTY_CYCLE   (0.500),
-    .CLKOUT3_DIVIDE       (3), // 1000 MHz / 3 = 333.333 MHz, 90 phase
+    .CLKOUT3_DIVIDE       (2), // 1000 MHz / 2 = 500 MHz, 90 phase
     .CLKOUT3_PHASE        (90.000),
     .CLKOUT3_DUTY_CYCLE   (0.500),
     .CLKIN1_PERIOD        (20.000) // 50 MHz input

example_demo/qmtech_kintex_7/qmtech_kintex7_ddr3.v

@@ -141,8 +141,8 @@
     
     // DDR3 Controller 
     ddr3_top #(
-        .CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
-        .DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+        .CONTROLLER_CLK_PERIOD(10_000), //ps, clock period of the controller interface
+        .DDR3_CLK_PERIOD(2_500), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
         .ROW_BITS(14), //width of row address
         .COL_BITS(10), //width of column address
         .BA_BITS(3), //width of bank address
@@ -152,7 +152,9 @@
         .WB2_DATA_BITS(32), //width of 2nd wishbone data bus
         .MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
         .ODELAY_SUPPORTED(1), //set to 1 when ODELAYE2 is supported
-        .SECOND_WISHBONE(0) //set to 1 if 2nd wishbone is needed 
+        .SECOND_WISHBONE(0), //set to 1 if 2nd wishbone is needed 
+        .BIST_MODE(1), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
+        .SPEED_BIN(1) // 0 = Use top-level parameters , 1 = DDR3-1066 (7-7-7) , 2 = DR3-1333 (9-9-9) , 3 = DDR3-1600 (11-11-11)
         ) ddr3_top
         (
             //clock and reset