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uberddr3 test on enclustra board, with MicroBlaze for summary reporting via UART

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AngeloJacobo 2025-02-13 19:27:11 +08:00
parent 97424583ba
commit c21b8a0a37
19 changed files with 3364 additions and 166 deletions
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367
example_demo/enclustra_kx2_st1/ddr3_test.v Normal file
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////////////////////////////////////////////////////////////////////////////////
//
// Filename: ddr3_test.v
// Project: Test the UberDDR3 by sending traffic via the Wishbone interface
//
// Purpose: Sends traffic over Wishbone interface of UberDDR3. This has 3 tests:
// - burst write/read
// - random write/read
// - alternating write/read
// Uses MicroBlaze to report via UART the number of read matches, mismatches, and
// total time elapsed. Report summary is sent every second.
//
// Engineer: Angelo C. Jacobo
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2023-2025 Angelo Jacobo
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////////////
// `default_nettype none
`timescale 1ps / 1ps
module ddr3_test #(
parameter WB_ADDR_BITS = 25,
WB_DATA_BITS = 512,
WB_SEL_BITS = WB_DATA_BITS / 8,
AUX_WIDTH = 4,
DATA_MASK = 1,
parameter[0:0] MICRON_SIM = 0
)
(
input wire i_clk, // ddr3 test clock
input wire i_clk100, // microblaze clock
input wire i_rst_n,
//
// Wishbone inputs
output reg o_wb_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
output reg o_wb_stb, //request a transfer
output reg o_wb_we, //write-enable (1 = write, 0 = read)
output reg[WB_ADDR_BITS - 1:0] o_wb_addr, //burst-addressable {row,bank,col}
output reg[WB_DATA_BITS - 1:0] o_wb_data, //write data, for a 4:1 controller data width is 8 times the number of pins on the device
output reg[WB_SEL_BITS - 1:0] o_wb_sel, //byte strobe for write (1 = write the byte)
output reg[AUX_WIDTH - 1:0] o_aux, //for AXI-interface compatibility (given upon strobe)
//
// Wishbone outputs
input wire i_wb_stall, //1 = busy, cannot accept requests
input wire i_wb_ack, //1 = read/write request has completed
input wire i_wb_err, //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
input wire[WB_DATA_BITS - 1:0] i_wb_data, //read data, for a 4:1 controller data width is 8 times the number of pins on the device
input wire[AUX_WIDTH - 1:0] i_aux, //for AXI-interface compatibility (given upon strobe)
//
// Done Calibration pin
input wire i_calib_complete,
//
// UART line
input wire rx,
output wire tx,
// Button for fault-injection
input wire btn,
//
// Debug
output wire timer_pulse,
output wire wrong_data_counter_non_zero
);
localparam IDLE=0,
BURST_WRITE=1,
BURST_READ=2,
RANDOM_WRITE=3,
RANDOM_READ=4,
ALTERNATE_WRITE_READ=5,
DONE_TEST=6;
localparam SIM_ADDRESS_INCR_LOG2 = WB_ADDR_BITS-2-6; // 2^(WB_ADDR_BITS-2)/64
localparam HALF_ADDRESS = 13;
localparam SIM_ADDRESS_START = {(WB_ADDR_BITS){1'b1}} - 99; // minus odd number so result is even (similar to default address start of zero)
(* mark_debug = "true" *) reg[3:0] state=IDLE;
reg[3:0] rest_counter=0;
wire[WB_DATA_BITS-1:0] correct_data;
wire[WB_DATA_BITS-1:0] wb_data_randomized;
reg[WB_ADDR_BITS-1:0] write_test_address_counter = 0, read_test_address_counter = 0;
reg[WB_ADDR_BITS-1:0] check_test_address_counter = 0;
reg[$clog2(WB_SEL_BITS)-1:0] write_by_byte_counter = 0;
(* mark_debug = "true" *) reg[63:0] correct_read_data_counter = 0, wrong_read_data_counter = 0; // 64-bit counter for correct and wrong read data, this make sure the counter will not overflow when several day's worth of DDR3 test is done on hardware
(* mark_debug = "true" *) reg[WB_DATA_BITS-1:0] wrong_data, expected_data;
reg[63:0] time_counter = 0;
(* mark_debug = "true" *) reg[31:0] injected_faults_counter = 0;
assign timer_pulse = time_counter[27]; // 1.34 sec
assign wrong_data_counter_non_zero = wrong_read_data_counter != 0; // pulse when there is wrong data
always @(posedge i_clk, negedge i_rst_n) begin
if(!i_rst_n) begin
state <= IDLE;
rest_counter <= 0;
o_wb_cyc <= 0;
o_wb_stb <= 0;
o_wb_we <= 0;
o_wb_addr <= 0;
o_wb_data <= 0;
o_wb_sel <= 0;
o_aux <= 0;
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
rest_counter <= 0;
read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
write_by_byte_counter <= 0;
injected_faults_counter <= 0;
end
else begin
case(state)
IDLE: if(i_calib_complete) begin // wait until DDR3 is done calibrating
rest_counter = rest_counter + 1;
if(rest_counter == 4'hf) begin // rest for 16 cycles before starting test
state <= BURST_WRITE;
o_wb_cyc <= 1'b1;
end
end
else begin
o_wb_cyc <= 0;
o_wb_stb <= 0;
o_wb_we <= 0;
o_wb_addr <= 0;
o_wb_data <= 0;
o_wb_sel <= 0;
o_aux <= 0;
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
rest_counter <= 0;
read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
write_by_byte_counter <= 0;
injected_faults_counter <= 0;
end
BURST_WRITE: if(!i_wb_stall) begin // Test 1: Burst write (per byte write to test datamask feature), then burst read
o_wb_stb <= 1'b1;
o_aux <= 2; // write
o_wb_we <= 1;
if(DATA_MASK) begin // If datamasking is available, test datamask by writing 8 bytes at a time
o_wb_sel <= {{WB_SEL_BITS-8{1'b0}}, 8'hff} << write_by_byte_counter; // write_by_byte_counter increments by 8 from 0 to (WB_SEL_BITS-8)
o_wb_addr <= write_test_address_counter;
o_wb_data <= {WB_SEL_BITS{8'haa}}; // fill data initially by 8'haa
o_wb_data[8*write_by_byte_counter +: 64] <= btn_pulse? {64{1'b0}} : wb_data_randomized[8*write_by_byte_counter +: 64]; // place the real data at the datamasked bytes
injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
if(write_by_byte_counter == (WB_SEL_BITS-8)) begin // once every 64bytes of data is written, go to next address
write_test_address_counter <= write_test_address_counter + 1;
/* verilator lint_off WIDTHEXPAND */
if( write_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin // wait until all address space is writtten
/* verilator lint_on WIDTHEXPAND */
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= BURST_READ;
end
end
write_by_byte_counter <= write_by_byte_counter + 8;
end
else begin // Burst write to all bytes (all datamask on)
o_wb_sel <= {WB_SEL_BITS{1'b1}};
o_wb_addr <= write_test_address_counter;
o_wb_data <= btn_pulse? {WB_DATA_BITS{1'b0}} : wb_data_randomized;
injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
write_test_address_counter <= write_test_address_counter + 1;
/* verilator lint_off WIDTHEXPAND */
if( write_test_address_counter == {WB_ADDR_BITS{1'b1}} ) begin // wait until all address space is writtten
/* verilator lint_on WIDTHEXPAND */
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= BURST_READ;
end
end
end
BURST_READ: if(!i_wb_stall) begin
o_wb_stb <= 1'b1;
o_aux <= 3; // read
o_wb_we <= 0;
o_wb_addr <= read_test_address_counter;
read_test_address_counter <= read_test_address_counter + 1;
/* verilator lint_off WIDTHEXPAND */
if( read_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin // wait until all address space is read
/* verilator lint_on WIDTHEXPAND */
read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= RANDOM_WRITE;
end
end
RANDOM_WRITE: if(!i_wb_stall) begin // Test 2: Random write (increments row address to force precharge-act-r/w) then random read
o_wb_stb <= 1'b1;
o_aux <= 2; // write
o_wb_sel <= {WB_SEL_BITS{1'b1}};
o_wb_we <= 1;
// swap the halves of address counter, since address mapping is {row,bank,col} then every increment of address counter will now increment the {row, bank} preventing burst operation and forcing precharge-activate before write/read
o_wb_addr[WB_ADDR_BITS-1:HALF_ADDRESS] <= write_test_address_counter[HALF_ADDRESS-1:0]; // [25:13] <= [12:0]
o_wb_addr[HALF_ADDRESS-1:0] <= write_test_address_counter[WB_ADDR_BITS-1:HALF_ADDRESS]; // [12:0] <= [25:13]
o_wb_data <= btn_pulse? {WB_DATA_BITS{1'b0}} : wb_data_randomized;
injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
write_test_address_counter <= write_test_address_counter + 1;
/* verilator lint_off WIDTHEXPAND */
if( write_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin // wait until all address space is writtten
/* verilator lint_on WIDTHEXPAND */
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= RANDOM_READ;
end
end
RANDOM_READ: if(!i_wb_stall) begin
o_wb_stb <= 1'b1;
o_aux <= 3; // read
o_wb_we <= 0;
// swap the halves of address counter, since address mapping is {row,bank,col} then every increment of address counter will now increment the {row, bank} preventing burst operation and forcing precharge-activate before write/read
o_wb_addr[WB_ADDR_BITS-1:HALF_ADDRESS] <= read_test_address_counter[HALF_ADDRESS-1:0]; // [25:13] <= [12:0]
o_wb_addr[HALF_ADDRESS-1:0] <= read_test_address_counter[WB_ADDR_BITS-1:HALF_ADDRESS]; // [12:0] <= [25:13]
read_test_address_counter <= read_test_address_counter + 1;
/* verilator lint_off WIDTHEXPAND */
if( read_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin // wait until all address space is read
/* verilator lint_on WIDTHEXPAND */
read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= ALTERNATE_WRITE_READ;
end
end
ALTERNATE_WRITE_READ: if(!i_wb_stall) begin
o_wb_stb <= 1'b1;
o_aux <= 2 + (o_wb_we? 1:0); //2 (write), 3 (read)
o_wb_sel <= {WB_SEL_BITS{1'b1}};
o_wb_we <= !o_wb_we; // alternating write-read
o_wb_addr <= write_test_address_counter;
o_wb_data <= btn_pulse? {WB_DATA_BITS{1'b0}} : wb_data_randomized;
injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
// if current operation is write, then dont increment address since we wil read the same address next
if(o_wb_we) begin // current operation is read thus increment address
write_test_address_counter <= write_test_address_counter + 1;
end
/* verilator lint_off WIDTHEXPAND */
if( (o_wb_addr == {(WB_ADDR_BITS){1'b1}}) && !o_wb_we ) begin // only
/* verilator lint_on WIDTHEXPAND */
write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
state <= DONE_TEST;
rest_counter <= 0;
end
end
DONE_TEST: begin
o_wb_stb <= 0;
rest_counter <= rest_counter + 1;
if(rest_counter == 4'hf) begin // rest for 16 cycles before repeating test
state <= BURST_WRITE;
end
end
endcase
end
end
// Uses different operations (XOR, addition, subtraction, bit rotation) to generate different values per byte.
assign wb_data_randomized = {
{(WB_SEL_BITS/8){write_test_address_counter[0 +: 8] ^ 8'hA5, // Byte 7
write_test_address_counter[0 +: 8] | 8'h1A, // Byte 6
write_test_address_counter[0 +: 8] & 8'h33, // Byte 5
write_test_address_counter[0 +: 8] ^ 8'h5A, // Byte 4
write_test_address_counter[0 +: 8] & 8'h21, // Byte 3
write_test_address_counter[0 +: 8] | 8'hC7, // Byte 2
write_test_address_counter[0 +: 8] ^ 8'h7E, // Byte 1
write_test_address_counter[0 +: 8] ^ 8'h3C}} // Byte 0
};
/******************************************************* Test Receiver *******************************************************/
assign correct_data = {
{(WB_SEL_BITS/8){check_test_address_counter[0 +: 8] ^ 8'hA5, // Byte 7
check_test_address_counter[0 +: 8] | 8'h1A, // Byte 6
check_test_address_counter[0 +: 8] & 8'h33, // Byte 5
check_test_address_counter[0 +: 8] ^ 8'h5A, // Byte 4
check_test_address_counter[0 +: 8] & 8'h21, // Byte 3
check_test_address_counter[0 +: 8] | 8'hC7, // Byte 2
check_test_address_counter[0 +: 8] ^ 8'h7E, // Byte 1
check_test_address_counter[0 +: 8] ^ 8'h3C }} // Byte 0
};
always @(posedge i_clk, negedge i_rst_n) begin
if(!i_rst_n) begin
check_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
correct_read_data_counter <= 64'd0;
wrong_read_data_counter <= 64'd0;
wrong_data <= 512'd0;
expected_data <= 512'd0;
end
else begin
if(i_calib_complete) begin
if ( i_wb_ack && i_aux[2:0] == 3'd3 ) begin //o_aux = 3 is for read requests from DDR3 test
if(i_wb_data == correct_data) begin // if read data matches the expected, increment correct_read_data_counter
correct_read_data_counter <= correct_read_data_counter + 64'd1;
end
else begin
wrong_read_data_counter <= wrong_read_data_counter + 64'd1;
wrong_data <= i_wb_data;
expected_data <= correct_data;
end
/* verilator lint_off WIDTHEXPAND */
check_test_address_counter <= check_test_address_counter + 1;
if(check_test_address_counter+1'b1 == {(WB_ADDR_BITS){1'b0}}) begin // if next address returns to zero, then if in MICRON_SIM jump to SIM_ADDRESS_START
check_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : {(WB_ADDR_BITS){1'b0}};
end
/* verilator lint_on WIDTHEXPAND */
end
end
else begin
check_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
correct_read_data_counter <= 64'd0;
wrong_read_data_counter <= 64'd0;
wrong_data <= 512'd0;
expected_data <= 512'd0;
end
end
end
/*********************************************************************************************************************************************/
// 64-bit counter to know how much time had passed and also debounce of btn for fault-injection
(* mark_debug = "true" *) reg[27:0] btn_debounce_delay;
(* mark_debug = "true" *) reg btn_pulse_long, btn_pulse_long_prev;
(* mark_debug = "true" *) wire btn_pulse;
assign btn_pulse = btn_pulse_long && !btn_pulse_long_prev; // if current btn_pulse is high but previously low (posedge) then make pulse
always @(posedge i_clk, negedge i_rst_n) begin
if(!i_rst_n) begin
btn_pulse_long_prev <= 1'b0;
btn_debounce_delay <= 0;
btn_pulse_long <= 0;
end
else begin
btn_pulse_long_prev <= btn_pulse_long;
if(btn && !btn_pulse_long) begin // when btn asserts and btn_pulse_long is still low
btn_pulse_long <= 1'b1;
end
if(btn_debounce_delay[27]) begin // if ~1.3s had passed, set btn_pulse_long low and reset delay
btn_pulse_long <= 0;
btn_debounce_delay <= 0;
end
else begin
btn_debounce_delay <= btn_pulse_long? btn_debounce_delay + 1 : 0;
end
end
end
always @(posedge i_clk100, negedge i_rst_n) begin
if(!i_rst_n) begin
time_counter <= 64'd0;
end
else begin
time_counter <= time_counter + 1;
end
end
design_1_wrapper microblaze_inst
( .clk_in1_0(i_clk100),
.correct_read_data_counter_0(correct_read_data_counter),
.reset_rtl_0(i_rst_n),
.time_counter_0(time_counter),
.injected_faults_counter_0(injected_faults_counter),
.uart_rtl_0_rxd(rx),
.uart_rtl_0_txd(tx),
.wrong_read_data_counter_0(wrong_read_data_counter)
);
endmodule

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example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/bd/bd.tcl Normal file
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proc init { cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
set full_sbusif_list [list ]
foreach busif $all_busif {
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
set busif_param_list [list]
set busif_name [get_property NAME $busif]
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
continue
}
foreach tparam $axi_standard_param_list {
lappend busif_param_list "C_${busif_name}_${tparam}"
}
bd::mark_propagate_only $cell_handle $busif_param_list
}
}
}
proc pre_propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
if { $val_on_cell != "" } {
set_property CONFIG.${tparam} $val_on_cell $busif
}
}
}
}
}
proc propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
if { $val_on_cell_intf_pin != "" } {
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
}
}
}
}
}

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example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/component.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>user.org</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>ddr3_test_monitor_axi</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>s00_axi</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="s00_axi"/>
</spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_awaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_awprot</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_awvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_awready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_wdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WSTRB</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_wstrb</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_wvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_wready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_bresp</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_bvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_bready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_araddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_arprot</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_arvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_arready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_rdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_rresp</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_rvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_rready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>s00_axi_aclk</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_aclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ACLK.ASSOCIATED_BUSIF">s00_axi</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ACLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>s00_axi_aresetn</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axi_aresetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>s00_axi</spirit:name>
<spirit:displayName>s00_axi</spirit:displayName>
<spirit:addressBlock>
<spirit:name>reg0</spirit:name>
<spirit:displayName>reg0</spirit:displayName>
<spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:baseAddress>
<spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH&apos;)) - 1) - 0 + 1)" spirit:minimum="4096" spirit:rangeType="long">4096</spirit:range>
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH&apos;)) - 1) - 0 + 1">32</spirit:width>
<spirit:usage>register</spirit:usage>
</spirit:addressBlock>
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_verilogsynthesis</spirit:name>
<spirit:displayName>Verilog Synthesis</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>ddr3_test_monitor_axi_v1_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>02a2ca45</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
<spirit:displayName>Verilog Simulation</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>ddr3_test_monitor_axi_v1_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>02a2ca45</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_softwaredriver</spirit:name>
<spirit:displayName>Software Driver</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>533b7796</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>080b65eb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>bd_tcl</spirit:name>
<spirit:displayName>Block Diagram</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>bd_tcl_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>45a2f450</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>correct_read_data_counter</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">63</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>wrong_read_data_counter</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">63</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>time_counter</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">63</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>injected_faults_counter</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_aclk</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_aresetn</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_awaddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH&apos;)) - 1)">6</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_awprot</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_awvalid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_awready</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_wdata</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_wstrb</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH&apos;)) / 8) - 1)">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_wvalid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_wready</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_bresp</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_bvalid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_bready</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_araddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH&apos;)) - 1)">6</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_arprot</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_arvalid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_arready</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_rdata</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_rresp</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_rvalid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s00_axi_rready</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI data bus</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="3" spirit:rangeType="long">32</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI address bus</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">7</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_6fc15197</spirit:name>
<spirit:enumeration>32</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_list_74b5137e</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/ddr3_test_monitor_axi_v1_0_S00_AXI.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ddr3_test_monitor_axi_v1_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_e4de66a6</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/ddr3_test_monitor_axi_v1_0_S00_AXI.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ddr3_test_monitor_axi_v1_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.mdd</spirit:name>
<spirit:userFileType>mdd</spirit:userFileType>
<spirit:userFileType>driver_mdd</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>driver_tcl</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/Makefile</spirit:name>
<spirit:userFileType>driver_src</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.h</spirit:name>
<spirit:fileType>cSource</spirit:fileType>
<spirit:userFileType>driver_src</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.c</spirit:name>
<spirit:fileType>cSource</spirit:fileType>
<spirit:userFileType>driver_src</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi_selftest.c</spirit:name>
<spirit:fileType>cSource</spirit:fileType>
<spirit:userFileType>driver_src</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xgui/ddr3_test_monitor_axi_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_080b65eb</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>bd_tcl_view_fileset</spirit:name>
<spirit:file>
<spirit:name>bd/bd.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>monitors ddr3 test results</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI data bus</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="3">32</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_DATA_WIDTH">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI address bus</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">7</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_ADDR_WIDTH">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S00_AXI_BASEADDR</spirit:name>
<spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
<spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ddr3_test_monitor_axi_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Pre-Production">kintex7</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>ddr3_test_monitor_axi_v1.0</xilinx:displayName>
<xilinx:coreRevision>9</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-02-09T12:59:49Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="2149db2e"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="0c04c4c2"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f7195f90"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="9e6f557d"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a0a6f17f"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="07777575"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>

10
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.mdd Normal file
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@ -0,0 +1,10 @@
OPTION psf_version = 2.1;
BEGIN DRIVER ddr3_test_monitor_axi
OPTION supported_peripherals = (ddr3_test_monitor_axi);
OPTION copyfiles = all;
OPTION VERSION = 1.0;
OPTION NAME = ddr3_test_monitor_axi;
END DRIVER

5
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.tcl Normal file
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@ -0,0 +1,5 @@
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "ddr3_test_monitor_axi" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
}

26
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/src/Makefile Normal file
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@ -0,0 +1,26 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling ddr3_test_monitor_axi..."
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

6
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.c Normal file
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@ -0,0 +1,6 @@
/***************************** Include Files *******************************/
#include "ddr3_test_monitor_axi.h"
/************************** Function Definitions ***************************/

107
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.h Normal file
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#ifndef DDR3_TEST_MONITOR_AXI_H
#define DDR3_TEST_MONITOR_AXI_H
/****************** Include Files ********************/
#include "xil_types.h"
#include "xstatus.h"
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG0_OFFSET 0
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG1_OFFSET 4
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG2_OFFSET 8
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG3_OFFSET 12
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG4_OFFSET 16
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG5_OFFSET 20
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG6_OFFSET 24
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG7_OFFSET 28
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG8_OFFSET 32
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG9_OFFSET 36
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG10_OFFSET 40
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG11_OFFSET 44
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG12_OFFSET 48
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG13_OFFSET 52
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG14_OFFSET 56
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG15_OFFSET 60
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG16_OFFSET 64
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG17_OFFSET 68
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG18_OFFSET 72
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG19_OFFSET 76
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG20_OFFSET 80
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG21_OFFSET 84
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG22_OFFSET 88
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG23_OFFSET 92
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG24_OFFSET 96
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG25_OFFSET 100
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG26_OFFSET 104
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG27_OFFSET 108
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG28_OFFSET 112
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG29_OFFSET 116
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG30_OFFSET 120
#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG31_OFFSET 124
/**************************** Type Definitions *****************************/
/**
*
* Write a value to a DDR3_TEST_MONITOR_AXI register. A 32 bit write is performed.
* If the component is implemented in a smaller width, only the least
* significant data is written.
*
* @param BaseAddress is the base address of the DDR3_TEST_MONITOR_AXIdevice.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note
* C-style signature:
* void DDR3_TEST_MONITOR_AXI_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
*
*/
#define DDR3_TEST_MONITOR_AXI_mWriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/**
*
* Read a value from a DDR3_TEST_MONITOR_AXI register. A 32 bit read is performed.
* If the component is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the DDR3_TEST_MONITOR_AXI device.
* @param RegOffset is the register offset from the base to write to.
*
* @return Data is the data from the register.
*
* @note
* C-style signature:
* u32 DDR3_TEST_MONITOR_AXI_mReadReg(u32 BaseAddress, unsigned RegOffset)
*
*/
#define DDR3_TEST_MONITOR_AXI_mReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ****************************/
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the DDR3_TEST_MONITOR_AXI instance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.
*
*/
XStatus DDR3_TEST_MONITOR_AXI_Reg_SelfTest(void * baseaddr_p);
#endif // DDR3_TEST_MONITOR_AXI_H

60
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi_selftest.c Normal file
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@ -0,0 +1,60 @@
/***************************** Include Files *******************************/
#include "ddr3_test_monitor_axi.h"
#include "xparameters.h"
#include "stdio.h"
#include "xil_io.h"
/************************** Constant Definitions ***************************/
#define READ_WRITE_MUL_FACTOR 0x10
/************************** Function Definitions ***************************/
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the DDR3_TEST_MONITOR_AXIinstance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.
*
*/
XStatus DDR3_TEST_MONITOR_AXI_Reg_SelfTest(void * baseaddr_p)
{
u32 baseaddr;
int write_loop_index;
int read_loop_index;
int Index;
baseaddr = (u32) baseaddr_p;
xil_printf("******************************\n\r");
xil_printf("* User Peripheral Self Test\n\r");
xil_printf("******************************\n\n\r");
/*
* Write to user logic slave module register(s) and read back
*/
xil_printf("User logic slave module test...\n\r");
for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
DDR3_TEST_MONITOR_AXI_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
if ( DDR3_TEST_MONITOR_AXI_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
return XST_FAILURE;
}
xil_printf(" - slave register write/read passed\n\n\r");
return XST_SUCCESS;
}

197
example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/example_designs/bfm_design/ddr3_test_monitor_axi_v1_0_tb.sv Normal file
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@ -0,0 +1,197 @@
`timescale 1ns / 1ps
`include "ddr3_test_monitor_axi_v1_0_tb_include.svh"
import axi_vip_pkg::*;
import ddr3_test_monitor_axi_v1_0_bfm_1_master_0_0_pkg::*;
module ddr3_test_monitor_axi_v1_0_tb();
xil_axi_uint error_cnt = 0;
xil_axi_uint comparison_cnt = 0;
axi_transaction wr_transaction;
axi_transaction rd_transaction;
axi_monitor_transaction mst_monitor_transaction;
axi_monitor_transaction master_moniter_transaction_queue[$];
xil_axi_uint master_moniter_transaction_queue_size =0;
axi_monitor_transaction mst_scb_transaction;
axi_monitor_transaction passthrough_monitor_transaction;
axi_monitor_transaction passthrough_master_moniter_transaction_queue[$];
xil_axi_uint passthrough_master_moniter_transaction_queue_size =0;
axi_monitor_transaction passthrough_mst_scb_transaction;
axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$];
xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0;
axi_monitor_transaction passthrough_slv_scb_transaction;
axi_monitor_transaction slv_monitor_transaction;
axi_monitor_transaction slave_moniter_transaction_queue[$];
xil_axi_uint slave_moniter_transaction_queue_size =0;
axi_monitor_transaction slv_scb_transaction;
xil_axi_uint mst_agent_verbosity = 0;
xil_axi_uint slv_agent_verbosity = 0;
xil_axi_uint passthrough_agent_verbosity = 0;
bit clock;
bit reset;
integer result_slave;
bit [31:0] S00_AXI_test_data[3:0];
localparam LC_AXI_BURST_LENGTH = 8;
localparam LC_AXI_DATA_WIDTH = 32;
task automatic COMPARE_DATA;
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected;
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave = 0; $stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.", " expected = 0x%h",expected, " actual = 0x%h",actual);
result_slave = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
" expected = 0x%h",expected, " actual = 0x%h",actual);
end
end
endtask
integer i;
integer j;
xil_axi_uint trans_cnt_before_switch = 48;
xil_axi_uint passthrough_cmd_switch_cnt = 0;
event passthrough_mastermode_start_event;
event passthrough_mastermode_end_event;
event passthrough_slavemode_end_event;
xil_axi_uint mtestID;
xil_axi_ulong mtestADDR;
xil_axi_len_t mtestBurstLength;
xil_axi_size_t mtestDataSize;
xil_axi_burst_t mtestBurstType;
xil_axi_lock_t mtestLOCK;
xil_axi_cache_t mtestCacheType = 0;
xil_axi_prot_t mtestProtectionType = 3'b000;
xil_axi_region_t mtestRegion = 4'b000;
xil_axi_qos_t mtestQOS = 4'b000;
xil_axi_data_beat dbeat;
xil_axi_data_beat [255:0] mtestWUSER;
xil_axi_data_beat mtestAWUSER = 'h0;
xil_axi_data_beat mtestARUSER = 0;
xil_axi_data_beat [255:0] mtestRUSER;
xil_axi_uint mtestBUSER = 0;
xil_axi_resp_t mtestBresp;
xil_axi_resp_t[255:0] mtestRresp;
bit [63:0] mtestWDataL;
bit [63:0] mtestRDataL;
axi_transaction pss_wr_transaction;
axi_transaction pss_rd_transaction;
axi_transaction reactive_transaction;
axi_transaction rd_payload_transaction;
axi_transaction wr_rand;
axi_transaction rd_rand;
axi_transaction wr_reactive;
axi_transaction rd_reactive;
axi_transaction wr_reactive2;
axi_transaction rd_reactive2;
axi_ready_gen bready_gen;
axi_ready_gen rready_gen;
axi_ready_gen awready_gen;
axi_ready_gen wready_gen;
axi_ready_gen arready_gen;
axi_ready_gen bready_gen2;
axi_ready_gen rready_gen2;
axi_ready_gen awready_gen2;
axi_ready_gen wready_gen2;
axi_ready_gen arready_gen2;
xil_axi_payload_byte data_mem[xil_axi_ulong];
ddr3_test_monitor_axi_v1_0_bfm_1_master_0_0_mst_t mst_agent_0;
`BD_WRAPPER DUT(
.ARESETN(reset),
.ACLK(clock)
);
initial begin
mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms
mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE);
mst_agent_0.set_agent_tag("Master VIP");
mst_agent_0.set_verbosity(mst_agent_verbosity);
mst_agent_0.start_master();
$timeformat (-12, 1, " ps", 1);
end
initial begin
reset <= 1'b0;
#200ns;
reset <= 1'b1;
repeat (5) @(negedge clock);
end
always #5 clock <= ~clock;
initial begin
S_AXI_TEST ( );
#1ns;
$finish;
end
task automatic S_AXI_TEST;
begin
#1;
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method starts");
mtestID = 0;
mtestADDR = 64'h00000000;
mtestBurstLength = 0;
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
mtestCacheType = 0;
mtestProtectionType = 0;
mtestRegion = 0;
mtestQOS = 0;
result_slave = 1;
mtestWDataL[31:0] = 32'h00000001;
for(int i = 0; i < 4;i++) begin
S00_AXI_test_data[i] <= mtestWDataL[31:0];
mst_agent_0.AXI4LITE_WRITE_BURST(
mtestADDR,
mtestProtectionType,
mtestWDataL,
mtestBresp
);
mtestWDataL[31:0] = mtestWDataL[31:0] + 1;
mtestADDR = mtestADDR + 64'h4;
end
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method completes");
$display("Sequential read transfers example similar to AXI BFM READ_BURST method starts");
mtestID = 0;
mtestADDR = 64'h00000000;
mtestBurstLength = 0;
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
mtestCacheType = 0;
mtestProtectionType = 0;
mtestRegion = 0;
mtestQOS = 0;
for(int i = 0; i < 4;i++) begin
mst_agent_0.AXI4LITE_READ_BURST(
mtestADDR,
mtestProtectionType,
mtestRDataL,
mtestRresp
);
mtestADDR = mtestADDR + 64'h4;
COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL);
end
$display("Sequential read transfers example similar to AXI BFM READ_BURST method completes");
$display("Sequential read transfers example similar to AXI VIP READ_BURST method completes");
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
endmodule

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proc create_ipi_design { offsetfile design_name } {
create_bd_design $design_name
open_bd_design $design_name
# Create Clock and Reset Ports
set ACLK [ create_bd_port -dir I -type clk ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
# Create instance: ddr3_test_monitor_axi_0, and set properties
set ddr3_test_monitor_axi_0 [ create_bd_cell -type ip -vlnv user.org:user:ddr3_test_monitor_axi:1.0 ddr3_test_monitor_axi_0]
# Create instance: master_0, and set properties
set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip master_0]
set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
# Create interface connections
connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins ddr3_test_monitor_axi_0/S00_AXI]
# Create port connections
connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins ddr3_test_monitor_axi_0/S00_AXI_ACLK]
connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins ddr3_test_monitor_axi_0/S00_AXI_ARESETN]
set_property target_simulator XSim [current_project]
set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
# Auto assign address
assign_bd_address
# Copy all address to interface_address.vh file
set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
upvar 1 $offsetfile offset_file
set offset_file "${bd_path}/ddr3_test_monitor_axi_v1_0_tb_include.svh"
set fp [open $offset_file "w"]
puts $fp "`ifndef ddr3_test_monitor_axi_v1_0_tb_include_vh_"
puts $fp "`define ddr3_test_monitor_axi_v1_0_tb_include_vh_\n"
puts $fp "//Configuration current bd names"
puts $fp "`define BD_NAME ${design_name}"
puts $fp "`define BD_INST_NAME ${design_name}_i"
puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
puts $fp "//Configuration address parameters"
puts $fp "`endif"
close $fp
}
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:ddr3_test_monitor_axi:1.0]]]]
set test_bench_file ${ip_path}/example_designs/bfm_design/ddr3_test_monitor_axi_v1_0_tb.sv
set interface_address_vh_file ""
# Set IP Repository and Update IP Catalogue
set repo_paths [get_property ip_repo_paths [current_fileset]]
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
update_ip_catalog
}
set design_name ""
set all_bd {}
set all_bd_files [get_files *.bd -quiet]
foreach file $all_bd_files {
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
lappend all_bd $bd_name
}
for { set i 1 } { 1 } { incr i } {
set design_name "ddr3_test_monitor_axi_v1_0_bfm_${i}"
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
break
}
}
create_ipi_design interface_address_vh_file ${design_name}
validate_bd_design
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
import_files -force -norecurse $wrapper_file
set_property SOURCE_SET sources_1 [get_filesets sim_1]
import_files -fileset sim_1 -norecurse -force $test_bench_file
remove_files -quiet -fileset sim_1 ddr3_test_monitor_axi_v1_0_tb_include.vh
import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
set_property top ddr3_test_monitor_axi_v1_0_tb [get_filesets sim_1]
set_property top_lib {} [get_filesets sim_1]
set_property top_file {} [get_filesets sim_1]
launch_simulation -simset sim_1 -mode behavioral

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example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/example_designs/debug_hw_design/ddr3_test_monitor_axi_v1_0_hw_test.tcl Normal file
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# Runtime Tcl commands to interact with - ddr3_test_monitor_axi_v1_0
# Sourcing design address info tcl
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
source ${bd_path}/ddr3_test_monitor_axi_v1_0_include.tcl
# jtag axi master interface hardware name, change as per your design.
set jtag_axi_master hw_axi_1
set ec 0
# hw test script
# Delete all previous axis transactions
if { [llength [get_hw_axi_txns -quiet]] } {
delete_hw_axi_txn [get_hw_axi_txns -quiet]
}
# Test all lite slaves.
set wdata_1 abcd1234
# Test: S00_AXI
# Create a write transaction at s00_axi_addr address
create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
# Create a read transaction at s00_axi_addr address
create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
# Initiate transactions
run_hw_axi r_s00_axi_addr
run_hw_axi w_s00_axi_addr
run_hw_axi r_s00_axi_addr
set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
# Compare read data
if { $rdata_tmp == $wdata_1 } {
puts "Data comparison test pass for - S00_AXI"
} else {
puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
inc ec
}
# Check error flag
if { $ec == 0 } {
puts "PTGEN_TEST: PASSED!"
} else {
puts "PTGEN_TEST: FAILED!"
}

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proc create_ipi_design { offsetfile design_name } {
create_bd_design $design_name
open_bd_design $design_name
# Create and configure Clock/Reset
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
#Constraints will be provided manually while pin planning.
create_bd_port -dir I -type rst reset_rtl
set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
set external_reset_port reset_rtl
create_bd_port -dir I -type clk clock_rtl
connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
set external_clock_port clock_rtl
#Avoid IPI DRC, make clock port synchronous to reset
if { $external_clock_port ne "" && $external_reset_port ne "" } {
set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
}
# Connect other sys_reset pins
connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
# Create instance: ddr3_test_monitor_axi_0, and set properties
set ddr3_test_monitor_axi_0 [ create_bd_cell -type ip -vlnv user.org:user:ddr3_test_monitor_axi:1.0 ddr3_test_monitor_axi_0 ]
# Create instance: jtag_axi_0, and set properties
set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Create instance: axi_peri_interconnect, and set properties
set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Connect all clock & reset of ddr3_test_monitor_axi_0 slave interfaces..
connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins ddr3_test_monitor_axi_0/S00_AXI]
connect_bd_net [get_bd_pins ddr3_test_monitor_axi_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins ddr3_test_monitor_axi_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Auto assign address
assign_bd_address
# Copy all address to ddr3_test_monitor_axi_v1_0_include.tcl file
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
upvar 1 $offsetfile offset_file
set offset_file "${bd_path}/ddr3_test_monitor_axi_v1_0_include.tcl"
set fp [open $offset_file "w"]
puts $fp "# Configuration address parameters"
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_ddr3_test_monitor_axi_0_S00_AXI_* ]]
puts $fp "set s00_axi_addr ${offset}"
close $fp
}
# Set IP Repository and Update IP Catalogue
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:ddr3_test_monitor_axi:1.0]]]]
set hw_test_file ${ip_path}/example_designs/debug_hw_design/ddr3_test_monitor_axi_v1_0_hw_test.tcl
set repo_paths [get_property ip_repo_paths [current_fileset]]
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
update_ip_catalog
}
set design_name ""
set all_bd {}
set all_bd_files [get_files *.bd -quiet]
foreach file $all_bd_files {
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
lappend all_bd $bd_name
}
for { set i 1 } { 1 } { incr i } {
set design_name "ddr3_test_monitor_axi_v1_0_hw_${i}"
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
break
}
}
set intf_address_include_file ""
create_ipi_design intf_address_include_file ${design_name}
save_bd_design
validate_bd_design
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
import_files -force -norecurse $wrapper_file
puts "-------------------------------------------------------------------------------------------------"
puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
puts " please perform following steps to test design in targeted board."
puts "1. Generate bitstream"
puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
puts "3. Download generated bitstream"
puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
puts " : source -notrace ${hw_test_file}"
puts "-------------------------------------------------------------------------------------------------"

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`timescale 1 ns / 1 ps
module ddr3_test_monitor_axi_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 7
)
(
// Users to add ports here
input wire[63:0] correct_read_data_counter, // address x0 = [31:0], x1 = [63:32]
input wire[63:0] wrong_read_data_counter, // address x2 = [31:0], x3 = [63:32]
input wire[63:0] time_counter, // address x4 = [31:0], x5 = [63:32]
input wire[31:0] injected_faults_counter,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
ddr3_test_monitor_axi_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) ddr3_test_monitor_axi_v1_0_S00_AXI_inst (
.correct_read_data_counter(correct_read_data_counter),
.wrong_read_data_counter(wrong_read_data_counter),
.timer_counter(time_counter),
.injected_faults_counter(injected_faults_counter),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule

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`timescale 1 ns / 1 ps
module ddr3_test_monitor_axi_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 7
)
(
// Users to add ports here
input wire[63:0] correct_read_data_counter,
input wire[63:0] wrong_read_data_counter,
input wire[63:0] timer_counter,
input wire[31:0] injected_faults_counter,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 4;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 32
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
slv_reg4 <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
slv_reg8 <= 0;
slv_reg9 <= 0;
slv_reg10 <= 0;
slv_reg11 <= 0;
slv_reg12 <= 0;
slv_reg13 <= 0;
slv_reg14 <= 0;
slv_reg15 <= 0;
slv_reg16 <= 0;
slv_reg17 <= 0;
slv_reg18 <= 0;
slv_reg19 <= 0;
slv_reg20 <= 0;
slv_reg21 <= 0;
slv_reg22 <= 0;
slv_reg23 <= 0;
slv_reg24 <= 0;
slv_reg25 <= 0;
slv_reg26 <= 0;
slv_reg27 <= 0;
slv_reg28 <= 0;
slv_reg29 <= 0;
slv_reg30 <= 0;
slv_reg31 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
5'h00:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h01:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h02:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h03:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h04:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 4
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h05:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 5
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h06:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 6
slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h07:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 7
slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h08:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 8
slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h09:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 9
slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0A:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 10
slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0B:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 11
slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0C:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 12
slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0D:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 13
slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0E:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 14
slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0F:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 15
slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h10:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 16
slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h11:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 17
slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h12:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 18
slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h13:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 19
slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h14:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 20
slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h15:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 21
slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h16:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 22
slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h17:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 23
slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h18:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 24
slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h19:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 25
slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1A:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 26
slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1B:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 27
slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1C:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 28
slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1D:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 29
slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1E:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 30
slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1F:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 31
slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
5'h00 : reg_data_out <= correct_read_data_counter[31:0];
5'h01 : reg_data_out <= correct_read_data_counter[63:32];
5'h02 : reg_data_out <= wrong_read_data_counter[31:0];
5'h03 : reg_data_out <= wrong_read_data_counter[63:32];
5'h04 : reg_data_out <= timer_counter[31:0];
5'h05 : reg_data_out <= timer_counter[63:32];
5'h06 : reg_data_out <= injected_faults_counter[31:0];
5'h07 : reg_data_out <= slv_reg7;
5'h08 : reg_data_out <= slv_reg8;
5'h09 : reg_data_out <= slv_reg9;
5'h0A : reg_data_out <= slv_reg10;
5'h0B : reg_data_out <= slv_reg11;
5'h0C : reg_data_out <= slv_reg12;
5'h0D : reg_data_out <= slv_reg13;
5'h0E : reg_data_out <= slv_reg14;
5'h0F : reg_data_out <= slv_reg15;
5'h10 : reg_data_out <= slv_reg16;
5'h11 : reg_data_out <= slv_reg17;
5'h12 : reg_data_out <= slv_reg18;
5'h13 : reg_data_out <= slv_reg19;
5'h14 : reg_data_out <= slv_reg20;
5'h15 : reg_data_out <= slv_reg21;
5'h16 : reg_data_out <= slv_reg22;
5'h17 : reg_data_out <= slv_reg23;
5'h18 : reg_data_out <= slv_reg24;
5'h19 : reg_data_out <= slv_reg25;
5'h1A : reg_data_out <= slv_reg26;
5'h1B : reg_data_out <= slv_reg27;
5'h1C : reg_data_out <= slv_reg28;
5'h1D : reg_data_out <= slv_reg29;
5'h1E : reg_data_out <= slv_reg30;
5'h1F : reg_data_out <= slv_reg31;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
// User logic ends
endmodule

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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
}
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to validate C_S00_AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to validate C_S00_AXI_BASEADDR
return true
}
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to validate C_S00_AXI_HIGHADDR
return true
}
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
}

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////////////////////////////////////////////////////////////////////////////////
//
// Filename: ddr3_test_top.v
// Project: Top level module instantiating the ddr3 test and UberDDR3.
//
// Engineer: Angelo C. Jacobo
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2023-2025 Angelo Jacobo
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module enclustra_ddr3_test
(
input wire i_clk200_p, i_clk200_n,
input wire i_rst_n,
// DDR3 I/O Interface
output wire ddr3_clk_p, ddr3_clk_n,
output wire ddr3_reset_n,
output wire ddr3_cke,
output wire ddr3_cs_n,
output wire ddr3_ras_n,
output wire ddr3_cas_n,
output wire ddr3_we_n,
output wire[15-1:0] ddr3_addr,
output wire[3-1:0] ddr3_ba,
inout wire[64-1:0] ddr3_dq,
inout wire[8-1:0] ddr3_dqs_p, ddr3_dqs_n,
output wire[8-1:0] ddr3_dm,
output wire ddr3_odt,
// UART line
input wire rx,
output wire tx,
//Debug LEDs
output wire[3:0] led,
// Button for fault injection
input wire btn
);
localparam CONTROLLER_CLK_PERIOD = 5_000, // ps, clock period of the controller interface
DDR3_CLK_PERIOD = 1_250, // ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
ROW_BITS = 15, // Width of row address
COL_BITS = 10, // Width of column address
BA_BITS = 3, // Width of bank address
BYTE_LANES = 8, // Number of DDR3 modules to be controlled
AUX_WIDTH = 16, // Width of aux line (must be >= 4)
BIST_MODE = 0; // Don't perform BIST, go straight to external DDR3 test
parameter MICRON_SIM = 0, // Enable faster simulation for Micron DDR3 model
ODELAY_SUPPORTED = 1, // Set to 1 when ODELAYE2 is supported
DATA_MASK = 1; // enable test on datamask
localparam WB_ADDR_BITS = ROW_BITS + COL_BITS + BA_BITS - 3,
WB_DATA_BITS = 8*BYTE_LANES*8,
WB_SEL_BITS = WB_DATA_BITS / 8;
wire sys_clk_200MHz;
wire i_controller_clk, i_ddr3_clk, i_ref_clk,i_clk100;
wire clk_locked;
wire timer_pulse, wrong_data_counter_non_zero;
// Wishbone output signals
wire o_wb_cyc; // Bus cycle active (1 = normal operation, 0 = cancel all ongoing transactions)
wire o_wb_stb; // Request a transfer
wire o_wb_we; // Write-enable (1 = write, 0 = read)
wire [WB_ADDR_BITS - 1:0] o_wb_addr; // Burst-addressable {row, bank, col}
wire [WB_DATA_BITS - 1:0] o_wb_data; // Write data (depends on controller width)
wire [WB_SEL_BITS - 1:0] o_wb_sel; // Byte strobe for write (1 = write the byte)
wire [AUX_WIDTH - 1:0] o_aux; // AXI-interface compatibility (given upon strobe)
// Wishbone input signals
wire i_wb_stall; // 1 = Busy, cannot accept requests
wire i_wb_ack; // 1 = Read/write request completed
wire [WB_DATA_BITS - 1:0] i_wb_data; // Read data
wire [AUX_WIDTH - 1:0] i_aux; // AXI-interface compatibility (given upon strobe)
(* mark_debug = "true" *) wire calib_complete;
assign led[0] = !calib_complete; //light up if at DONE_CALIBRATE
assign led[1] = !wrong_data_counter_non_zero; //light up if at there is wrong data
assign led[2] = !timer_pulse; //light up at timer pulse
assign led[3] = !timer_pulse; //light up at timer pulse
IBUFDS sys_clk_ibufgds
(
.O(sys_clk_200MHz),
.I(i_clk200_p),
.IB(i_clk200_n)
);
clk_wiz_0 clk_wiz_inst
(
// Clock out ports
.controller_clk(i_controller_clk),
.ddr3_clk(i_ddr3_clk),
.ref200_clk(i_ref_clk),
.clk100(i_clk100),
// Status and control signals
.reset(!i_rst_n),
.locked(clk_locked),
// Clock in ports
.clk_in1(sys_clk_200MHz)
);
// DDR3 Controller
ddr3_top #(
.CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.ROW_BITS(ROW_BITS), //width of row address
.COL_BITS(COL_BITS), //width of column address
.BA_BITS(BA_BITS), //width of bank address
.BYTE_LANES(BYTE_LANES), //number of DDR3 modules to be controlled
.AUX_WIDTH(AUX_WIDTH), //width of aux line (must be >= 4)
.MICRON_SIM(MICRON_SIM), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
.ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 when ODELAYE2 is supported
.BIST_MODE(BIST_MODE)
) ddr3_top_inst
(
//clock and reset
.i_controller_clk(i_controller_clk),
.i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD
.i_ref_clk(i_ref_clk),
.i_ddr3_clk_90(),
.i_rst_n(i_rst_n && clk_locked),
// Wishbone inputs
.i_wb_cyc(o_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
.i_wb_stb(o_wb_stb), //request a transfer
.i_wb_we(o_wb_we), //write-enable (1 = write, 0 = read)
.i_wb_addr(o_wb_addr), //burst-addressable {row,bank,col}
.i_wb_data(o_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
.i_wb_sel(o_wb_sel), //byte strobe for write (1 = write the byte)
.i_aux(o_aux), //for AXI-interface compatibility (given upon strobe)
// Wishbone outputs
.o_wb_stall(i_wb_stall), //1 = busy, cannot accept requests
.o_wb_ack(i_wb_ack), //1 = read/write request has completed
.o_wb_data(i_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
.o_aux(i_aux),
// PHY Interface (to be added later)
// DDR3 I/O Interface
.o_ddr3_clk_p(ddr3_clk_p),
.o_ddr3_clk_n(ddr3_clk_n),
.o_ddr3_reset_n(ddr3_reset_n),
.o_ddr3_cke(ddr3_cke), // CKE
.o_ddr3_cs_n(ddr3_cs_n), // chip select signal (controls rank 1 only)
.o_ddr3_ras_n(ddr3_ras_n), // RAS#
.o_ddr3_cas_n(ddr3_cas_n), // CAS#
.o_ddr3_we_n(ddr3_we_n), // WE#
.o_ddr3_addr(ddr3_addr),
.o_ddr3_ba_addr(ddr3_ba),
.io_ddr3_dq(ddr3_dq),
.io_ddr3_dqs(ddr3_dqs_p),
.io_ddr3_dqs_n(ddr3_dqs_n),
.o_ddr3_dm(ddr3_dm),
.o_ddr3_odt(ddr3_odt), // on-die termination
// debug
.o_calib_complete(calib_complete)
);
ddr3_test #(
.WB_ADDR_BITS(WB_ADDR_BITS),
.WB_DATA_BITS(WB_DATA_BITS),
.WB_SEL_BITS(WB_SEL_BITS),
.AUX_WIDTH(AUX_WIDTH),
.DATA_MASK(DATA_MASK),
.MICRON_SIM(MICRON_SIM)
) ddr3_test_inst
(
.i_clk(i_controller_clk),
.i_clk100(i_clk100),
.i_rst_n(i_rst_n),
//
// Wishbone inputs
.o_wb_cyc(o_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
.o_wb_stb(o_wb_stb), //request a transfer
.o_wb_we(o_wb_we), //write-enable (1 = write, 0 = read)
.o_wb_addr(o_wb_addr), //burst-addressable {row,bank,col}
.o_wb_data(o_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
.o_wb_sel(o_wb_sel), //byte strobe for write (1 = write the byte)
.o_aux(o_aux), //for AXI-interface compatibility (given upon strobe)
//
// Wishbone outputs
.i_wb_stall(i_wb_stall), //1 = busy, cannot accept requests
.i_wb_ack(i_wb_ack), //1 = read/write request has completed
.i_wb_err(0), //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
.i_wb_data(i_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
.i_aux(i_aux), //for AXI-interface compatibility (given upon strobe)
//
// Done Calibration pin
.i_calib_complete(calib_complete),
//
// UART line
.rx(rx),
.tx(tx),
// Button for fault injection
.btn(!btn),
// Debug
.timer_pulse(timer_pulse),
.wrong_data_counter_non_zero(wrong_data_counter_non_zero)
);
endmodule

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////////////////////////////////////////////////////////////////////////////////
//
// Filename: ddr3_test_top.v
// Project: Testbench for ddr3_test_top.v
//
// Engineer: Angelo C. Jacobo
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2023-2025 Angelo Jacobo
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module ddr3_test_top_tb;
// PHY Interface to DDR3 Device
wire[1:0] ddr3_cke; // CKE
wire[1:0] ddr3_cs_n; // chip select signal
wire[1:0] ddr3_odt; // on-die termination
wire ddr3_ras_n; // RAS#
wire ddr3_cas_n; // CAS#
wire ddr3_we_n; // WE#
wire ddr3_reset_n;
wire[$bits(DUT.ddr3_addr)-1:0] ddr3_addr;
wire[$bits(DUT.ddr3_ba)-1:0] ddr3_ba;
wire[$bits(DUT.ddr3_dm)-1:0] ddr3_dm;
wire[$bits(DUT.ddr3_dq)-1:0] ddr3_dq;
wire[$bits(DUT.ddr3_dqs_p)-1:0] ddr3_dqs_p;
wire[$bits(DUT.ddr3_dqs_n)-1:0] ddr3_dqs_n;
wire[1:0] ddr3_clk_p, ddr3_clk_n;
// clocks and reset
reg i_clk200_p;
reg i_rst_n;
initial begin
i_clk200_p = 0;
i_rst_n = 0;
#1000;
i_rst_n = 1;
end
always #2_500 i_clk200_p = !i_clk200_p; // 200MHz
enclustra_ddr3_test #(
.MICRON_SIM(1),
.ODELAY_SUPPORTED(1),
.DATA_MASK(1)
)
DUT (
.i_clk200_p(i_clk200_p),
.i_clk200_n(!i_clk200_p),
.i_rst_n(i_rst_n),
// DDR3 I/O Interface
.ddr3_clk_p(ddr3_clk_p),
.ddr3_clk_n(ddr3_clk_n),
.ddr3_reset_n(ddr3_reset_n),
.ddr3_cke(ddr3_cke),
.ddr3_cs_n(ddr3_cs_n),
.ddr3_ras_n(ddr3_ras_n),
.ddr3_cas_n(ddr3_cas_n),
.ddr3_we_n(ddr3_we_n),
.ddr3_addr(ddr3_addr),
.ddr3_ba(ddr3_ba),
.ddr3_dq(ddr3_dq),
.ddr3_dqs_p(ddr3_dqs_p),
.ddr3_dqs_n(ddr3_dqs_n),
.ddr3_dm(ddr3_dm),
.ddr3_odt(ddr3_odt),
// UART line
.rx(0),
.tx(),
// Debug LEDs
.led()
);
// DDR3 Device
ddr3_module ddr3_module(
.reset_n(ddr3_reset_n),
.ck(ddr3_clk_p), //[1:0]
.ck_n(ddr3_clk_n), //[1:0]
.cke(ddr3_cke), //[1:0]
.s_n(ddr3_cs_n), //[1:0]
.ras_n(ddr3_ras_n),
.cas_n(ddr3_cas_n),
.we_n(ddr3_we_n),
.ba(ddr3_ba),
.addr({0,ddr3_addr}),
.odt(ddr3_odt), //[1:0]
.dqs({ddr3_dm[0], ddr3_dm,ddr3_dm[0],ddr3_dqs_p}), //ddr3_module uses last 8 MSB [16:9] as datamask
.dqs_n(ddr3_dqs_n),
.dq(ddr3_dq)
);
assign ddr3_cke[1]=0,
ddr3_cs_n[1]=1,
ddr3_odt[1]=0,
ddr3_clk_p[1]=0,
ddr3_clk_n[1]=0;
endmodule

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# IO constraints
################################################################################
# cpu_reset_n:0
set_property LOC C22 [get_ports {i_rst_n}]
set_property IOSTANDARD LVCMOS18 [get_ports {i_rst_n}]
set_property PACKAGE_PIN C22 [get_ports i_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports i_rst_n]
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports btn]
# clk200:0.p
set_property LOC AB11 [get_ports {i_clk200_p}]
set_property IOSTANDARD LVDS [get_ports {i_clk200_p}]
set_property IOSTANDARD LVDS [get_ports i_clk200_p]
# clk200:0.n
set_property LOC AC11 [get_ports {i_clk200_n}]
set_property IOSTANDARD LVDS [get_ports {i_clk200_n}]
set_property PACKAGE_PIN AB11 [get_ports i_clk200_p]
set_property PACKAGE_PIN AC11 [get_ports i_clk200_n]
set_property IOSTANDARD LVDS [get_ports i_clk200_n]
# serial:0.tx
set_property LOC A20 [get_ports {tx}]
set_property IOSTANDARD LVCMOS18 [get_ports {tx}]
set_property PACKAGE_PIN A20 [get_ports tx]
set_property IOSTANDARD LVCMOS18 [get_ports tx]
# serial:0.rx
set_property LOC B20 [get_ports {rx}]
set_property IOSTANDARD LVCMOS18 [get_ports {rx}]
set_property PACKAGE_PIN B20 [get_ports rx]
set_property IOSTANDARD LVCMOS18 [get_ports rx]
# ddram:0.a
set_property LOC AE11 [get_ports {ddr3_addr[0]}]
set_property PACKAGE_PIN AE11 [get_ports {ddr3_addr[0]}]
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
# ddram:0.a
set_property LOC AF9 [get_ports {ddr3_addr[1]}]
set_property PACKAGE_PIN AF9 [get_ports {ddr3_addr[1]}]
set_property SLEW FAST [get_ports {ddr3_addr[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
# ddram:0.a
set_property LOC AD10 [get_ports {ddr3_addr[2]}]
set_property PACKAGE_PIN AD10 [get_ports {ddr3_addr[2]}]
set_property SLEW FAST [get_ports {ddr3_addr[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
# ddram:0.a
set_property LOC AB10 [get_ports {ddr3_addr[3]}]
set_property PACKAGE_PIN AB10 [get_ports {ddr3_addr[3]}]
set_property SLEW FAST [get_ports {ddr3_addr[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
# ddram:0.a
set_property LOC AA9 [get_ports {ddr3_addr[4]}]
set_property PACKAGE_PIN AA9 [get_ports {ddr3_addr[4]}]
set_property SLEW FAST [get_ports {ddr3_addr[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
# ddram:0.a
set_property LOC AB9 [get_ports {ddr3_addr[5]}]
set_property PACKAGE_PIN AB9 [get_ports {ddr3_addr[5]}]
set_property SLEW FAST [get_ports {ddr3_addr[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
# ddram:0.a
set_property LOC AA8 [get_ports {ddr3_addr[6]}]
set_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[6]}]
set_property SLEW FAST [get_ports {ddr3_addr[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
# ddram:0.a
set_property LOC AC8 [get_ports {ddr3_addr[7]}]
set_property PACKAGE_PIN AC8 [get_ports {ddr3_addr[7]}]
set_property SLEW FAST [get_ports {ddr3_addr[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
# ddram:0.a
set_property LOC AA7 [get_ports {ddr3_addr[8]}]
set_property PACKAGE_PIN AA7 [get_ports {ddr3_addr[8]}]
set_property SLEW FAST [get_ports {ddr3_addr[8]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
# ddram:0.a
set_property LOC AE8 [get_ports {ddr3_addr[9]}]
set_property PACKAGE_PIN AE8 [get_ports {ddr3_addr[9]}]
set_property SLEW FAST [get_ports {ddr3_addr[9]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
# ddram:0.a
set_property LOC AF10 [get_ports {ddr3_addr[10]}]
set_property PACKAGE_PIN AF10 [get_ports {ddr3_addr[10]}]
set_property SLEW FAST [get_ports {ddr3_addr[10]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
# ddram:0.a
set_property LOC AD8 [get_ports {ddr3_addr[11]}]
set_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[11]}]
set_property SLEW FAST [get_ports {ddr3_addr[11]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
# ddram:0.a
set_property LOC AE10 [get_ports {ddr3_addr[12]}]
set_property PACKAGE_PIN AE10 [get_ports {ddr3_addr[12]}]
set_property SLEW FAST [get_ports {ddr3_addr[12]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
# ddram:0.a
set_property LOC AF8 [get_ports {ddr3_addr[13]}]
set_property PACKAGE_PIN AF8 [get_ports {ddr3_addr[13]}]
set_property SLEW FAST [get_ports {ddr3_addr[13]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
# ddram:0.a
set_property LOC AC7 [get_ports {ddr3_addr[14]}]
set_property PACKAGE_PIN AC7 [get_ports {ddr3_addr[14]}]
set_property SLEW FAST [get_ports {ddr3_addr[14]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
# ddram:0.ba
set_property LOC AD11 [get_ports {ddr3_ba[0]}]
set_property PACKAGE_PIN AD11 [get_ports {ddr3_ba[0]}]
set_property SLEW FAST [get_ports {ddr3_ba[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
# ddram:0.ba
set_property LOC AA10 [get_ports {ddr3_ba[1]}]
set_property PACKAGE_PIN AA10 [get_ports {ddr3_ba[1]}]
set_property SLEW FAST [get_ports {ddr3_ba[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
# ddram:0.ba
set_property LOC AF12 [get_ports {ddr3_ba[2]}]
set_property PACKAGE_PIN AF12 [get_ports {ddr3_ba[2]}]
set_property SLEW FAST [get_ports {ddr3_ba[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
# ddram:0.ras_n
set_property LOC AE13 [get_ports {ddr3_ras_n}]
set_property SLEW FAST [get_ports {ddr3_ras_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_ras_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]
set_property PACKAGE_PIN AE13 [get_ports ddr3_ras_n]
set_property SLEW FAST [get_ports ddr3_ras_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_ras_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n]
# ddram:0.cas_n
set_property LOC AE12 [get_ports {ddr3_cas_n}]
set_property SLEW FAST [get_ports {ddr3_cas_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_cas_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]
set_property PACKAGE_PIN AE12 [get_ports ddr3_cas_n]
set_property SLEW FAST [get_ports ddr3_cas_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_cas_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n]
# ddram:0.we_n
set_property LOC AA12 [get_ports {ddr3_we_n}]
set_property SLEW FAST [get_ports {ddr3_we_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_we_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]
set_property PACKAGE_PIN AA12 [get_ports ddr3_we_n]
set_property SLEW FAST [get_ports ddr3_we_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_we_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n]
# ddram:0.cs_n
set_property LOC Y12 [get_ports {ddr3_cs_n}]
set_property SLEW FAST [get_ports {ddr3_cs_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_cs_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n}]
set_property PACKAGE_PIN Y12 [get_ports ddr3_cs_n]
set_property SLEW FAST [get_ports ddr3_cs_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_cs_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_cs_n]
# ddram:0.dm
set_property LOC Y3 [get_ports {ddr3_dm[0]}]
set_property PACKAGE_PIN Y3 [get_ports {ddr3_dm[0]}]
set_property SLEW FAST [get_ports {ddr3_dm[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
# ddram:0.dm
set_property LOC U5 [get_ports {ddr3_dm[1]}]
set_property PACKAGE_PIN U5 [get_ports {ddr3_dm[1]}]
set_property SLEW FAST [get_ports {ddr3_dm[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
# ddram:0.dm
set_property LOC AD4 [get_ports {ddr3_dm[2]}]
set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[2]}]
set_property SLEW FAST [get_ports {ddr3_dm[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
# ddram:0.dm
set_property LOC AC4 [get_ports {ddr3_dm[3]}]
set_property PACKAGE_PIN AC4 [get_ports {ddr3_dm[3]}]
set_property SLEW FAST [get_ports {ddr3_dm[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
# ddram:0.dm
set_property LOC AF19 [get_ports {ddr3_dm[4]}]
set_property PACKAGE_PIN AF19 [get_ports {ddr3_dm[4]}]
set_property SLEW FAST [get_ports {ddr3_dm[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[4]}]
# ddram:0.dm
set_property LOC AC16 [get_ports {ddr3_dm[5]}]
set_property PACKAGE_PIN AC16 [get_ports {ddr3_dm[5]}]
set_property SLEW FAST [get_ports {ddr3_dm[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[5]}]
# ddram:0.dm
set_property LOC AB19 [get_ports {ddr3_dm[6]}]
set_property PACKAGE_PIN AB19 [get_ports {ddr3_dm[6]}]
set_property SLEW FAST [get_ports {ddr3_dm[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[6]}]
# ddram:0.dm
set_property LOC V14 [get_ports {ddr3_dm[7]}]
set_property PACKAGE_PIN V14 [get_ports {ddr3_dm[7]}]
set_property SLEW FAST [get_ports {ddr3_dm[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[7]}]
# ddram:0.dq
set_property LOC AA2 [get_ports {ddr3_dq[0]}]
set_property PACKAGE_PIN AA2 [get_ports {ddr3_dq[0]}]
set_property SLEW FAST [get_ports {ddr3_dq[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
# ddram:0.dq
set_property LOC Y2 [get_ports {ddr3_dq[1]}]
set_property PACKAGE_PIN Y2 [get_ports {ddr3_dq[1]}]
set_property SLEW FAST [get_ports {ddr3_dq[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
# ddram:0.dq
set_property LOC AB2 [get_ports {ddr3_dq[2]}]
set_property PACKAGE_PIN AB2 [get_ports {ddr3_dq[2]}]
set_property SLEW FAST [get_ports {ddr3_dq[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
# ddram:0.dq
set_property LOC V1 [get_ports {ddr3_dq[3]}]
set_property PACKAGE_PIN V1 [get_ports {ddr3_dq[3]}]
set_property SLEW FAST [get_ports {ddr3_dq[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
# ddram:0.dq
set_property LOC Y1 [get_ports {ddr3_dq[4]}]
set_property PACKAGE_PIN Y1 [get_ports {ddr3_dq[4]}]
set_property SLEW FAST [get_ports {ddr3_dq[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
# ddram:0.dq
set_property LOC W1 [get_ports {ddr3_dq[5]}]
set_property PACKAGE_PIN W1 [get_ports {ddr3_dq[5]}]
set_property SLEW FAST [get_ports {ddr3_dq[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
# ddram:0.dq
set_property LOC AC2 [get_ports {ddr3_dq[6]}]
set_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[6]}]
set_property SLEW FAST [get_ports {ddr3_dq[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
# ddram:0.dq
set_property LOC V2 [get_ports {ddr3_dq[7]}]
set_property PACKAGE_PIN V2 [get_ports {ddr3_dq[7]}]
set_property SLEW FAST [get_ports {ddr3_dq[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
# ddram:0.dq
set_property LOC W3 [get_ports {ddr3_dq[8]}]
set_property PACKAGE_PIN W3 [get_ports {ddr3_dq[8]}]
set_property SLEW FAST [get_ports {ddr3_dq[8]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
# ddram:0.dq
set_property LOC V3 [get_ports {ddr3_dq[9]}]
set_property PACKAGE_PIN V3 [get_ports {ddr3_dq[9]}]
set_property SLEW FAST [get_ports {ddr3_dq[9]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
# ddram:0.dq
set_property LOC U1 [get_ports {ddr3_dq[10]}]
set_property PACKAGE_PIN U1 [get_ports {ddr3_dq[10]}]
set_property SLEW FAST [get_ports {ddr3_dq[10]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
# ddram:0.dq
set_property LOC U7 [get_ports {ddr3_dq[11]}]
set_property PACKAGE_PIN U7 [get_ports {ddr3_dq[11]}]
set_property SLEW FAST [get_ports {ddr3_dq[11]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
# ddram:0.dq
set_property LOC U6 [get_ports {ddr3_dq[12]}]
set_property PACKAGE_PIN U6 [get_ports {ddr3_dq[12]}]
set_property SLEW FAST [get_ports {ddr3_dq[12]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
# ddram:0.dq
set_property LOC V4 [get_ports {ddr3_dq[13]}]
set_property PACKAGE_PIN V4 [get_ports {ddr3_dq[13]}]
set_property SLEW FAST [get_ports {ddr3_dq[13]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
# ddram:0.dq
set_property LOC V6 [get_ports {ddr3_dq[14]}]
set_property PACKAGE_PIN V6 [get_ports {ddr3_dq[14]}]
set_property SLEW FAST [get_ports {ddr3_dq[14]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
# ddram:0.dq
set_property LOC U2 [get_ports {ddr3_dq[15]}]
set_property PACKAGE_PIN U2 [get_ports {ddr3_dq[15]}]
set_property SLEW FAST [get_ports {ddr3_dq[15]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
# ddram:0.dq
set_property LOC AE3 [get_ports {ddr3_dq[16]}]
set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[16]}]
set_property SLEW FAST [get_ports {ddr3_dq[16]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[16]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}]
# ddram:0.dq
set_property LOC AE6 [get_ports {ddr3_dq[17]}]
set_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[17]}]
set_property SLEW FAST [get_ports {ddr3_dq[17]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[17]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}]
# ddram:0.dq
set_property LOC AF3 [get_ports {ddr3_dq[18]}]
set_property PACKAGE_PIN AF3 [get_ports {ddr3_dq[18]}]
set_property SLEW FAST [get_ports {ddr3_dq[18]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[18]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}]
# ddram:0.dq
set_property LOC AD1 [get_ports {ddr3_dq[19]}]
set_property PACKAGE_PIN AD1 [get_ports {ddr3_dq[19]}]
set_property SLEW FAST [get_ports {ddr3_dq[19]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[19]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}]
# ddram:0.dq
set_property LOC AE1 [get_ports {ddr3_dq[20]}]
set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[20]}]
set_property SLEW FAST [get_ports {ddr3_dq[20]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[20]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}]
# ddram:0.dq
set_property LOC AE2 [get_ports {ddr3_dq[21]}]
set_property PACKAGE_PIN AE2 [get_ports {ddr3_dq[21]}]
set_property SLEW FAST [get_ports {ddr3_dq[21]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[21]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}]
# ddram:0.dq
set_property LOC AF2 [get_ports {ddr3_dq[22]}]
set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[22]}]
set_property SLEW FAST [get_ports {ddr3_dq[22]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[22]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}]
# ddram:0.dq
set_property LOC AE5 [get_ports {ddr3_dq[23]}]
set_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[23]}]
set_property SLEW FAST [get_ports {ddr3_dq[23]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[23]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}]
# ddram:0.dq
set_property LOC AD5 [get_ports {ddr3_dq[24]}]
set_property PACKAGE_PIN AD5 [get_ports {ddr3_dq[24]}]
set_property SLEW FAST [get_ports {ddr3_dq[24]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[24]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}]
# ddram:0.dq
set_property LOC Y5 [get_ports {ddr3_dq[25]}]
set_property PACKAGE_PIN Y5 [get_ports {ddr3_dq[25]}]
set_property SLEW FAST [get_ports {ddr3_dq[25]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[25]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}]
# ddram:0.dq
set_property LOC AC6 [get_ports {ddr3_dq[26]}]
set_property PACKAGE_PIN AC6 [get_ports {ddr3_dq[26]}]
set_property SLEW FAST [get_ports {ddr3_dq[26]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[26]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}]
# ddram:0.dq
set_property LOC Y6 [get_ports {ddr3_dq[27]}]
set_property PACKAGE_PIN Y6 [get_ports {ddr3_dq[27]}]
set_property SLEW FAST [get_ports {ddr3_dq[27]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[27]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}]
# ddram:0.dq
set_property LOC AB4 [get_ports {ddr3_dq[28]}]
set_property PACKAGE_PIN AB4 [get_ports {ddr3_dq[28]}]
set_property SLEW FAST [get_ports {ddr3_dq[28]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[28]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}]
# ddram:0.dq
set_property LOC AD6 [get_ports {ddr3_dq[29]}]
set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[29]}]
set_property SLEW FAST [get_ports {ddr3_dq[29]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[29]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}]
# ddram:0.dq
set_property LOC AB6 [get_ports {ddr3_dq[30]}]
set_property PACKAGE_PIN AB6 [get_ports {ddr3_dq[30]}]
set_property SLEW FAST [get_ports {ddr3_dq[30]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[30]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}]
# ddram:0.dq
set_property LOC AC3 [get_ports {ddr3_dq[31]}]
set_property PACKAGE_PIN AC3 [get_ports {ddr3_dq[31]}]
set_property SLEW FAST [get_ports {ddr3_dq[31]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[31]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}]
# ddram:0.dq
set_property LOC AD16 [get_ports {ddr3_dq[32]}]
set_property PACKAGE_PIN AD16 [get_ports {ddr3_dq[32]}]
set_property SLEW FAST [get_ports {ddr3_dq[32]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[32]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[32]}]
# ddram:0.dq
set_property LOC AE17 [get_ports {ddr3_dq[33]}]
set_property PACKAGE_PIN AE17 [get_ports {ddr3_dq[33]}]
set_property SLEW FAST [get_ports {ddr3_dq[33]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[33]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[33]}]
# ddram:0.dq
set_property LOC AF15 [get_ports {ddr3_dq[34]}]
set_property PACKAGE_PIN AF15 [get_ports {ddr3_dq[34]}]
set_property SLEW FAST [get_ports {ddr3_dq[34]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[34]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[34]}]
# ddram:0.dq
set_property LOC AF20 [get_ports {ddr3_dq[35]}]
set_property PACKAGE_PIN AF20 [get_ports {ddr3_dq[35]}]
set_property SLEW FAST [get_ports {ddr3_dq[35]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[35]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[35]}]
# ddram:0.dq
set_property LOC AD15 [get_ports {ddr3_dq[36]}]
set_property PACKAGE_PIN AD15 [get_ports {ddr3_dq[36]}]
set_property SLEW FAST [get_ports {ddr3_dq[36]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[36]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[36]}]
# ddram:0.dq
set_property LOC AF14 [get_ports {ddr3_dq[37]}]
set_property PACKAGE_PIN AF14 [get_ports {ddr3_dq[37]}]
set_property SLEW FAST [get_ports {ddr3_dq[37]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[37]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[37]}]
# ddram:0.dq
set_property LOC AE15 [get_ports {ddr3_dq[38]}]
set_property PACKAGE_PIN AE15 [get_ports {ddr3_dq[38]}]
set_property SLEW FAST [get_ports {ddr3_dq[38]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[38]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[38]}]
# ddram:0.dq
set_property LOC AF17 [get_ports {ddr3_dq[39]}]
set_property PACKAGE_PIN AF17 [get_ports {ddr3_dq[39]}]
set_property SLEW FAST [get_ports {ddr3_dq[39]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[39]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[39]}]
# ddram:0.dq
set_property LOC AA14 [get_ports {ddr3_dq[40]}]
set_property PACKAGE_PIN AA14 [get_ports {ddr3_dq[40]}]
set_property SLEW FAST [get_ports {ddr3_dq[40]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[40]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[40]}]
# ddram:0.dq
set_property LOC AA15 [get_ports {ddr3_dq[41]}]
set_property PACKAGE_PIN AA15 [get_ports {ddr3_dq[41]}]
set_property SLEW FAST [get_ports {ddr3_dq[41]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[41]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[41]}]
# ddram:0.dq
set_property LOC AC14 [get_ports {ddr3_dq[42]}]
set_property PACKAGE_PIN AC14 [get_ports {ddr3_dq[42]}]
set_property SLEW FAST [get_ports {ddr3_dq[42]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[42]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[42]}]
# ddram:0.dq
set_property LOC AD14 [get_ports {ddr3_dq[43]}]
set_property PACKAGE_PIN AD14 [get_ports {ddr3_dq[43]}]
set_property SLEW FAST [get_ports {ddr3_dq[43]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[43]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[43]}]
# ddram:0.dq
set_property LOC AB14 [get_ports {ddr3_dq[44]}]
set_property PACKAGE_PIN AB14 [get_ports {ddr3_dq[44]}]
set_property SLEW FAST [get_ports {ddr3_dq[44]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[44]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[44]}]
# ddram:0.dq
set_property LOC AB15 [get_ports {ddr3_dq[45]}]
set_property PACKAGE_PIN AB15 [get_ports {ddr3_dq[45]}]
set_property SLEW FAST [get_ports {ddr3_dq[45]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[45]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[45]}]
# ddram:0.dq
set_property LOC AA17 [get_ports {ddr3_dq[46]}]
set_property PACKAGE_PIN AA17 [get_ports {ddr3_dq[46]}]
set_property SLEW FAST [get_ports {ddr3_dq[46]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[46]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[46]}]
# ddram:0.dq
set_property LOC AA18 [get_ports {ddr3_dq[47]}]
set_property PACKAGE_PIN AA18 [get_ports {ddr3_dq[47]}]
set_property SLEW FAST [get_ports {ddr3_dq[47]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[47]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[47]}]
# ddram:0.dq
set_property LOC AB20 [get_ports {ddr3_dq[48]}]
set_property PACKAGE_PIN AB20 [get_ports {ddr3_dq[48]}]
set_property SLEW FAST [get_ports {ddr3_dq[48]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[48]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[48]}]
# ddram:0.dq
set_property LOC AD19 [get_ports {ddr3_dq[49]}]
set_property PACKAGE_PIN AD19 [get_ports {ddr3_dq[49]}]
set_property SLEW FAST [get_ports {ddr3_dq[49]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[49]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[49]}]
# ddram:0.dq
set_property LOC AC19 [get_ports {ddr3_dq[50]}]
set_property PACKAGE_PIN AC19 [get_ports {ddr3_dq[50]}]
set_property SLEW FAST [get_ports {ddr3_dq[50]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[50]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[50]}]
# ddram:0.dq
set_property LOC AA20 [get_ports {ddr3_dq[51]}]
set_property PACKAGE_PIN AA20 [get_ports {ddr3_dq[51]}]
set_property SLEW FAST [get_ports {ddr3_dq[51]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[51]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[51]}]
# ddram:0.dq
set_property LOC AA19 [get_ports {ddr3_dq[52]}]
set_property PACKAGE_PIN AA19 [get_ports {ddr3_dq[52]}]
set_property SLEW FAST [get_ports {ddr3_dq[52]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[52]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[52]}]
# ddram:0.dq
set_property LOC AC17 [get_ports {ddr3_dq[53]}]
set_property PACKAGE_PIN AC17 [get_ports {ddr3_dq[53]}]
set_property SLEW FAST [get_ports {ddr3_dq[53]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[53]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[53]}]
# ddram:0.dq
set_property LOC AD18 [get_ports {ddr3_dq[54]}]
set_property PACKAGE_PIN AD18 [get_ports {ddr3_dq[54]}]
set_property SLEW FAST [get_ports {ddr3_dq[54]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[54]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[54]}]
# ddram:0.dq
set_property LOC AB17 [get_ports {ddr3_dq[55]}]
set_property PACKAGE_PIN AB17 [get_ports {ddr3_dq[55]}]
set_property SLEW FAST [get_ports {ddr3_dq[55]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[55]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[55]}]
# ddram:0.dq
set_property LOC W15 [get_ports {ddr3_dq[56]}]
set_property PACKAGE_PIN W15 [get_ports {ddr3_dq[56]}]
set_property SLEW FAST [get_ports {ddr3_dq[56]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[56]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[56]}]
# ddram:0.dq
set_property LOC W16 [get_ports {ddr3_dq[57]}]
set_property PACKAGE_PIN W16 [get_ports {ddr3_dq[57]}]
set_property SLEW FAST [get_ports {ddr3_dq[57]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[57]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[57]}]
# ddram:0.dq
set_property LOC W14 [get_ports {ddr3_dq[58]}]
set_property PACKAGE_PIN W14 [get_ports {ddr3_dq[58]}]
set_property SLEW FAST [get_ports {ddr3_dq[58]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[58]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[58]}]
# ddram:0.dq
set_property LOC V16 [get_ports {ddr3_dq[59]}]
set_property PACKAGE_PIN V16 [get_ports {ddr3_dq[59]}]
set_property SLEW FAST [get_ports {ddr3_dq[59]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[59]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[59]}]
# ddram:0.dq
set_property LOC V19 [get_ports {ddr3_dq[60]}]
set_property PACKAGE_PIN V19 [get_ports {ddr3_dq[60]}]
set_property SLEW FAST [get_ports {ddr3_dq[60]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[60]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[60]}]
# ddram:0.dq
set_property LOC V17 [get_ports {ddr3_dq[61]}]
set_property PACKAGE_PIN V17 [get_ports {ddr3_dq[61]}]
set_property SLEW FAST [get_ports {ddr3_dq[61]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[61]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[61]}]
# ddram:0.dq
set_property LOC V18 [get_ports {ddr3_dq[62]}]
set_property PACKAGE_PIN V18 [get_ports {ddr3_dq[62]}]
set_property SLEW FAST [get_ports {ddr3_dq[62]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[62]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[62]}]
# ddram:0.dq
set_property LOC Y17 [get_ports {ddr3_dq[63]}]
set_property PACKAGE_PIN Y17 [get_ports {ddr3_dq[63]}]
set_property SLEW FAST [get_ports {ddr3_dq[63]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[63]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[63]}]
# ddram:0.dqs_p
set_property LOC AB1 [get_ports {ddr3_dqs_p[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}]
# ddram:0.dqs_p
set_property LOC W6 [get_ports {ddr3_dqs_p[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}]
# ddram:0.dqs_p
set_property LOC AF5 [get_ports {ddr3_dqs_p[2]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[2]}]
# ddram:0.dqs_p
set_property LOC AA5 [get_ports {ddr3_dqs_p[3]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[3]}]
# ddram:0.dqs_p
set_property LOC AE18 [get_ports {ddr3_dqs_p[4]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[4]}]
# ddram:0.dqs_p
set_property LOC Y15 [get_ports {ddr3_dqs_p[5]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[5]}]
# ddram:0.dqs_p
set_property LOC AD20 [get_ports {ddr3_dqs_p[6]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[6]}]
# ddram:0.dqs_p
set_property LOC W18 [get_ports {ddr3_dqs_p[7]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[7]}]
# ddram:0.dqs_n
set_property LOC AC1 [get_ports {ddr3_dqs_n[0]}]
set_property PACKAGE_PIN AB1 [get_ports {ddr3_dqs_p[0]}]
set_property PACKAGE_PIN AC1 [get_ports {ddr3_dqs_n[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}]
# ddram:0.dqs_n
set_property LOC W5 [get_ports {ddr3_dqs_n[1]}]
set_property PACKAGE_PIN W6 [get_ports {ddr3_dqs_p[1]}]
set_property PACKAGE_PIN W5 [get_ports {ddr3_dqs_n[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}]
# ddram:0.dqs_n
set_property LOC AF4 [get_ports {ddr3_dqs_n[2]}]
set_property PACKAGE_PIN AF5 [get_ports {ddr3_dqs_p[2]}]
set_property PACKAGE_PIN AF4 [get_ports {ddr3_dqs_n[2]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[2]}]
# ddram:0.dqs_n
set_property LOC AB5 [get_ports {ddr3_dqs_n[3]}]
set_property PACKAGE_PIN AA5 [get_ports {ddr3_dqs_p[3]}]
set_property PACKAGE_PIN AB5 [get_ports {ddr3_dqs_n[3]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[3]}]
# ddram:0.dqs_n
set_property LOC AF18 [get_ports {ddr3_dqs_n[4]}]
set_property PACKAGE_PIN AE18 [get_ports {ddr3_dqs_p[4]}]
set_property PACKAGE_PIN AF18 [get_ports {ddr3_dqs_n[4]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[4]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[4]}]
# ddram:0.dqs_n
set_property LOC Y16 [get_ports {ddr3_dqs_n[5]}]
set_property PACKAGE_PIN Y15 [get_ports {ddr3_dqs_p[5]}]
set_property PACKAGE_PIN Y16 [get_ports {ddr3_dqs_n[5]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[5]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[5]}]
# ddram:0.dqs_n
set_property LOC AE20 [get_ports {ddr3_dqs_n[6]}]
set_property PACKAGE_PIN AD20 [get_ports {ddr3_dqs_p[6]}]
set_property PACKAGE_PIN AE20 [get_ports {ddr3_dqs_n[6]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[6]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[6]}]
# ddram:0.dqs_n
set_property LOC W19 [get_ports {ddr3_dqs_n[7]}]
set_property PACKAGE_PIN W18 [get_ports {ddr3_dqs_p[7]}]
set_property PACKAGE_PIN W19 [get_ports {ddr3_dqs_n[7]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[7]}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[7]}]
# ddram:0.clk_p
set_property LOC AB12 [get_ports {ddr3_clk_p}]
set_property SLEW FAST [get_ports {ddr3_clk_p}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_clk_p}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_clk_p}]
set_property SLEW FAST [get_ports ddr3_clk_p]
set_property VCCAUX_IO HIGH [get_ports ddr3_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr3_clk_p]
# ddram:0.clk_n
set_property LOC AC12 [get_ports {ddr3_clk_n}]
set_property SLEW FAST [get_ports {ddr3_clk_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_clk_n}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_clk_n}]
set_property PACKAGE_PIN AB12 [get_ports ddr3_clk_p]
set_property PACKAGE_PIN AC12 [get_ports ddr3_clk_n]
set_property SLEW FAST [get_ports ddr3_clk_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr3_clk_n]
# ddram:0.cke
set_property LOC AA13 [get_ports {ddr3_cke}]
set_property SLEW FAST [get_ports {ddr3_cke}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_cke}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke}]
set_property PACKAGE_PIN AA13 [get_ports ddr3_cke]
set_property SLEW FAST [get_ports ddr3_cke]
set_property VCCAUX_IO HIGH [get_ports ddr3_cke]
set_property IOSTANDARD SSTL15 [get_ports ddr3_cke]
# ddram:0.odt
set_property LOC AD13 [get_ports {ddr3_odt}]
set_property SLEW FAST [get_ports {ddr3_odt}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_odt}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt}]
set_property PACKAGE_PIN AD13 [get_ports ddr3_odt]
set_property SLEW FAST [get_ports ddr3_odt]
set_property VCCAUX_IO HIGH [get_ports ddr3_odt]
set_property IOSTANDARD SSTL15 [get_ports ddr3_odt]
# ddram:0.reset_n
set_property LOC AB7 [get_ports {ddr3_reset_n}]
set_property SLEW FAST [get_ports {ddr3_reset_n}]
set_property VCCAUX_IO HIGH [get_ports {ddr3_reset_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_reset_n}]
set_property SLEW SLOW [get_ports {ddr3_reset_n}]
set_property PACKAGE_PIN AB7 [get_ports ddr3_reset_n]
set_property VCCAUX_IO HIGH [get_ports ddr3_reset_n]
set_property IOSTANDARD SSTL15 [get_ports ddr3_reset_n]
set_property SLEW SLOW [get_ports ddr3_reset_n]
# user_led:0
set_property LOC U9 [get_ports {led[0]}]
set_property PACKAGE_PIN U9 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[0]}]
set_property SLEW SLOW [get_ports {led[0]}]
# user_led:1
set_property LOC V12 [get_ports {led[1]}]
set_property PACKAGE_PIN V12 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[1]}]
set_property SLEW SLOW [get_ports {led[1]}]
# user_led:2
set_property LOC V13 [get_ports {led[2]}]
set_property PACKAGE_PIN V13 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[2]}]
set_property SLEW SLOW [get_ports {led[2]}]
# user_led:3
set_property LOC W13 [get_ports {led[3]}]
set_property PACKAGE_PIN W13 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[3]}]
set_property SLEW SLOW [get_ports {led[3]}]
@ -747,4 +738,3 @@ set_property CFGBVS GND [current_design]
################################################################################
create_clock -name i_clk200_p -period 5.0 [get_ports i_clk200_p]