update all simulation log files

2025-05-12 11:05:36 +08:00 · 2025-05-12 11:05:36 +08:00 · fe8563ed65
parent 9fd104b566
commit fe8563ed65
16 changed files with 226679 additions and 226659 deletions
--- a/testbench/xsim/test_10_000_ddr3_2_500_odelay_0_lanes_two_lanes_bus_delay_0_bist_2.log
+++ b/testbench/xsim/test_10_000_ddr3_2_500_odelay_0_lanes_two_lanes_bus_delay_0_bist_2.log
--- a/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_eight_lanes_bus_delay_0_bist_2.log
+++ b/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_eight_lanes_bus_delay_0_bist_2.log
--- a/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_eight_lanes_bus_delay_1_bist_1.log
+++ b/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_eight_lanes_bus_delay_1_bist_1.log
--- a/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_two_lanes_bus_delay_1_bist_1.log
+++ b/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_two_lanes_bus_delay_1_bist_1.log
--- a/testbench/xsim/test_12_000_ddr3_3_000_odelay_0_lanes_two_lanes_bus_delay_0_bist_2.log
+++ b/testbench/xsim/test_12_000_ddr3_3_000_odelay_0_lanes_two_lanes_bus_delay_0_bist_2.log
--- a/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_eight_lanes_bus_delay_0_bist_2.log
+++ b/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_eight_lanes_bus_delay_0_bist_2.log
--- a/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_eight_lanes_bus_delay_1_bist_1.log
+++ b/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_eight_lanes_bus_delay_1_bist_1.log
--- a/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_two_lanes_bus_delay_1_bist_1.log
+++ b/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_two_lanes_bus_delay_1_bist_1.log
--- a/testbench/xsim/test_5_000_ddr3_1_250_odelay_0_lanes_two_lanes_bus_delay_0_bist_1.log
+++ b/testbench/xsim/test_5_000_ddr3_1_250_odelay_0_lanes_two_lanes_bus_delay_0_bist_1.log
--- a/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_eight_lanes_bus_delay_0_bist_1.log
+++ b/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_eight_lanes_bus_delay_0_bist_1.log
--- a/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_eight_lanes_bus_delay_1_bist_2.log
+++ b/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_eight_lanes_bus_delay_1_bist_2.log
--- a/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_two_lanes_bus_delay_1_bist_2.log
+++ b/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_two_lanes_bus_delay_1_bist_2.log
--- a/testbench/xsim/test_6_000_ddr3_1_500_odelay_0_lanes_two_lanes_bus_delay_0_bist_1.log
+++ b/testbench/xsim/test_6_000_ddr3_1_500_odelay_0_lanes_two_lanes_bus_delay_0_bist_1.log
--- a/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_eight_lanes_bus_delay_0_bist_1.log
+++ b/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_eight_lanes_bus_delay_0_bist_1.log
--- a/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_eight_lanes_bus_delay_1_bist_2.log
+++ b/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_eight_lanes_bus_delay_1_bist_2.log
--- a/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_two_lanes_bus_delay_1_bist_2.log
+++ b/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_two_lanes_bus_delay_1_bist_2.log