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UberDDR3
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run at DDR3-1000 (125MHz controller clock)

This commit is contained in:
AngeloJacobo 2025-12-26 10:02:16 +08:00
parent 80da754a64
commit 356c6cc1a2
2 changed files with 8 additions and 7 deletions
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9
example_demo/alinx_ax7325b/ax7325b_ddr3.v
View File

@ -164,12 +164,12 @@
// DDR3 Controller
ddr3_top #(
.CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.CONTROLLER_CLK_PERIOD(8_000), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(2_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.ROW_BITS(15), //width of row address
.COL_BITS(10), //width of column address
.BA_BITS(3), //width of bank address
.BYTE_LANES(8), //number of DDR3 modules to be controlled
.BYTE_LANES(2), //number of DDR3 modules to be controlled
.AUX_WIDTH(16), //width of aux line (must be >= 4)
.WB2_ADDR_BITS(32), //width of 2nd wishbone address bus
.WB2_DATA_BITS(32), //width of 2nd wishbone data bus
@ -177,7 +177,8 @@
.ODELAY_SUPPORTED(1), //set to 1 when ODELAYE2 is supported
.SECOND_WISHBONE(0), //set to 1 if 2nd wishbone is needed
.ECC_ENABLE(0), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
.WB_ERROR(0) // set to 1 to support Wishbone error (asserts at ECC double bit error)
.WB_ERROR(0), // set to 1 to support Wishbone error (asserts at ECC double bit error)
.BIST_MODE(1)
) ddr3_top
(
//clock and reset

6
example_demo/alinx_ax7325b/clk_wiz.v
View File

@ -25,16 +25,16 @@ module clk_wiz
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (5), // 200 MHz * 5 = 1000 MHz
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (12), // 1000 MHz / 12 = 83.333 MHz
.CLKOUT0_DIVIDE (8), // 1000 MHz / 8 = 125 MHz
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz, 0 phase
.CLKOUT1_DIVIDE (2), // 1000 MHz / 2 = 500 MHz, 0 phase
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (5), // 1000 MHz / 5 = 200 MHz
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz, 90 phase
.CLKOUT3_DIVIDE (2), // 1000 MHz / 2 = 500 MHz, 90 phase
.CLKOUT3_PHASE (90.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (5.000) // 200 MHz input