add uart_tx to top

2025-03-02 19:05:30 +08:00 · 2025-03-02 19:05:30 +08:00 · 7f801b1f1d
parent c0bc4ca48a
commit 7f801b1f1d
1 changed files with 4 additions and 2 deletions
--- a/rtl/ddr3_top.v
+++ b/rtl/ddr3_top.v
@ -123,7 +123,8 @@ module ddr3_top #(
 //        output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
        // 
        // User enabled self-refresh
-        input wire i_user_self_refresh
+        input wire i_user_self_refresh,
+        output wire uart_tx
    );
    
 // Instantiation Template (DEFAULT VALUE IS FOR ARTY S7)
@ -326,7 +327,8 @@ ddr3_top #(
 //            .o_debug2(o_debug2),
 //            .o_debug3(o_debug3)
            // User enabled self-refresh
-            .i_user_self_refresh(user_self_refresh)
+            .i_user_self_refresh(user_self_refresh),
+            .uart_tx(uart_tx)
        );
        
    ddr3_phy #(