Step 3: Register conditions in advance (calibration fsm)
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AngeloJacobo
parent
282d9596ca
commit
fad0a7b19a
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@ -582,6 +582,7 @@ module ddr3_controller #(
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reg prev_write_level_feedback = 1;
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reg[wb_data_bits-1:0] read_data_store = 0;
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reg[127:0] write_pattern = 0;
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reg[63:0] write_pattern_lane = 0;
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reg[$clog2(64):0] data_start_index[LANES-1:0];
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reg[LANES-1:0] lane_write_dq_late = 0;
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reg[LANES-1:0] lane_read_dq_early = 0;
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@ -594,6 +595,7 @@ module ddr3_controller #(
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reg stored_write_level_feedback = 0;
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reg[5:0] start_index_check = 0;
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reg[63:0] read_lane_data = 0;
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reg[31:0] read_lane_data_shifted = 0;
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reg odelay_cntvalue_halfway = 0;
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reg initial_calibration_done = 0;
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reg final_calibration_done = 0;
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@ -664,6 +666,9 @@ module ddr3_controller #(
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reg stage1_do_act, stage1_do_act_d;
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reg force_o_wb_stall_high_q, force_o_wb_stall_high_d;
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reg force_o_wb_stall_calib_high_q, force_o_wb_stall_calib_high_d;
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reg[1:0] prep_done;
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reg write_pattern_matches;
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// initial block for all regs
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initial begin
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o_wb_stall = 1;
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@ -1440,9 +1445,9 @@ module ddr3_controller #(
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end
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end
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always @* begin
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for(index = 0; index < LANES; index = index + 1) begin
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late_dq[index] = (lane_write_dq_late[index] && (data_start_index[index] != 0)) && (STAGE2_DATA_DEPTH > 1);
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always @(posedge i_controller_clk) begin
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for(index = 0; index < LANES; index = index + 1) begin
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late_dq[index] <= (lane_write_dq_late[index] && (data_start_index[index] != 0)) && (STAGE2_DATA_DEPTH > 1);
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end
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end
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@ -2406,6 +2411,9 @@ module ddr3_controller #(
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pause_counter <= 0;
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read_data_store <= 0;
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write_pattern <= 0;
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write_pattern_lane <= 0;
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read_lane_data_shifted <= 0;
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write_pattern_matches <= 0;
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added_read_pipe_max <= 0;
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dqs_start_index_stored <= 0;
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dqs_start_index_repeat <= 0;
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@ -2426,6 +2434,7 @@ module ddr3_controller #(
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lane_read_dq_early <= 0;
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shift_read_pipe <= 0;
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bitslip_counter <= 0;
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prep_done <= 0;
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`ifdef UART_DEBUG
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uart_start_send <= 0;
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uart_text <= 0;
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@ -2458,6 +2467,7 @@ module ddr3_controller #(
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idelay_data_cntvaluein_prev <= idelay_data_cntvaluein[lane];
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reset_from_calibrate <= 0;
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reset_after_rank_1 <= 0; // reset for dual rank
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prep_done <= 0;
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if(wb2_update) begin
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odelay_data_cntvaluein[wb2_write_lane] <= wb2_phy_odelay_data_ld[wb2_write_lane]? wb2_phy_odelay_data_cntvaluein : odelay_data_cntvaluein[wb2_write_lane];
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@ -2995,9 +3005,8 @@ module ddr3_controller #(
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// e.g. LANE={burst7, burst6, burst5, burst4, burst3, burst2, burst1, burst0} then with 1 ddr3 cycle delay between DQ and command
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// burst0 will not be written but only starting on burst1
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// if lane_write_dq_late is already set to 1 for this lane, then current lane should already be fixed without changing the data_start_index
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ANALYZE_DATA: if(write_pattern[ (lane_write_dq_late[lane]? 0 : data_start_index[lane]) +: 64] == {read_data_store[((DQ_BITS*LANES)*7 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*6 + 8*lane) +: 8],
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read_data_store[((DQ_BITS*LANES)*5 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*4 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*3 + 8*lane) +: 8],
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read_data_store[((DQ_BITS*LANES)*2 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*1 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*0 + 8*lane) +: 8] }) begin
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ANALYZE_DATA: if(prep_done[1]) begin
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if(write_pattern_matches) begin
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/* verilator lint_off WIDTH */
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if(lane == LANES - 1) begin
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/* verilator lint_on WIDTH */
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@ -3013,6 +3022,7 @@ module ddr3_controller #(
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else begin
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lane <= lane + 1;
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data_start_index[lane+1] <= 0;
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state_calibrate <= ANALYZE_DATA;
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`ifdef UART_DEBUG_ALIGN
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uart_start_send <= 1'b1;
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uart_text <= {"state=ANALYZE_DATA, Done lane=",hex_to_ascii(lane),8'h0a,"-----------------",8'h0a};
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@ -3062,6 +3072,7 @@ module ddr3_controller #(
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`ifdef UART_DEBUG_ALIGN
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else begin
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uart_start_send <= 1'b1;
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state_calibrate <= ANALYZE_DATA;
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uart_text <= {"state=ANALYZE_DATA, lane=",hex_to_ascii(lane), ", data_start_index[lane]=0x",
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hex_to_ascii(data_start_index[lane][6:4]),hex_to_ascii(data_start_index[lane][3:0]),8'h0a,8'h0a,8'h0a,8'h0a,
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{read_data_store[((DQ_BITS*LANES)*7 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*6 + 8*lane) +: 8],
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@ -3073,13 +3084,17 @@ module ddr3_controller #(
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state_calibrate_next <= ANALYZE_DATA;
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end
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`endif
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end
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end
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else begin
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prep_done <= {prep_done[0],1'b1};
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end
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// check when the 4 MSB of write_pattern {d0ad51c1} starts on read_lane_data (read_lane_data is just the concatenation of read_data_store of a specific lane)
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// assumption here read_lane_data ~= 298cd0ad51c1XXXX is written: either because we write too late (thus we need to delay outgoing stage2_data) OR we read too early (thus we need to calibrate incoming iserdes_dq)
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CHECK_STARTING_DATA: begin
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CHECK_STARTING_DATA: if(prep_done[1]) begin
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/* verilator lint_off WIDTHTRUNC */
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if(read_lane_data[start_index_check +: 32] == write_pattern[0 +: 32]) begin
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if(read_lane_data_shifted == write_pattern[0 +: 32]) begin
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/* verilator lint_on WIDTHTRUNC */
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// first assumption: controller DQ is late WHEN WRITING(THUS WE NEED TO CALIBRATE data_start_index of outgoing stage2_data)
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if(!lane_write_dq_late[lane]) begin // lane_write_dq_late is not yet set so we know this first assunmption is not yet tested
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@ -3137,6 +3152,9 @@ module ddr3_controller #(
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end
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`endif
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end
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end
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else begin
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prep_done <= {prep_done[0],1'b1};
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end
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BITSLIP_DQS_TRAIN_3: if(train_delay == 0) begin //train again the ISERDES to capture the DQ correctly
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@ -3354,10 +3372,13 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
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`ifdef FORMAL_COVER
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state_calibrate <= DONE_CALIBRATE;
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`endif
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read_lane_data <= {read_data_store[((DQ_BITS*LANES)*7 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*6 + 8*lane) +: 8],
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read_data_store[((DQ_BITS*LANES)*5 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*4 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*3 + 8*lane) +: 8],
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read_data_store[((DQ_BITS*LANES)*2 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*1 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*0 + 8*lane) +: 8] };
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read_lane_data <= {read_data_store[((DQ_BITS*LANES)*7 + ({29'd0, lane}<<3)) +: 8], read_data_store[((DQ_BITS*LANES)*6 + ({29'd0, lane}<<3)) +: 8],
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read_data_store[((DQ_BITS*LANES)*5 + ({29'd0, lane}<<3)) +: 8], read_data_store[((DQ_BITS*LANES)*4 + ({29'd0, lane}<<3)) +: 8], read_data_store[((DQ_BITS*LANES)*3 + ({29'd0, lane}<<3)) +: 8],
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read_data_store[((DQ_BITS*LANES)*2 + ({29'd0, lane}<<3)) +: 8],read_data_store[((DQ_BITS*LANES)*1 + ({29'd0, lane}<<3)) +: 8],read_data_store[((DQ_BITS*LANES)*0 + ({29'd0, lane}<<3)) +: 8] };
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write_pattern_lane <= write_pattern[ (lane_write_dq_late[lane]? 0 : data_start_index[lane]) +: 64];
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read_lane_data_shifted <= read_lane_data[start_index_check +: 32];
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write_pattern_matches <= write_pattern_lane == read_lane_data;
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//halfway value has been reached (illegal) and will go back to zero at next load
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if(odelay_data_cntvaluein[lane] == 15) begin
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odelay_cntvalue_halfway <= 1;
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