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Add YPCB-00338-1P1 DDR3 example

This commit is contained in:
Roland Coeurjoly 2026-05-20 16:32:30 +02:00
parent be6b2a3b8d
commit 5f6165980a
6 changed files with 683 additions and 1 deletions
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66
example_demo/ypcb_00338_1p1/Makefile Normal file
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PROJECT = ypcb_00338_1p1_ddr3
FAMILY = kintex7
PART = xc7k480tffg1156-2
CHIPDB = ${KINTEX7_CHIPDB}
ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v ../../rtl/ddr3_phy.v ../../rtl/ddr3_top.v clk_wiz.v
NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
PRJXRAY_DB_DIR ?= ${NEXTPNR_XILINX_DIR}/external/prjxray-db
DBPART = $(shell echo ${PART} | sed -e 's/-[0-9]//g')
SPEEDGRADE = $(shell echo ${PART} | sed -e 's/.*\-\([0-9]\)/\1/g')
CHIPDB ?= ./
ifeq ($(CHIPDB),)
CHIPDB = ./
endif
PYPY3 ?= pypy3
TOP ?= ${PROJECT}
TOP_MODULE ?= ${TOP}
TOP_VERILOG ?= ${TOP}.v
PNR_DEBUG ?= # --verbose --debug
PNR_ARGS ?=
PNR_FREQ_MHZ ?= 83.333
JTAG_LINK ?= -c digilent_hs3
XDC ?= ${PROJECT}.xdc
.PHONY: openxc7
openxc7: ${PROJECT}_openxc7.bit
.PHONY: program
program: ${PROJECT}_openxc7.bit
openFPGALoader ${JTAG_LINK} --bitstream $<
${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES} Makefile
yosys -p "read_verilog $< ${ADDITIONAL_SOURCES}; synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json"
# The chip database only needs to be generated once
# that is why we don't clean it with make clean
${CHIPDB}/${DBPART}.bin:
${PYPY3} ${NEXTPNR_XILINX_PYTHON_DIR}/bbaexport.py --device ${PART} --bba ${DBPART}.bba
bbasm -l ${DBPART}.bba ${CHIPDB}/${DBPART}.bin
rm -f ${DBPART}.bba
${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --json ${PROJECT}.json --fasm $@ --freq ${PNR_FREQ_MHZ} ${PNR_ARGS} ${PNR_DEBUG}
${PROJECT}.frames: ${PROJECT}.fasm
fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
${PROJECT}_openxc7.bit: ${PROJECT}.frames
xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
.PHONY: clean
clean:
rm -f *.bit
rm -f *.frames
rm -f *.fasm
rm -f *.json
rm -f *.bin
rm -f *.bba

66
example_demo/ypcb_00338_1p1/clk_wiz.v Normal file
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`timescale 1ps/1ps
module clk_wiz
(
input wire clk_in1,
output wire clk_out1,
output wire clk_out2,
output wire clk_out3,
output wire clk_out4,
input wire reset,
output wire locked
);
wire clk_out1_clk_wiz_0;
wire clk_out2_clk_wiz_0;
wire clk_out3_clk_wiz_0;
wire clk_out4_clk_wiz_0;
wire clkfbout;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("INTERNAL"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (20), // 50 MHz * 20 = 1000 MHz
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (12), // 1000 MHz / 12 = 83.333 MHz
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz, 0 phase
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (5), // 1000 MHz / 5 = 200 MHz
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz, 90 phase
.CLKOUT3_PHASE (90.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (20.000) // 50 MHz input
)
plle2_adv_inst
(
.CLKFBOUT (clkfbout),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT2 (clk_out3_clk_wiz_0),
.CLKOUT3 (clk_out4_clk_wiz_0),
.CLKFBIN (clkfbout),
.CLKIN1 (clk_in1),
.LOCKED (locked),
.RST (reset)
);
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_clk_wiz_0));
BUFG clkout3_buf
(.O (clk_out3),
.I (clk_out3_clk_wiz_0));
BUFG clkout4_buf
(.O (clk_out4),
.I (clk_out4_clk_wiz_0));
endmodule

129
example_demo/ypcb_00338_1p1/ypcb_00338_1p1_ddr3.v Normal file
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`default_nettype none
`timescale 1ps / 1ps
module ypcb_00338_1p1_ddr3 (
input wire clk50,
input wire rst_n,
output wire [0:0] ddr3_ck_p,
output wire [0:0] ddr3_ck_n,
output wire ddr3_reset_n,
output wire [0:0] ddr3_cke,
output wire [0:0] ddr3_cs_n,
output wire ddr3_ras_n,
output wire ddr3_cas_n,
output wire ddr3_we_n,
output wire [14:0] ddr3_addr,
output wire [2:0] ddr3_ba,
inout wire [63:0] ddr3_dq,
inout wire [7:0] ddr3_dqs_p,
inout wire [7:0] ddr3_dqs_n,
output wire [0:0] ddr3_odt,
output wire [2:0] led
);
localparam integer BYTE_LANES = 1;
localparam integer WB_ADDR_BITS = 15 + 10 + 3 - 3;
localparam integer WB_DATA_BITS = 8 * BYTE_LANES * 8;
localparam integer WB_SEL_BITS = WB_DATA_BITS / 8;
wire controller_clk;
wire ddr3_clk;
wire ref_clk;
wire ddr3_clk_90;
wire clk_locked;
wire calib_complete;
wire [31:0] debug1;
wire uart_tx_unused;
wire [BYTE_LANES-1:0] ddr3_dm_unused;
wire bist_done = calib_complete && (debug1[4:0] == 5'd23);
assign led[0] = bist_done;
assign led[1] = !bist_done;
assign led[2] = clk_locked;
clk_wiz clk_wiz_inst (
.clk_in1(clk50),
.clk_out1(controller_clk),
.clk_out2(ddr3_clk),
.clk_out3(ref_clk),
.clk_out4(ddr3_clk_90),
.reset(!rst_n),
.locked(clk_locked)
);
ddr3_top #(
.CONTROLLER_CLK_PERIOD(12_000),
.DDR3_CLK_PERIOD(3_000),
.ROW_BITS(15),
.COL_BITS(10),
.BA_BITS(3),
.BYTE_LANES(BYTE_LANES),
.AUX_WIDTH(4),
.WB2_ADDR_BITS(32),
.WB2_DATA_BITS(32),
.DUAL_RANK_DIMM(0),
.MICRON_SIM(0),
.ODELAY_SUPPORTED(0),
.SECOND_WISHBONE(0),
.DLL_OFF(0),
.WB_ERROR(0),
.BIST_MODE(1),
.BIST_TEST_DATAMASK(0),
.ECC_ENABLE(0),
.SPEED_BIN(1),
.SDRAM_CAPACITY(4)
) ddr3_top_inst (
.i_controller_clk(controller_clk),
.i_ddr3_clk(ddr3_clk),
.i_ref_clk(ref_clk),
.i_ddr3_clk_90(ddr3_clk_90),
.i_rst_n(rst_n && clk_locked),
.i_wb_cyc(1'b1),
.i_wb_stb(1'b0),
.i_wb_we(1'b0),
.i_wb_addr({WB_ADDR_BITS{1'b0}}),
.i_wb_data({WB_DATA_BITS{1'b0}}),
.i_wb_sel({WB_SEL_BITS{1'b1}}),
.i_aux(4'b0),
.o_wb_stall(),
.o_wb_ack(),
.o_wb_err(),
.o_wb_data(),
.o_aux(),
.i_wb2_cyc(1'b0),
.i_wb2_stb(1'b0),
.i_wb2_we(1'b0),
.i_wb2_addr(32'b0),
.i_wb2_data(32'b0),
.i_wb2_sel(4'b0),
.o_wb2_stall(),
.o_wb2_ack(),
.o_wb2_data(),
.o_ddr3_clk_p(ddr3_ck_p),
.o_ddr3_clk_n(ddr3_ck_n),
.o_ddr3_reset_n(ddr3_reset_n),
.o_ddr3_cke(ddr3_cke),
.o_ddr3_cs_n(ddr3_cs_n),
.o_ddr3_ras_n(ddr3_ras_n),
.o_ddr3_cas_n(ddr3_cas_n),
.o_ddr3_we_n(ddr3_we_n),
.o_ddr3_addr(ddr3_addr),
.o_ddr3_ba_addr(ddr3_ba),
.io_ddr3_dq(ddr3_dq[7:0]),
.io_ddr3_dqs(ddr3_dqs_p[0:0]),
.io_ddr3_dqs_n(ddr3_dqs_n[0:0]),
.o_ddr3_dm(ddr3_dm_unused),
.o_ddr3_odt(ddr3_odt),
.o_calib_complete(calib_complete),
.o_debug1(debug1),
.i_user_self_refresh(1'b0),
.uart_tx(uart_tx_unused)
);
endmodule
`default_nettype wire

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example_demo/ypcb_00338_1p1/ypcb_00338_1p1_ddr3.xdc Normal file
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set_property LOC AA28 [get_ports {clk50}]
set_property IOSTANDARD LVCMOS18 [get_ports {clk50}]
create_clock -name clk50 -period 20.000 [get_ports clk50]
set_property LOC R28 [get_ports {rst_n}]
set_property IOSTANDARD LVCMOS18 [get_ports {rst_n}]
set_property LOC P30 [get_ports {led[0]}]
set_property LOC M30 [get_ports {led[1]}]
set_property LOC N30 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {led[2]}]
set_property LOC AK27 [get_ports {ddr3_addr[0]}]
set_property LOC AN23 [get_ports {ddr3_addr[1]}]
set_property LOC AL24 [get_ports {ddr3_addr[2]}]
set_property LOC AK26 [get_ports {ddr3_addr[3]}]
set_property LOC AH24 [get_ports {ddr3_addr[4]}]
set_property LOC AH25 [get_ports {ddr3_addr[5]}]
set_property LOC AL26 [get_ports {ddr3_addr[6]}]
set_property LOC AJ24 [get_ports {ddr3_addr[7]}]
set_property LOC AJ25 [get_ports {ddr3_addr[8]}]
set_property LOC AM23 [get_ports {ddr3_addr[9]}]
set_property LOC AL28 [get_ports {ddr3_addr[10]}]
set_property LOC AL25 [get_ports {ddr3_addr[11]}]
set_property LOC AM25 [get_ports {ddr3_addr[12]}]
set_property LOC AK24 [get_ports {ddr3_addr[13]}]
set_property LOC AM27 [get_ports {ddr3_addr[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
set_property SLEW FAST [get_ports {ddr3_addr[1]}]
set_property SLEW FAST [get_ports {ddr3_addr[2]}]
set_property SLEW FAST [get_ports {ddr3_addr[3]}]
set_property SLEW FAST [get_ports {ddr3_addr[4]}]
set_property SLEW FAST [get_ports {ddr3_addr[5]}]
set_property SLEW FAST [get_ports {ddr3_addr[6]}]
set_property SLEW FAST [get_ports {ddr3_addr[7]}]
set_property SLEW FAST [get_ports {ddr3_addr[8]}]
set_property SLEW FAST [get_ports {ddr3_addr[9]}]
set_property SLEW FAST [get_ports {ddr3_addr[10]}]
set_property SLEW FAST [get_ports {ddr3_addr[11]}]
set_property SLEW FAST [get_ports {ddr3_addr[12]}]
set_property SLEW FAST [get_ports {ddr3_addr[13]}]
set_property SLEW FAST [get_ports {ddr3_addr[14]}]
set_property LOC AM26 [get_ports {ddr3_ba[0]}]
set_property LOC AP24 [get_ports {ddr3_ba[1]}]
set_property LOC AN28 [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
set_property SLEW FAST [get_ports {ddr3_ba[0]}]
set_property SLEW FAST [get_ports {ddr3_ba[1]}]
set_property SLEW FAST [get_ports {ddr3_ba[2]}]
set_property LOC AJ29 [get_ports {ddr3_ras_n}]
set_property LOC AP26 [get_ports {ddr3_cas_n}]
set_property LOC AN27 [get_ports {ddr3_we_n}]
set_property LOC AK28 [get_ports {ddr3_cs_n}]
set_property LOC AP27 [get_ports {ddr3_cke}]
set_property LOC AK29 [get_ports {ddr3_odt}]
set_property LOC AD31 [get_ports {ddr3_reset_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_reset_n}]
set_property SLEW FAST [get_ports {ddr3_ras_n}]
set_property SLEW FAST [get_ports {ddr3_cas_n}]
set_property SLEW FAST [get_ports {ddr3_we_n}]
set_property SLEW FAST [get_ports {ddr3_cs_n}]
set_property SLEW FAST [get_ports {ddr3_cke}]
set_property SLEW FAST [get_ports {ddr3_odt}]
set_property SLEW FAST [get_ports {ddr3_reset_n}]
set_property LOC AN25 [get_ports {ddr3_ck_p}]
set_property LOC AP25 [get_ports {ddr3_ck_n}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n}]
set_property LOC AG17 [get_ports {ddr3_dq[0]}]
set_property LOC AG16 [get_ports {ddr3_dq[1]}]
set_property LOC AH17 [get_ports {ddr3_dq[2]}]
set_property LOC AJ19 [get_ports {ddr3_dq[3]}]
set_property LOC AH18 [get_ports {ddr3_dq[4]}]
set_property LOC AH19 [get_ports {ddr3_dq[5]}]
set_property LOC AJ16 [get_ports {ddr3_dq[6]}]
set_property LOC AJ17 [get_ports {ddr3_dq[7]}]
set_property LOC AL20 [get_ports {ddr3_dq[8]}]
set_property LOC AN17 [get_ports {ddr3_dq[9]}]
set_property LOC AL19 [get_ports {ddr3_dq[10]}]
set_property LOC AM16 [get_ports {ddr3_dq[11]}]
set_property LOC AL18 [get_ports {ddr3_dq[12]}]
set_property LOC AL16 [get_ports {ddr3_dq[13]}]
set_property LOC AM20 [get_ports {ddr3_dq[14]}]
set_property LOC AN18 [get_ports {ddr3_dq[15]}]
set_property LOC AL23 [get_ports {ddr3_dq[16]}]
set_property LOC AN20 [get_ports {ddr3_dq[17]}]
set_property LOC AK23 [get_ports {ddr3_dq[18]}]
set_property LOC AP19 [get_ports {ddr3_dq[19]}]
set_property LOC AN22 [get_ports {ddr3_dq[20]}]
set_property LOC AN19 [get_ports {ddr3_dq[21]}]
set_property LOC AM22 [get_ports {ddr3_dq[22]}]
set_property LOC AP20 [get_ports {ddr3_dq[23]}]
set_property LOC AJ21 [get_ports {ddr3_dq[24]}]
set_property LOC AH22 [get_ports {ddr3_dq[25]}]
set_property LOC AK21 [get_ports {ddr3_dq[26]}]
set_property LOC AG21 [get_ports {ddr3_dq[27]}]
set_property LOC AG22 [get_ports {ddr3_dq[28]}]
set_property LOC AG20 [get_ports {ddr3_dq[29]}]
set_property LOC AH23 [get_ports {ddr3_dq[30]}]
set_property LOC AG23 [get_ports {ddr3_dq[31]}]
set_property LOC AJ32 [get_ports {ddr3_dq[32]}]
set_property LOC AK32 [get_ports {ddr3_dq[33]}]
set_property LOC AK31 [get_ports {ddr3_dq[34]}]
set_property LOC AL30 [get_ports {ddr3_dq[35]}]
set_property LOC AL34 [get_ports {ddr3_dq[36]}]
set_property LOC AL31 [get_ports {ddr3_dq[37]}]
set_property LOC AK34 [get_ports {ddr3_dq[38]}]
set_property LOC AL29 [get_ports {ddr3_dq[39]}]
set_property LOC AJ34 [get_ports {ddr3_dq[40]}]
set_property LOC AH32 [get_ports {ddr3_dq[41]}]
set_property LOC AJ30 [get_ports {ddr3_dq[42]}]
set_property LOC AH34 [get_ports {ddr3_dq[43]}]
set_property LOC AF31 [get_ports {ddr3_dq[44]}]
set_property LOC AG30 [get_ports {ddr3_dq[45]}]
set_property LOC AG31 [get_ports {ddr3_dq[46]}]
set_property LOC AF30 [get_ports {ddr3_dq[47]}]
set_property LOC AE32 [get_ports {ddr3_dq[48]}]
set_property LOC AC33 [get_ports {ddr3_dq[49]}]
set_property LOC AF33 [get_ports {ddr3_dq[50]}]
set_property LOC AC32 [get_ports {ddr3_dq[51]}]
set_property LOC AD34 [get_ports {ddr3_dq[52]}]
set_property LOC AC34 [get_ports {ddr3_dq[53]}]
set_property LOC AE33 [get_ports {ddr3_dq[54]}]
set_property LOC AE31 [get_ports {ddr3_dq[55]}]
set_property LOC AE26 [get_ports {ddr3_dq[56]}]
set_property LOC AF29 [get_ports {ddr3_dq[57]}]
set_property LOC AE24 [get_ports {ddr3_dq[58]}]
set_property LOC AF28 [get_ports {ddr3_dq[59]}]
set_property LOC AF24 [get_ports {ddr3_dq[60]}]
set_property LOC AG25 [get_ports {ddr3_dq[61]}]
set_property LOC AF26 [get_ports {ddr3_dq[62]}]
set_property LOC AF25 [get_ports {ddr3_dq[63]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[32]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[33]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[34]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[35]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[36]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[37]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[38]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[39]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[40]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[41]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[42]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[43]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[44]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[45]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[46]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[47]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[48]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[49]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[50]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[51]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[52]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[53]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[54]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[55]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[56]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[57]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[58]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[59]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[60]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[61]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[62]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[63]}]
set_property SLEW FAST [get_ports {ddr3_dq[0]}]
set_property SLEW FAST [get_ports {ddr3_dq[1]}]
set_property SLEW FAST [get_ports {ddr3_dq[2]}]
set_property SLEW FAST [get_ports {ddr3_dq[3]}]
set_property SLEW FAST [get_ports {ddr3_dq[4]}]
set_property SLEW FAST [get_ports {ddr3_dq[5]}]
set_property SLEW FAST [get_ports {ddr3_dq[6]}]
set_property SLEW FAST [get_ports {ddr3_dq[7]}]
set_property SLEW FAST [get_ports {ddr3_dq[8]}]
set_property SLEW FAST [get_ports {ddr3_dq[9]}]
set_property SLEW FAST [get_ports {ddr3_dq[10]}]
set_property SLEW FAST [get_ports {ddr3_dq[11]}]
set_property SLEW FAST [get_ports {ddr3_dq[12]}]
set_property SLEW FAST [get_ports {ddr3_dq[13]}]
set_property SLEW FAST [get_ports {ddr3_dq[14]}]
set_property SLEW FAST [get_ports {ddr3_dq[15]}]
set_property SLEW FAST [get_ports {ddr3_dq[16]}]
set_property SLEW FAST [get_ports {ddr3_dq[17]}]
set_property SLEW FAST [get_ports {ddr3_dq[18]}]
set_property SLEW FAST [get_ports {ddr3_dq[19]}]
set_property SLEW FAST [get_ports {ddr3_dq[20]}]
set_property SLEW FAST [get_ports {ddr3_dq[21]}]
set_property SLEW FAST [get_ports {ddr3_dq[22]}]
set_property SLEW FAST [get_ports {ddr3_dq[23]}]
set_property SLEW FAST [get_ports {ddr3_dq[24]}]
set_property SLEW FAST [get_ports {ddr3_dq[25]}]
set_property SLEW FAST [get_ports {ddr3_dq[26]}]
set_property SLEW FAST [get_ports {ddr3_dq[27]}]
set_property SLEW FAST [get_ports {ddr3_dq[28]}]
set_property SLEW FAST [get_ports {ddr3_dq[29]}]
set_property SLEW FAST [get_ports {ddr3_dq[30]}]
set_property SLEW FAST [get_ports {ddr3_dq[31]}]
set_property SLEW FAST [get_ports {ddr3_dq[32]}]
set_property SLEW FAST [get_ports {ddr3_dq[33]}]
set_property SLEW FAST [get_ports {ddr3_dq[34]}]
set_property SLEW FAST [get_ports {ddr3_dq[35]}]
set_property SLEW FAST [get_ports {ddr3_dq[36]}]
set_property SLEW FAST [get_ports {ddr3_dq[37]}]
set_property SLEW FAST [get_ports {ddr3_dq[38]}]
set_property SLEW FAST [get_ports {ddr3_dq[39]}]
set_property SLEW FAST [get_ports {ddr3_dq[40]}]
set_property SLEW FAST [get_ports {ddr3_dq[41]}]
set_property SLEW FAST [get_ports {ddr3_dq[42]}]
set_property SLEW FAST [get_ports {ddr3_dq[43]}]
set_property SLEW FAST [get_ports {ddr3_dq[44]}]
set_property SLEW FAST [get_ports {ddr3_dq[45]}]
set_property SLEW FAST [get_ports {ddr3_dq[46]}]
set_property SLEW FAST [get_ports {ddr3_dq[47]}]
set_property SLEW FAST [get_ports {ddr3_dq[48]}]
set_property SLEW FAST [get_ports {ddr3_dq[49]}]
set_property SLEW FAST [get_ports {ddr3_dq[50]}]
set_property SLEW FAST [get_ports {ddr3_dq[51]}]
set_property SLEW FAST [get_ports {ddr3_dq[52]}]
set_property SLEW FAST [get_ports {ddr3_dq[53]}]
set_property SLEW FAST [get_ports {ddr3_dq[54]}]
set_property SLEW FAST [get_ports {ddr3_dq[55]}]
set_property SLEW FAST [get_ports {ddr3_dq[56]}]
set_property SLEW FAST [get_ports {ddr3_dq[57]}]
set_property SLEW FAST [get_ports {ddr3_dq[58]}]
set_property SLEW FAST [get_ports {ddr3_dq[59]}]
set_property SLEW FAST [get_ports {ddr3_dq[60]}]
set_property SLEW FAST [get_ports {ddr3_dq[61]}]
set_property SLEW FAST [get_ports {ddr3_dq[62]}]
set_property SLEW FAST [get_ports {ddr3_dq[63]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[0]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[1]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[2]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[3]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[4]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[5]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[6]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[7]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[8]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[9]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[10]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[11]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[12]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[13]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[14]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[15]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[16]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[17]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[18]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[19]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[20]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[21]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[22]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[23]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[24]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[25]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[26]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[27]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[28]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[29]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[30]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[31]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[32]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[33]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[34]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[35]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[36]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[37]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[38]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[39]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[40]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[41]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[42]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[43]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[44]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[45]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[46]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[47]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[48]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[49]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[50]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[51]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[52]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[53]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[54]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[55]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[56]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[57]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[58]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[59]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[60]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[61]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[62]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[63]}]
set_property LOC AK16 [get_ports {ddr3_dqs_p[0]}]
set_property LOC AM17 [get_ports {ddr3_dqs_p[1]}]
set_property LOC AP21 [get_ports {ddr3_dqs_p[2]}]
set_property LOC AH20 [get_ports {ddr3_dqs_p[3]}]
set_property LOC AK33 [get_ports {ddr3_dqs_p[4]}]
set_property LOC AG33 [get_ports {ddr3_dqs_p[5]}]
set_property LOC AE34 [get_ports {ddr3_dqs_p[6]}]
set_property LOC AE27 [get_ports {ddr3_dqs_p[7]}]
set_property LOC AK17 [get_ports {ddr3_dqs_n[0]}]
set_property LOC AM18 [get_ports {ddr3_dqs_n[1]}]
set_property LOC AP22 [get_ports {ddr3_dqs_n[2]}]
set_property LOC AJ20 [get_ports {ddr3_dqs_n[3]}]
set_property LOC AL33 [get_ports {ddr3_dqs_n[4]}]
set_property LOC AH33 [get_ports {ddr3_dqs_n[5]}]
set_property LOC AF34 [get_ports {ddr3_dqs_n[6]}]
set_property LOC AE28 [get_ports {ddr3_dqs_n[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[7]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[4]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[5]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[6]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[7]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[4]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[5]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[6]}]
set_property SLEW FAST [get_ports {ddr3_dqs_p[7]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[4]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[5]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[6]}]
set_property SLEW FAST [get_ports {ddr3_dqs_n[7]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[0]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[1]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[2]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[3]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[4]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[5]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[6]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[7]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[0]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[1]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[2]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[3]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[4]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[5]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[6]}]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[7]}]

3
rtl/ddr3_controller.v
View File

@ -87,6 +87,7 @@ module ddr3_controller #(
DLL_OFF = 0, // 1 = DLL off for low frequency ddr3 clock
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
parameter[1:0] BIST_MODE = 2, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
parameter[0:0] BIST_TEST_DATAMASK = 1, // 1 = include per-byte DM writes in BIST, 0 = all-byte writes only
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) (only change when you know what you are doing)
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
@ -3180,7 +3181,7 @@ BITSLIP_DQS_TRAIN_3: if(train_delay == 0) begin //train again the ISERDES to cap
BURST_WRITE: if(!o_wb_stall_calib) begin // Test 1: Burst write (per byte write to test datamask feature), then burst read
calib_stb <= 1'b1;
calib_aux <= 2; // write
if(TDQS == 0 && ECC_ENABLE == 0) begin //Test datamask by writing 1 byte at a time
if(BIST_TEST_DATAMASK && TDQS == 0 && ECC_ENABLE == 0) begin //Test datamask by writing 1 byte at a time
calib_sel <= 1 << write_by_byte_counter;
calib_we <= 1;
calib_addr <= write_test_address_counter;

2
rtl/ddr3_top.v
View File

@ -53,6 +53,7 @@ module ddr3_top #(
DLL_OFF = 0, // 1 = DLL off for low frequency ddr3 clock (< 125MHz)
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
parameter[1:0] BIST_MODE = 1, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
parameter[0:0] BIST_TEST_DATAMASK = 1, // 1 = include per-byte DM writes in BIST, 0 = all-byte writes only
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)
@ -263,6 +264,7 @@ ddr3_top #(
.DLL_OFF(DLL_OFF), // 1 = DLL off for low frequency ddr3 clock (< 125MHz)
.WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
.BIST_MODE(BIST_MODE), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
.BIST_TEST_DATAMASK(BIST_TEST_DATAMASK), // 1 = include per-byte DM writes in BIST, 0 = all-byte writes only
.DIC(DIC), //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms)
.RTT_NOM(RTT_NOM), //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
.DUAL_RANK_DIMM(DUAL_RANK_DIMM), // enable dual rank DIMM (1 = enable, 0 = disable)