updated simulation

2025-04-19 10:07:51 +08:00 · 2025-04-19 10:07:51 +08:00 · 08ead41fd6
parent a34a5369ec
commit 08ead41fd6
16 changed files with 278972 additions and 364170 deletions
--- a/testbench/xsim/test_10_000_ddr3_2_500_odelay_0_lanes_two_lanes_bus_delay_0_bist_2.log
+++ b/testbench/xsim/test_10_000_ddr3_2_500_odelay_0_lanes_two_lanes_bus_delay_0_bist_2.log
--- a/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_eight_lanes_bus_delay_0_bist_2.log
+++ b/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_eight_lanes_bus_delay_0_bist_2.log
--- a/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_eight_lanes_bus_delay_1_bist_1.log
+++ b/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_eight_lanes_bus_delay_1_bist_1.log
--- a/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_two_lanes_bus_delay_1_bist_1.log
+++ b/testbench/xsim/test_10_000_ddr3_2_500_odelay_1_lanes_two_lanes_bus_delay_1_bist_1.log
--- a/testbench/xsim/test_12_000_ddr3_3_000_odelay_0_lanes_two_lanes_bus_delay_0_bist_2.log
+++ b/testbench/xsim/test_12_000_ddr3_3_000_odelay_0_lanes_two_lanes_bus_delay_0_bist_2.log
--- a/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_eight_lanes_bus_delay_0_bist_2.log
+++ b/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_eight_lanes_bus_delay_0_bist_2.log
--- a/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_eight_lanes_bus_delay_1_bist_1.log
+++ b/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_eight_lanes_bus_delay_1_bist_1.log
--- a/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_two_lanes_bus_delay_1_bist_1.log
+++ b/testbench/xsim/test_12_000_ddr3_3_000_odelay_1_lanes_two_lanes_bus_delay_1_bist_1.log
--- a/testbench/xsim/test_5_000_ddr3_1_250_odelay_0_lanes_two_lanes_bus_delay_0_bist_1.log
+++ b/testbench/xsim/test_5_000_ddr3_1_250_odelay_0_lanes_two_lanes_bus_delay_0_bist_1.log
--- a/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_eight_lanes_bus_delay_0_bist_1.log
+++ b/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_eight_lanes_bus_delay_0_bist_1.log
--- a/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_eight_lanes_bus_delay_1_bist_2.log
+++ b/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_eight_lanes_bus_delay_1_bist_2.log
--- a/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_two_lanes_bus_delay_1_bist_2.log
+++ b/testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_two_lanes_bus_delay_1_bist_2.log
--- a/testbench/xsim/test_6_000_ddr3_1_500_odelay_0_lanes_two_lanes_bus_delay_0_bist_1.log
+++ b/testbench/xsim/test_6_000_ddr3_1_500_odelay_0_lanes_two_lanes_bus_delay_0_bist_1.log
--- a/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_eight_lanes_bus_delay_0_bist_1.log
+++ b/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_eight_lanes_bus_delay_0_bist_1.log
--- a/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_eight_lanes_bus_delay_1_bist_2.log
+++ b/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_eight_lanes_bus_delay_1_bist_2.log
--- a/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_two_lanes_bus_delay_1_bist_2.log
+++ b/testbench/xsim/test_6_000_ddr3_1_500_odelay_1_lanes_two_lanes_bus_delay_1_bist_2.log