Merge pull request #31 from AngeloJacobo/pass_verilator_lint
Pass verilator lint
This commit is contained in:
Angelo Jacobo
GitHub
commit
4b159fa03a
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@ -9,6 +9,15 @@ testbench/xsim/*backup*
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testbench/xsim/*.log
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testbench/xsim/*.pb
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testbench/xsim/*.wdb
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example_demo/*/build/*
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example_demo/build_logs*
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*.fasm
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*.frames
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*.bin
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*.json
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*.bba
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*toolchain-nix*
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testbench/ddr3_dimm_micron_sim_behav.wcfg
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# But do not ignore testbench/xsim/test_*.log
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!testbench/xsim/test_*.log
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@ -29,11 +29,11 @@ JTAG_LINK ?= -c digilent_hs2
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XDC ?= ${PROJECT}.xdc
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.PHONY: all
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all: ${PROJECT}.bit
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.PHONY: openxc7
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openxc7: ${PROJECT}_openxc7.bit
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.PHONY: program
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program: ${PROJECT}.bit
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program: ${PROJECT}_openxc7.bit
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openFPGALoader ${JTAG_LINK} --bitstream $<
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${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
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@ -52,18 +52,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
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${PROJECT}.frames: ${PROJECT}.fasm
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fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
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${PROJECT}.bit: ${PROJECT}.frames
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${PROJECT}_openxc7.bit: ${PROJECT}.frames
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xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
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#############################################################################################
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# SPDX-License-Identifier: MIT
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# Generated from https://github.com/FPGAOL-CE/caas-wizard
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#
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BUILDDIR := ${CURDIR}/build
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LOGFILE := ${BUILDDIR}/top.log
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# Build design
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.PHONY: vivado
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vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
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${BUILDDIR}:
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mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
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.ONESHELL:
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${BUILDDIR}/vivado.tcl: ${BUILDDIR}
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cat << EOF > $@
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# vivado.tcl generated for FPGAOL-CE/caas-wizard
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# can be launched from any directory
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cd ${BUILDDIR}
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create_project -part ${PART} -force v_proj
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set_property target_language Verilog [current_project]
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cd ..
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read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
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read_xdc [glob $(wildcard ${PROJECT}.xdc) ]
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cd build
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synth_design -top ${PROJECT}
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opt_design
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place_design
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phys_opt_design
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route_design
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write_bitstream -verbose -force ${PROJECT}_vivado.bit
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# report_utilization -file util.rpt
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# report_timing_summary -file timing.rpt
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EOF
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${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
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cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
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.PHONY: program_vivado
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program_vivado:
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openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
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#############################################################################################
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.PHONY: clean
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clean:
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@rm -f *.bit
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@rm -f *.frames
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@rm -f *.fasm
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@rm -f *.json
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@rm -f *.bin
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@rm -f *.bba
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.PHONY: pnrclean
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pnrclean:
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rm *.fasm *.frames *.bit
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rm -f *.bit
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rm -f *.frames
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rm -f *.fasm
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rm -f *.json
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rm -f *.bin
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rm -f *.bba
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rm -rf ${BUILDDIR}
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Binary file not shown.
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@ -2,13 +2,13 @@
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module clk_wiz
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(
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input clk_in1,
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output clk_out1,
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output clk_out2,
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output clk_out3,
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output clk_out4,
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input reset,
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output locked
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input wire clk_in1,
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output wire clk_out1,
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output wire clk_out2,
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output wire clk_out3,
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output wire clk_out4,
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input wire reset,
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output wire locked
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);
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wire clk_out1_clk_wiz_0;
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wire clk_out2_clk_wiz_0;
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@ -4,6 +4,7 @@ PART = xc7k325tffg900-2
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CHIPDB = ${KINTEX7_CHIPDB}
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ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v ../../rtl/ddr3_phy.v ../../rtl/ddr3_top.v uart_rx.v uart_tx.v clk_wiz.v
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#############################################################################################
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NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
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NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
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@ -25,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
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PNR_DEBUG ?= # --verbose --debug
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BOARD ?= UNKNOWN
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JTAG_LINK ?= -c digilent_hs2
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XDC ?= ${PROJECT}.xdc
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.PHONY: all
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all: ${PROJECT}.bit
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.PHONY: openxc7
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openxc7: ${PROJECT}_openxc7.bit
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.PHONY: program
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program: ${PROJECT}.bit
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program: ${PROJECT}_openxc7.bit
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openFPGALoader ${JTAG_LINK} --bitstream $<
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${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
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@ -53,18 +53,63 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
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${PROJECT}.frames: ${PROJECT}.fasm
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fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
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${PROJECT}.bit: ${PROJECT}.frames
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${PROJECT}_openxc7.bit: ${PROJECT}.frames
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xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
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#############################################################################################
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# SPDX-License-Identifier: MIT
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# Generated from https://github.com/FPGAOL-CE/caas-wizard
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#
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BUILDDIR := ${CURDIR}/build
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LOGFILE := ${BUILDDIR}/top.log
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# Build design
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.PHONY: vivado
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vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
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${BUILDDIR}:
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mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
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.ONESHELL:
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${BUILDDIR}/vivado.tcl: ${BUILDDIR}
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cat << EOF > $@
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# vivado.tcl generated for FPGAOL-CE/caas-wizard
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# can be launched from any directory
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cd ${BUILDDIR}
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create_project -part ${PART} -force v_proj
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set_property target_language Verilog [current_project]
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cd ..
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read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
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read_xdc [glob $(wildcard ${PROJECT}.xdc) ]
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cd build
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synth_design -top ${PROJECT}
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opt_design
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place_design
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phys_opt_design
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route_design
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write_bitstream -verbose -force ${PROJECT}_vivado.bit
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# report_utilization -file util.rpt
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# report_timing_summary -file timing.rpt
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EOF
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${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
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cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
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.PHONY: program_vivado
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program_vivado:
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openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
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#############################################################################################
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.PHONY: clean
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clean:
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@rm -f *.bit
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@rm -f *.frames
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@rm -f *.fasm
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@rm -f *.json
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@rm -f *.bin
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@rm -f *.bba
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.PHONY: pnrclean
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pnrclean:
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rm *.fasm *.frames *.bit
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rm -f *.bit
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rm -f *.frames
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rm -f *.fasm
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rm -f *.json
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rm -f *.bin
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rm -f *.bba
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rm -rf ${BUILDDIR}
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Binary file not shown.
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@ -2,13 +2,13 @@
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module clk_wiz
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(
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input clk_in1,
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output clk_out1,
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output clk_out2,
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output clk_out3,
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output clk_out4,
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input reset,
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output locked
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input wire clk_in1,
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output wire clk_out1,
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output wire clk_out2,
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output wire clk_out3,
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output wire clk_out4,
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input wire reset,
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output wire locked
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);
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wire clk_out1_clk_wiz_0;
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wire clk_out2_clk_wiz_0;
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@ -5,6 +5,7 @@ PART = xc7s50csga324-1
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CHIPDB = ${SPARTAN7_CHIPDB}
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ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v ../../rtl/ddr3_phy.v ../../rtl/ddr3_top.v uart_rx.v uart_tx.v clk_wiz.v
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#############################################################################################
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NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
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NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
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@ -26,16 +27,15 @@ TOP_VERILOG ?= ${TOP}.v
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PNR_DEBUG ?= # --verbose --debug
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BOARD ?= UNKNOWN
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JTAG_LINK ?= --board ${BOARD}
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XDC ?= ${PROJECT}.xdc
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.PHONY: all
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all: ${PROJECT}.bit
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.PHONY: openxc7
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openxc7: ${PROJECT}_openxc7.bit
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.PHONY: program
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program: ${PROJECT}.bit
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program: ${PROJECT}_openxc7.bit
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openFPGALoader ${JTAG_LINK} --bitstream $<
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${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
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@ -54,18 +54,63 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
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${PROJECT}.frames: ${PROJECT}.fasm
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fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
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${PROJECT}.bit: ${PROJECT}.frames
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${PROJECT}_openxc7.bit: ${PROJECT}.frames
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xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
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#############################################################################################
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# SPDX-License-Identifier: MIT
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# Generated from https://github.com/FPGAOL-CE/caas-wizard
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#
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BUILDDIR := ${CURDIR}/build
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LOGFILE := ${BUILDDIR}/top.log
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# Build design
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.PHONY: vivado
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vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
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${BUILDDIR}:
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mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
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.ONESHELL:
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${BUILDDIR}/vivado.tcl: ${BUILDDIR}
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cat << EOF > $@
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# vivado.tcl generated for FPGAOL-CE/caas-wizard
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# can be launched from any directory
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cd ${BUILDDIR}
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create_project -part ${PART} -force v_proj
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set_property target_language Verilog [current_project]
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cd ..
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read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
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read_xdc [glob $(wildcard ${PROJECT}_vivado.xdc) ]
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cd build
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synth_design -top ${PROJECT}
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opt_design
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place_design
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phys_opt_design
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route_design
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write_bitstream -verbose -force ${PROJECT}_vivado.bit
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# report_utilization -file util.rpt
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# report_timing_summary -file timing.rpt
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EOF
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${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
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cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
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.PHONY: program_vivado
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program_vivado:
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openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
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#############################################################################################
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.PHONY: clean
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clean:
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@rm -f *.bit
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@rm -f *.frames
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@rm -f *.fasm
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@rm -f *.json
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@rm -f *.bin
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@rm -f *.bba
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.PHONY: pnrclean
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pnrclean:
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rm *.fasm *.frames *.bit
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rm -f *.bit
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rm -f *.frames
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rm -f *.fasm
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rm -f *.json
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rm -f *.bin
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rm -f *.bba
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rm -rf ${BUILDDIR}
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Binary file not shown.
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@ -0,0 +1,265 @@
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## This file is a general .xdc for the Arty S7-50 Rev. E
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## To use it in a project:
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## - uncomment the lines corresponding to used pins
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## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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## Clock Signals
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set_property -dict {PACKAGE_PIN R2 IOSTANDARD SSTL135} [get_ports i_clk]
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create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk]
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## LEDs
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set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
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set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
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set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports {led[2]}]
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set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {led[3]}]
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## Buttons
|
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports i_rst]
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||||
## USB-UART Interface
|
||||
set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports tx]
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set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports rx]
|
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|
||||
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############## DDR3 ##################
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# DQ PINS
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set_property SLEW FAST [get_ports {ddr3_dq[0]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
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set_property PACKAGE_PIN K2 [get_ports {ddr3_dq[0]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[1]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}]
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||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
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set_property PACKAGE_PIN K3 [get_ports {ddr3_dq[1]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[2]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
|
||||
set_property PACKAGE_PIN L4 [get_ports {ddr3_dq[2]}]
|
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set_property SLEW FAST [get_ports {ddr3_dq[3]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
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set_property PACKAGE_PIN M6 [get_ports {ddr3_dq[3]}]
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set_property SLEW FAST [get_ports {ddr3_dq[4]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}]
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||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
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set_property PACKAGE_PIN K6 [get_ports {ddr3_dq[4]}]
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set_property SLEW FAST [get_ports {ddr3_dq[5]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
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set_property PACKAGE_PIN M4 [get_ports {ddr3_dq[5]}]
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|
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set_property SLEW FAST [get_ports {ddr3_dq[6]}]
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||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
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set_property PACKAGE_PIN L5 [get_ports {ddr3_dq[6]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[7]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
|
||||
set_property PACKAGE_PIN L6 [get_ports {ddr3_dq[7]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[8]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
|
||||
set_property PACKAGE_PIN N4 [get_ports {ddr3_dq[8]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[9]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
|
||||
set_property PACKAGE_PIN R1 [get_ports {ddr3_dq[9]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[10]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
|
||||
set_property PACKAGE_PIN N1 [get_ports {ddr3_dq[10]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[11]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
|
||||
set_property PACKAGE_PIN N5 [get_ports {ddr3_dq[11]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[12]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
|
||||
set_property PACKAGE_PIN M2 [get_ports {ddr3_dq[12]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[13]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
|
||||
set_property PACKAGE_PIN P1 [get_ports {ddr3_dq[13]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[14]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
|
||||
set_property PACKAGE_PIN M1 [get_ports {ddr3_dq[14]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[15]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
|
||||
set_property PACKAGE_PIN P2 [get_ports {ddr3_dq[15]}]
|
||||
|
||||
# Address Pins
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[13]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
|
||||
set_property PACKAGE_PIN U6 [get_ports {ddr3_addr[13]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[12]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
|
||||
set_property PACKAGE_PIN R6 [get_ports {ddr3_addr[12]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[11]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
|
||||
set_property PACKAGE_PIN T5 [get_ports {ddr3_addr[11]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[10]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
|
||||
set_property PACKAGE_PIN P6 [get_ports {ddr3_addr[10]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[9]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
|
||||
set_property PACKAGE_PIN V7 [get_ports {ddr3_addr[9]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[8]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
|
||||
set_property PACKAGE_PIN U7 [get_ports {ddr3_addr[8]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[7]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
|
||||
set_property PACKAGE_PIN T6 [get_ports {ddr3_addr[7]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[6]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
|
||||
set_property PACKAGE_PIN V6 [get_ports {ddr3_addr[6]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[5]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
|
||||
set_property PACKAGE_PIN R7 [get_ports {ddr3_addr[5]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[4]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
|
||||
set_property PACKAGE_PIN T3 [get_ports {ddr3_addr[4]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[3]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
|
||||
set_property PACKAGE_PIN V4 [get_ports {ddr3_addr[3]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[2]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
|
||||
set_property PACKAGE_PIN V2 [get_ports {ddr3_addr[2]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[1]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
|
||||
set_property PACKAGE_PIN R4 [get_ports {ddr3_addr[1]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
|
||||
set_property PACKAGE_PIN U2 [get_ports {ddr3_addr[0]}]
|
||||
|
||||
# Bank Pins
|
||||
set_property SLEW FAST [get_ports {ddr3_ba[2]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
|
||||
set_property PACKAGE_PIN U3 [get_ports {ddr3_ba[2]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_ba[1]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
|
||||
set_property PACKAGE_PIN T1 [get_ports {ddr3_ba[1]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_ba[0]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
|
||||
set_property PACKAGE_PIN V5 [get_ports {ddr3_ba[0]}]
|
||||
|
||||
# Command Pins
|
||||
set_property SLEW FAST [get_ports ddr3_ras_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
|
||||
set_property PACKAGE_PIN U1 [get_ports ddr3_ras_n]
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_cas_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
|
||||
set_property PACKAGE_PIN V3 [get_ports ddr3_cas_n]
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_we_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
|
||||
set_property PACKAGE_PIN P7 [get_ports ddr3_we_n]
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_reset_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
|
||||
set_property PACKAGE_PIN J6 [get_ports ddr3_reset_n]
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_cke]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_cke]
|
||||
set_property PACKAGE_PIN T2 [get_ports ddr3_cke]
|
||||
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_odt]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_odt]
|
||||
set_property PACKAGE_PIN P5 [get_ports ddr3_odt]
|
||||
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_cs_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n]
|
||||
set_property PACKAGE_PIN R3 [get_ports ddr3_cs_n]
|
||||
|
||||
# Data Mask Pins
|
||||
set_property SLEW FAST [get_ports {ddr3_dm[0]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
|
||||
set_property PACKAGE_PIN K4 [get_ports {ddr3_dm[0]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dm[1]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
|
||||
set_property PACKAGE_PIN M3 [get_ports {ddr3_dm[1]}]
|
||||
|
||||
# DQS Pins
|
||||
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}]
|
||||
set_property PACKAGE_PIN K1 [get_ports {ddr3_dqs_p[0]}]
|
||||
set_property PACKAGE_PIN L1 [get_ports {ddr3_dqs_n[0]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}]
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}]
|
||||
set_property PACKAGE_PIN N3 [get_ports {ddr3_dqs_p[1]}]
|
||||
set_property PACKAGE_PIN N2 [get_ports {ddr3_dqs_n[1]}]
|
||||
|
||||
# Clock Pins
|
||||
set_property SLEW FAST [get_ports ddr3_clk_p]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_p]
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_clk_n]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_n]
|
||||
set_property PACKAGE_PIN R5 [get_ports ddr3_clk_p]
|
||||
set_property PACKAGE_PIN T4 [get_ports ddr3_clk_n]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
|
||||
## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as
|
||||
## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage
|
||||
## and to be able to use this pin as an ordinary I/O the following property must
|
||||
## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
|
||||
## used the internal reference is set to half that value (i.e. 0.675v). Note that
|
||||
## this property must be set even if SW3 is not used in the design.
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
|
||||
|
||||
|
|
@ -2,13 +2,13 @@
|
|||
|
||||
module clk_wiz
|
||||
(
|
||||
input clk_in1,
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
input reset,
|
||||
output locked
|
||||
input wire clk_in1,
|
||||
output wire clk_out1,
|
||||
output wire clk_out2,
|
||||
output wire clk_out3,
|
||||
output wire clk_out4,
|
||||
input wire reset,
|
||||
output wire locked
|
||||
);
|
||||
wire clk_out1_clk_wiz_0;
|
||||
wire clk_out2_clk_wiz_0;
|
||||
|
|
|
|||
|
|
@ -26,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
|
|||
|
||||
PNR_DEBUG ?= # --verbose --debug
|
||||
|
||||
BOARD ?= UNKNOWN
|
||||
JTAG_LINK ?= --board ${BOARD}
|
||||
JTAG_LINK ?= -c digilent_hs2
|
||||
|
||||
XDC ?= ${PROJECT}.xdc
|
||||
|
||||
.PHONY: all
|
||||
all: ${PROJECT}.bit
|
||||
.PHONY: openxc7
|
||||
openxc7: ${PROJECT}_openxc7.bit
|
||||
|
||||
.PHONY: program
|
||||
program: ${PROJECT}.bit
|
||||
program: ${PROJECT}_openxc7.bit
|
||||
openFPGALoader ${JTAG_LINK} --bitstream $<
|
||||
|
||||
${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
|
||||
|
|
@ -54,18 +53,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
|
|||
${PROJECT}.frames: ${PROJECT}.fasm
|
||||
fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
|
||||
|
||||
${PROJECT}.bit: ${PROJECT}.frames
|
||||
${PROJECT}_openxc7.bit: ${PROJECT}.frames
|
||||
xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
|
||||
|
||||
|
||||
#############################################################################################
|
||||
# SPDX-License-Identifier: MIT
|
||||
# Generated from https://github.com/FPGAOL-CE/caas-wizard
|
||||
#
|
||||
BUILDDIR := ${CURDIR}/build
|
||||
|
||||
LOGFILE := ${BUILDDIR}/top.log
|
||||
|
||||
# Build design
|
||||
.PHONY: vivado
|
||||
vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
|
||||
|
||||
${BUILDDIR}:
|
||||
mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
|
||||
|
||||
.ONESHELL:
|
||||
${BUILDDIR}/vivado.tcl: ${BUILDDIR}
|
||||
cat << EOF > $@
|
||||
# vivado.tcl generated for FPGAOL-CE/caas-wizard
|
||||
# can be launched from any directory
|
||||
cd ${BUILDDIR}
|
||||
create_project -part ${PART} -force v_proj
|
||||
set_property target_language Verilog [current_project]
|
||||
cd ..
|
||||
read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
|
||||
read_xdc [glob $(wildcard ${PROJECT}.xdc) ]
|
||||
cd build
|
||||
synth_design -top ${PROJECT}
|
||||
opt_design
|
||||
place_design
|
||||
phys_opt_design
|
||||
route_design
|
||||
write_bitstream -verbose -force ${PROJECT}_vivado.bit
|
||||
# report_utilization -file util.rpt
|
||||
# report_timing_summary -file timing.rpt
|
||||
EOF
|
||||
|
||||
${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
|
||||
cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
|
||||
|
||||
.PHONY: program_vivado
|
||||
program_vivado:
|
||||
openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
|
||||
|
||||
#############################################################################################
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
@rm -f *.bit
|
||||
@rm -f *.frames
|
||||
@rm -f *.fasm
|
||||
@rm -f *.json
|
||||
@rm -f *.bin
|
||||
@rm -f *.bba
|
||||
|
||||
.PHONY: pnrclean
|
||||
pnrclean:
|
||||
rm *.fasm *.frames *.bit
|
||||
rm -f *.bit
|
||||
rm -f *.frames
|
||||
rm -f *.fasm
|
||||
rm -f *.json
|
||||
rm -f *.bin
|
||||
rm -f *.bba
|
||||
rm -rf ${BUILDDIR}
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@
|
|||
|
||||
module clk_wiz
|
||||
(
|
||||
input clk_in1,
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
output clk_out5,
|
||||
input reset,
|
||||
output locked
|
||||
input wire clk_in1,
|
||||
output wire clk_out1,
|
||||
output wire clk_out2,
|
||||
output wire clk_out3,
|
||||
output wire clk_out4,
|
||||
output wire clk_out5,
|
||||
input wire reset,
|
||||
output wire locked
|
||||
);
|
||||
wire clk_out1_clk_wiz_0;
|
||||
wire clk_out2_clk_wiz_0;
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -4,6 +4,7 @@ PART = xc7a200tsbg484-1
|
|||
CHIPDB = ${ARTIX7_CHIPDB}
|
||||
ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v ../../rtl/ddr3_phy.v ../../rtl/ddr3_top.v uart_rx.v uart_tx.v clk_wiz.v
|
||||
|
||||
|
||||
#############################################################################################
|
||||
NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
|
||||
NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
|
||||
|
|
@ -25,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
|
|||
|
||||
PNR_DEBUG ?= # --verbose --debug
|
||||
|
||||
BOARD ?= UNKNOWN
|
||||
JTAG_LINK ?= --board ${BOARD}
|
||||
JTAG_LINK ?= -c digilent_hs2
|
||||
|
||||
XDC ?= ${PROJECT}.xdc
|
||||
|
||||
.PHONY: all
|
||||
all: ${PROJECT}.bit
|
||||
.PHONY: openxc7
|
||||
openxc7: ${PROJECT}_openxc7.bit
|
||||
|
||||
.PHONY: program
|
||||
program: ${PROJECT}.bit
|
||||
program: ${PROJECT}_openxc7.bit
|
||||
openFPGALoader ${JTAG_LINK} --bitstream $<
|
||||
|
||||
${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
|
||||
|
|
@ -53,18 +53,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
|
|||
${PROJECT}.frames: ${PROJECT}.fasm
|
||||
fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
|
||||
|
||||
${PROJECT}.bit: ${PROJECT}.frames
|
||||
${PROJECT}_openxc7.bit: ${PROJECT}.frames
|
||||
xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
|
||||
|
||||
|
||||
#############################################################################################
|
||||
# SPDX-License-Identifier: MIT
|
||||
# Generated from https://github.com/FPGAOL-CE/caas-wizard
|
||||
#
|
||||
BUILDDIR := ${CURDIR}/build
|
||||
|
||||
LOGFILE := ${BUILDDIR}/top.log
|
||||
|
||||
# Build design
|
||||
.PHONY: vivado
|
||||
vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
|
||||
|
||||
${BUILDDIR}:
|
||||
mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
|
||||
|
||||
.ONESHELL:
|
||||
${BUILDDIR}/vivado.tcl: ${BUILDDIR}
|
||||
cat << EOF > $@
|
||||
# vivado.tcl generated for FPGAOL-CE/caas-wizard
|
||||
# can be launched from any directory
|
||||
cd ${BUILDDIR}
|
||||
create_project -part ${PART} -force v_proj
|
||||
set_property target_language Verilog [current_project]
|
||||
cd ..
|
||||
read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
|
||||
read_xdc [glob $(wildcard ${PROJECT}.xdc) ]
|
||||
cd build
|
||||
synth_design -top ${PROJECT}
|
||||
opt_design
|
||||
place_design
|
||||
phys_opt_design
|
||||
route_design
|
||||
write_bitstream -verbose -force ${PROJECT}_vivado.bit
|
||||
# report_utilization -file util.rpt
|
||||
# report_timing_summary -file timing.rpt
|
||||
EOF
|
||||
|
||||
${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
|
||||
cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
|
||||
|
||||
.PHONY: program_vivado
|
||||
program_vivado:
|
||||
openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
|
||||
|
||||
#############################################################################################
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
@rm -f *.bit
|
||||
@rm -f *.frames
|
||||
@rm -f *.fasm
|
||||
@rm -f *.json
|
||||
@rm -f *.bin
|
||||
@rm -f *.bba
|
||||
|
||||
.PHONY: pnrclean
|
||||
pnrclean:
|
||||
rm *.fasm *.frames *.bit
|
||||
rm -f *.bit
|
||||
rm -f *.frames
|
||||
rm -f *.fasm
|
||||
rm -f *.json
|
||||
rm -f *.bin
|
||||
rm -f *.bba
|
||||
rm -rf ${BUILDDIR}
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
|
||||
module clk_wiz
|
||||
(
|
||||
input clk_in1,
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
input reset,
|
||||
output locked
|
||||
input wire clk_in1,
|
||||
output wire clk_out1,
|
||||
output wire clk_out2,
|
||||
output wire clk_out3,
|
||||
output wire clk_out4,
|
||||
input wire reset,
|
||||
output wire locked
|
||||
);
|
||||
wire clk_out1_clk_wiz_0;
|
||||
wire clk_out2_clk_wiz_0;
|
||||
|
|
|
|||
|
|
@ -216,9 +216,7 @@
|
|||
.io_ddr3_dqs_n(ddr3_dqs_n),
|
||||
.o_ddr3_dm(ddr3_dm),
|
||||
.o_ddr3_odt(ddr3_odt), // on-die termination
|
||||
.o_debug1(o_debug1),
|
||||
.o_debug2(o_debug2),
|
||||
.o_debug3()
|
||||
.o_debug1(o_debug1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
|
|
@ -4,6 +4,7 @@ PART = xc7k325tffg676-1
|
|||
CHIPDB = ${KINTEX7_CHIPDB}
|
||||
ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v ../../rtl/ddr3_phy.v ../../rtl/ddr3_top.v uart_rx.v uart_tx.v clk_wiz.v
|
||||
|
||||
|
||||
#############################################################################################
|
||||
NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
|
||||
NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
|
||||
|
|
@ -25,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
|
|||
|
||||
PNR_DEBUG ?= # --verbose --debug
|
||||
|
||||
BOARD ?= UNKNOWN
|
||||
JTAG_LINK ?= -c digilent_hs2
|
||||
|
||||
XDC ?= ${PROJECT}.xdc
|
||||
|
||||
.PHONY: all
|
||||
all: ${PROJECT}.bit
|
||||
.PHONY: openxc7
|
||||
openxc7: ${PROJECT}_openxc7.bit
|
||||
|
||||
.PHONY: program
|
||||
program: ${PROJECT}.bit
|
||||
program: ${PROJECT}_openxc7.bit
|
||||
openFPGALoader ${JTAG_LINK} --bitstream $<
|
||||
|
||||
${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
|
||||
|
|
@ -53,18 +53,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
|
|||
${PROJECT}.frames: ${PROJECT}.fasm
|
||||
fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
|
||||
|
||||
${PROJECT}.bit: ${PROJECT}.frames
|
||||
${PROJECT}_openxc7.bit: ${PROJECT}.frames
|
||||
xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
|
||||
|
||||
|
||||
#############################################################################################
|
||||
# SPDX-License-Identifier: MIT
|
||||
# Generated from https://github.com/FPGAOL-CE/caas-wizard
|
||||
#
|
||||
BUILDDIR := ${CURDIR}/build
|
||||
|
||||
LOGFILE := ${BUILDDIR}/top.log
|
||||
|
||||
# Build design
|
||||
.PHONY: vivado
|
||||
vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
|
||||
|
||||
${BUILDDIR}:
|
||||
mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
|
||||
|
||||
.ONESHELL:
|
||||
${BUILDDIR}/vivado.tcl: ${BUILDDIR}
|
||||
cat << EOF > $@
|
||||
# vivado.tcl generated for FPGAOL-CE/caas-wizard
|
||||
# can be launched from any directory
|
||||
cd ${BUILDDIR}
|
||||
create_project -part ${PART} -force v_proj
|
||||
set_property target_language Verilog [current_project]
|
||||
cd ..
|
||||
read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
|
||||
read_xdc [glob $(wildcard ${PROJECT}.xdc) ]
|
||||
cd build
|
||||
synth_design -top ${PROJECT}
|
||||
opt_design
|
||||
place_design
|
||||
phys_opt_design
|
||||
route_design
|
||||
write_bitstream -verbose -force ${PROJECT}_vivado.bit
|
||||
# report_utilization -file util.rpt
|
||||
# report_timing_summary -file timing.rpt
|
||||
EOF
|
||||
|
||||
${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
|
||||
cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
|
||||
|
||||
.PHONY: program_vivado
|
||||
program_vivado:
|
||||
openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
|
||||
|
||||
#############################################################################################
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
@rm -f *.bit
|
||||
@rm -f *.frames
|
||||
@rm -f *.fasm
|
||||
@rm -f *.json
|
||||
@rm -f *.bin
|
||||
@rm -f *.bba
|
||||
|
||||
.PHONY: pnrclean
|
||||
pnrclean:
|
||||
rm *.fasm *.frames *.bit
|
||||
rm -f *.bit
|
||||
rm -f *.frames
|
||||
rm -f *.fasm
|
||||
rm -f *.json
|
||||
rm -f *.bin
|
||||
rm -f *.bba
|
||||
rm -rf ${BUILDDIR}
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
|
||||
module clk_wiz
|
||||
(
|
||||
input clk_in1,
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
input reset,
|
||||
output locked
|
||||
input wire clk_in1,
|
||||
output wire clk_out1,
|
||||
output wire clk_out2,
|
||||
output wire clk_out3,
|
||||
output wire clk_out4,
|
||||
input wire reset,
|
||||
output wire locked
|
||||
);
|
||||
wire clk_out1_clk_wiz_0;
|
||||
wire clk_out2_clk_wiz_0;
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -26,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
|
|||
|
||||
PNR_DEBUG ?= # --verbose --debug
|
||||
|
||||
BOARD ?= UNKNOWN
|
||||
JTAG_LINK ?= -c digilent_hs2
|
||||
|
||||
XDC ?= ${PROJECT}.xdc
|
||||
|
||||
.PHONY: all
|
||||
all: ${PROJECT}.bit
|
||||
.PHONY: openxc7
|
||||
openxc7: ${PROJECT}_openxc7.bit
|
||||
|
||||
.PHONY: program
|
||||
program: ${PROJECT}.bit
|
||||
program: ${PROJECT}_openxc7.bit
|
||||
openFPGALoader ${JTAG_LINK} --bitstream $<
|
||||
|
||||
${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
|
||||
|
|
@ -54,18 +53,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
|
|||
${PROJECT}.frames: ${PROJECT}.fasm
|
||||
fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
|
||||
|
||||
${PROJECT}.bit: ${PROJECT}.frames
|
||||
${PROJECT}_openxc7.bit: ${PROJECT}.frames
|
||||
xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
|
||||
|
||||
|
||||
#############################################################################################
|
||||
# SPDX-License-Identifier: MIT
|
||||
# Generated from https://github.com/FPGAOL-CE/caas-wizard
|
||||
#
|
||||
BUILDDIR := ${CURDIR}/build
|
||||
|
||||
LOGFILE := ${BUILDDIR}/top.log
|
||||
|
||||
# Build design
|
||||
.PHONY: vivado
|
||||
vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
|
||||
|
||||
${BUILDDIR}:
|
||||
mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
|
||||
|
||||
.ONESHELL:
|
||||
${BUILDDIR}/vivado.tcl: ${BUILDDIR}
|
||||
cat << EOF > $@
|
||||
# vivado.tcl generated for FPGAOL-CE/caas-wizard
|
||||
# can be launched from any directory
|
||||
cd ${BUILDDIR}
|
||||
create_project -part ${PART} -force v_proj
|
||||
set_property target_language Verilog [current_project]
|
||||
cd ..
|
||||
read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
|
||||
read_xdc [glob $(wildcard ${PROJECT}_vivado.xdc) ]
|
||||
cd build
|
||||
synth_design -top ${PROJECT}
|
||||
opt_design
|
||||
place_design
|
||||
phys_opt_design
|
||||
route_design
|
||||
write_bitstream -verbose -force ${PROJECT}_vivado.bit
|
||||
# report_utilization -file util.rpt
|
||||
# report_timing_summary -file timing.rpt
|
||||
EOF
|
||||
|
||||
${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
|
||||
cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
|
||||
|
||||
.PHONY: program_vivado
|
||||
program_vivado:
|
||||
openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
|
||||
|
||||
#############################################################################################
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
@rm -f *.bit
|
||||
@rm -f *.frames
|
||||
@rm -f *.fasm
|
||||
@rm -f *.json
|
||||
@rm -f *.bin
|
||||
@rm -f *.bba
|
||||
|
||||
.PHONY: pnrclean
|
||||
pnrclean:
|
||||
rm *.fasm *.frames *.bit
|
||||
rm -f *.bit
|
||||
rm -f *.frames
|
||||
rm -f *.fasm
|
||||
rm -f *.json
|
||||
rm -f *.bin
|
||||
rm -f *.bba
|
||||
rm -rf ${BUILDDIR}
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
|
||||
module clk_wiz
|
||||
(
|
||||
input clk_in1,
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
input reset,
|
||||
output locked
|
||||
input wire clk_in1,
|
||||
output wire clk_out1,
|
||||
output wire clk_out2,
|
||||
output wire clk_out3,
|
||||
output wire clk_out4,
|
||||
input wire reset,
|
||||
output wire locked
|
||||
);
|
||||
wire clk_out1_clk_wiz_0;
|
||||
wire clk_out2_clk_wiz_0;
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -0,0 +1,537 @@
|
|||
## Clock Signals
|
||||
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports i_clk]
|
||||
create_clock -period 20.000 -name sys_clk_pin -waveform {0.000 10.000} -add [get_ports i_clk]
|
||||
|
||||
## Reset
|
||||
set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS33} [get_ports i_rst_n]
|
||||
|
||||
## LEDs
|
||||
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
|
||||
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
|
||||
|
||||
## DDR3
|
||||
# PadFunction: IO_L18N_T2_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[0]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
|
||||
|
||||
set_property PACKAGE_PIN D21 [get_ports {ddr3_dq[0]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L16P_T2_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[1]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
|
||||
|
||||
set_property PACKAGE_PIN C21 [get_ports {ddr3_dq[1]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L17P_T2_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[2]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
|
||||
|
||||
set_property PACKAGE_PIN B22 [get_ports {ddr3_dq[2]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L16N_T2_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[3]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
|
||||
|
||||
set_property PACKAGE_PIN B21 [get_ports {ddr3_dq[3]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L13P_T2_MRCC_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[4]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
|
||||
|
||||
set_property PACKAGE_PIN D19 [get_ports {ddr3_dq[4]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L14P_T2_SRCC_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[5]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
|
||||
|
||||
set_property PACKAGE_PIN E20 [get_ports {ddr3_dq[5]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L13N_T2_MRCC_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[6]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
|
||||
|
||||
set_property PACKAGE_PIN C19 [get_ports {ddr3_dq[6]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L14N_T2_SRCC_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[7]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
|
||||
|
||||
set_property PACKAGE_PIN D20 [get_ports {ddr3_dq[7]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L19N_T3_VREF_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[8]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
|
||||
|
||||
set_property PACKAGE_PIN C23 [get_ports {ddr3_dq[8]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L24P_T3_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[9]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
|
||||
|
||||
set_property PACKAGE_PIN D23 [get_ports {ddr3_dq[9]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L23N_T3_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[10]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
|
||||
|
||||
set_property PACKAGE_PIN B24 [get_ports {ddr3_dq[10]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L20P_T3_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[11]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
|
||||
|
||||
set_property PACKAGE_PIN B25 [get_ports {ddr3_dq[11]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L23P_T3_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[12]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
|
||||
|
||||
set_property PACKAGE_PIN C24 [get_ports {ddr3_dq[12]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L22P_T3_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[13]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
|
||||
|
||||
set_property PACKAGE_PIN C26 [get_ports {ddr3_dq[13]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L20N_T3_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[14]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
|
||||
|
||||
set_property PACKAGE_PIN A25 [get_ports {ddr3_dq[14]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L22N_T3_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dq[15]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
|
||||
|
||||
set_property PACKAGE_PIN B26 [get_ports {ddr3_dq[15]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L4P_T0_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[13]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
|
||||
|
||||
set_property PACKAGE_PIN G15 [get_ports {ddr3_addr[13]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L12N_T1_MRCC_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[12]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
|
||||
|
||||
set_property PACKAGE_PIN C18 [get_ports {ddr3_addr[12]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L1N_T0_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[11]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
|
||||
|
||||
set_property PACKAGE_PIN H15 [get_ports {ddr3_addr[11]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L5N_T0_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[10]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
|
||||
|
||||
set_property PACKAGE_PIN F20 [get_ports {ddr3_addr[10]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L4N_T0_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[9]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
|
||||
|
||||
set_property PACKAGE_PIN F15 [get_ports {ddr3_addr[9]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L1P_T0_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[8]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
|
||||
|
||||
set_property PACKAGE_PIN H14 [get_ports {ddr3_addr[8]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L8P_T1_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[7]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
|
||||
|
||||
set_property PACKAGE_PIN E16 [get_ports {ddr3_addr[7]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L6P_T0_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[6]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
|
||||
|
||||
set_property PACKAGE_PIN H16 [get_ports {ddr3_addr[6]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L8N_T1_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[5]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
|
||||
|
||||
set_property PACKAGE_PIN D16 [get_ports {ddr3_addr[5]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L6N_T0_VREF_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[4]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
|
||||
|
||||
set_property PACKAGE_PIN G16 [get_ports {ddr3_addr[4]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L7P_T1_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[3]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
|
||||
|
||||
set_property PACKAGE_PIN C17 [get_ports {ddr3_addr[3]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L2N_T0_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[2]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
|
||||
|
||||
set_property PACKAGE_PIN F17 [get_ports {ddr3_addr[2]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L2P_T0_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[1]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
|
||||
|
||||
set_property PACKAGE_PIN G17 [get_ports {ddr3_addr[1]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L11P_T1_SRCC_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
|
||||
|
||||
set_property PACKAGE_PIN E17 [get_ports {ddr3_addr[0]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L9P_T1_DQS_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_ba[2]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
|
||||
|
||||
set_property PACKAGE_PIN A17 [get_ports {ddr3_ba[2]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L12P_T1_MRCC_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_ba[1]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
|
||||
|
||||
set_property PACKAGE_PIN D18 [get_ports {ddr3_ba[1]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L7N_T1_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_ba[0]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
|
||||
|
||||
set_property PACKAGE_PIN B17 [get_ports {ddr3_ba[0]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L10N_T1_16
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_ras_n]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
|
||||
|
||||
set_property PACKAGE_PIN A19 [get_ports ddr3_ras_n]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L10P_T1_16
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_cas_n]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
|
||||
|
||||
set_property PACKAGE_PIN B19 [get_ports ddr3_cas_n]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L9N_T1_DQS_16
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_we_n]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
|
||||
|
||||
set_property PACKAGE_PIN A18 [get_ports ddr3_we_n]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_0_16
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_reset_n]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
|
||||
|
||||
set_property PACKAGE_PIN H17 [get_ports ddr3_reset_n]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L11N_T1_SRCC_16
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_cke]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_cke]
|
||||
|
||||
set_property PACKAGE_PIN E18 [get_ports ddr3_cke]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L5P_T0_16
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_odt]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_odt]
|
||||
|
||||
set_property PACKAGE_PIN G19 [get_ports ddr3_odt]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L17N_T2_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dm[0]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
|
||||
|
||||
set_property PACKAGE_PIN A22 [get_ports {ddr3_dm[0]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L19P_T3_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dm[1]}]
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
|
||||
|
||||
set_property PACKAGE_PIN C22 [get_ports {ddr3_dm[1]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L15P_T2_DQS_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}]
|
||||
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}]
|
||||
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L15N_T2_DQS_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}]
|
||||
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}]
|
||||
|
||||
set_property PACKAGE_PIN B20 [get_ports {ddr3_dqs_p[0]}]
|
||||
set_property PACKAGE_PIN A20 [get_ports {ddr3_dqs_n[0]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L21P_T3_DQS_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}]
|
||||
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}]
|
||||
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L21N_T3_DQS_16
|
||||
|
||||
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
|
||||
|
||||
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}]
|
||||
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}]
|
||||
|
||||
set_property PACKAGE_PIN A23 [get_ports {ddr3_dqs_p[1]}]
|
||||
set_property PACKAGE_PIN A24 [get_ports {ddr3_dqs_n[1]}]
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L3P_T0_DQS_16
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_clk_p]
|
||||
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_p]
|
||||
|
||||
|
||||
|
||||
|
||||
# PadFunction: IO_L3N_T0_DQS_16
|
||||
|
||||
set_property SLEW FAST [get_ports ddr3_clk_n]
|
||||
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_n]
|
||||
|
||||
set_property PACKAGE_PIN F18 [get_ports ddr3_clk_p]
|
||||
set_property PACKAGE_PIN F19 [get_ports ddr3_clk_n]
|
||||
|
||||
|
||||
|
||||
## UART
|
||||
set_property PACKAGE_PIN F3 [get_ports rx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports rx]
|
||||
set_property PACKAGE_PIN E3 [get_ports tx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports tx]
|
||||
|
||||
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 16]
|
||||
# set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
|
||||
|
||||
# ## Place the IOSERDES_train manually (else the tool will place this blocks which can block the route for CLKB0 (OBUFDS for ddr3_clk_p))
|
||||
# set_property LOC OLOGIC_X0Y91 [get_cells {ddr3_top/ddr3_phy_inst/genblk5[1].OSERDESE2_train}]
|
||||
# set_property LOC ILOGIC_X0Y94 [get_cells {ddr3_top/ddr3_phy_inst/genblk5[0].ISERDESE2_train}]
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#!/bin/bash
|
||||
|
||||
# Create a logs directory to store all log files
|
||||
rm -rf build_logs
|
||||
mkdir -p build_logs
|
||||
|
||||
# Loop through each item in the current directory
|
||||
for dir in */; do
|
||||
# Check if it's a directory and contains a Makefile
|
||||
if [ -d "$dir" ] && [ -f "$dir/Makefile" ]; then
|
||||
log_file="build_logs/${dir%/}.log"
|
||||
echo "Building $dir... Logging to $log_file"
|
||||
{
|
||||
echo "===== $(date) - Building $dir ====="
|
||||
cd "$dir"
|
||||
make clean
|
||||
make
|
||||
echo ""
|
||||
echo "DONE OPENXC7"
|
||||
echo ""
|
||||
echo ""
|
||||
make vivado
|
||||
echo ""
|
||||
echo "DONE VIVADO"
|
||||
echo ""
|
||||
echo ""
|
||||
cd ..
|
||||
echo "===== Finished $dir ====="
|
||||
} &> "$log_file"
|
||||
else
|
||||
echo "Skipping $dir (no Makefile found)"
|
||||
fi
|
||||
done
|
||||
|
|
@ -4,6 +4,7 @@ PART = xc7a35tftg256-2
|
|||
CHIPDB = ${ARTIX7_CHIPDB}
|
||||
ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v ../../rtl/ddr3_phy.v ../../rtl/ddr3_top.v uart_rx.v uart_tx.v clk_wiz.v
|
||||
|
||||
|
||||
#############################################################################################
|
||||
NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
|
||||
NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
|
||||
|
|
@ -25,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
|
|||
|
||||
PNR_DEBUG ?= # --verbose --debug
|
||||
|
||||
BOARD ?= UNKNOWN
|
||||
JTAG_LINK ?= --board ${BOARD}
|
||||
JTAG_LINK ?= -c digilent_hs2
|
||||
|
||||
XDC ?= ${PROJECT}.xdc
|
||||
|
||||
.PHONY: all
|
||||
all: ${PROJECT}.bit
|
||||
.PHONY: openxc7
|
||||
openxc7: ${PROJECT}_openxc7.bit
|
||||
|
||||
.PHONY: program
|
||||
program: ${PROJECT}.bit
|
||||
program: ${PROJECT}_openxc7.bit
|
||||
openFPGALoader ${JTAG_LINK} --bitstream $<
|
||||
|
||||
${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
|
||||
|
|
@ -53,17 +53,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
|
|||
${PROJECT}.frames: ${PROJECT}.fasm
|
||||
fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
|
||||
|
||||
${PROJECT}.bit: ${PROJECT}.frames
|
||||
${PROJECT}_openxc7.bit: ${PROJECT}.frames
|
||||
xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
|
||||
|
||||
|
||||
#############################################################################################
|
||||
# SPDX-License-Identifier: MIT
|
||||
# Generated from https://github.com/FPGAOL-CE/caas-wizard
|
||||
#
|
||||
BUILDDIR := ${CURDIR}/build
|
||||
|
||||
LOGFILE := ${BUILDDIR}/top.log
|
||||
|
||||
# Build design
|
||||
.PHONY: vivado
|
||||
vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
|
||||
|
||||
${BUILDDIR}:
|
||||
mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
|
||||
|
||||
.ONESHELL:
|
||||
${BUILDDIR}/vivado.tcl: ${BUILDDIR}
|
||||
cat << EOF > $@
|
||||
# vivado.tcl generated for FPGAOL-CE/caas-wizard
|
||||
# can be launched from any directory
|
||||
cd ${BUILDDIR}
|
||||
create_project -part ${PART} -force v_proj
|
||||
set_property target_language Verilog [current_project]
|
||||
cd ..
|
||||
read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
|
||||
read_xdc [glob $(wildcard ${PROJECT}.xdc) ]
|
||||
cd build
|
||||
synth_design -top ${PROJECT}
|
||||
opt_design
|
||||
place_design
|
||||
phys_opt_design
|
||||
route_design
|
||||
write_bitstream -verbose -force ${PROJECT}_vivado.bit
|
||||
# report_utilization -file util.rpt
|
||||
# report_timing_summary -file timing.rpt
|
||||
EOF
|
||||
|
||||
${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
|
||||
cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
|
||||
|
||||
.PHONY: program_vivado
|
||||
program_vivado:
|
||||
openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
|
||||
|
||||
#############################################################################################
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
@rm -f *.frames
|
||||
@rm -f *.fasm
|
||||
@rm -f *.json
|
||||
@rm -f *.bin
|
||||
@rm -f *.bba
|
||||
|
||||
.PHONY: pnrclean
|
||||
pnrclean:
|
||||
rm *.fasm *.frames *.bit
|
||||
rm -f *.bit
|
||||
rm -f *.frames
|
||||
rm -f *.fasm
|
||||
rm -f *.json
|
||||
rm -f *.bin
|
||||
rm -f *.bba
|
||||
rm -rf ${BUILDDIR}
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
|
||||
module clk_wiz
|
||||
(
|
||||
input clk_in1,
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
input reset,
|
||||
output locked
|
||||
input wire clk_in1,
|
||||
output wire clk_out1,
|
||||
output wire clk_out2,
|
||||
output wire clk_out3,
|
||||
output wire clk_out4,
|
||||
input wire reset,
|
||||
output wire locked
|
||||
);
|
||||
wire clk_out1_clk_wiz_0;
|
||||
wire clk_out2_clk_wiz_0;
|
||||
|
|
|
|||
|
|
@ -207,9 +207,7 @@
|
|||
.io_ddr3_dqs_n(ddr3_dqs_n),
|
||||
.o_ddr3_dm(ddr3_dm),
|
||||
.o_ddr3_odt(ddr3_odt), // on-die termination
|
||||
.o_debug1(o_debug1),
|
||||
.o_debug2(),
|
||||
.o_debug3()
|
||||
.o_debug1(o_debug1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
|
|
@ -67,7 +67,7 @@ module ddr3_controller #(
|
|||
COL_BITS = 10, //width of DDR3 column address
|
||||
BA_BITS = 3, //width of bank address
|
||||
DQ_BITS = 8, //device width
|
||||
LANES = 2, //number of DDR3 device to be controlled
|
||||
LANES = 8, //number of DDR3 device to be controlled
|
||||
AUX_WIDTH = 16, //width of aux line (must be >= 4)
|
||||
WB2_ADDR_BITS = 7, //width of 2nd wishbone address bus
|
||||
WB2_DATA_BITS = 32, //width of 2nd wishbone data bus
|
||||
|
|
@ -401,7 +401,7 @@ module ddr3_controller #(
|
|||
localparam[18:0] MR3_MPR_DIS = {MR3_SEL, 13'b0_0000_0000_0000, !MPR_EN, MPR_LOC};
|
||||
|
||||
// MR1 (JEDEC DDR3 doc pg. 27)
|
||||
localparam DLL_EN = DLL_OFF? 1'b0 : 1'b1; //DLL Enable/Disable: Enabled(0)
|
||||
localparam DLL_EN = DLL_OFF? 1'b1 : 1'b0; //DLL Enable/Disable: Enabled(0)
|
||||
// localparam[1:0] DIC = 2'b01; //Output Driver Impedance Control (RZQ/7) (elevate this to parameter)
|
||||
// localparam[2:0] RTT_NOM = 3'b001; //RTT Nominal: RZQ/4 (elevate this to parameter)
|
||||
localparam[0:0] WL_EN = 1'b1; //Write Leveling Enable: Disabled
|
||||
|
|
@ -649,6 +649,7 @@ module ddr3_controller #(
|
|||
reg[1:0] shift_read_pipe = 0;
|
||||
reg[wb_data_bits-1:0] wrong_data = 0, expected_data=0;
|
||||
wire[wb_data_bits-1:0] correct_data;
|
||||
reg[LANES-1:0] late_dq;
|
||||
// initial block for all regs
|
||||
initial begin
|
||||
o_wb_stall = 1;
|
||||
|
|
@ -1235,13 +1236,13 @@ module ddr3_controller #(
|
|||
stage2_data[index+1] <= stage2_data[index]; // 0->1, 1->2
|
||||
stage2_dm[index+1] <= stage2_dm[index];
|
||||
end
|
||||
|
||||
|
||||
for(index = 0; index < LANES; index = index + 1) begin
|
||||
/* verilator lint_off WIDTH */
|
||||
// if DQ is too late (298cd0ad51c1XXXX is written) then we want to DQ to be early
|
||||
// Thus, we will forward the stage2_data_unaligned directly to stage2_data[1] (instead of the usual stage2_data[0])
|
||||
// checks if the DQ for this lane is late (index being zero while write_dq_late high means we will try 2nd assumption), if yes then we forward stage2_data_unaligned directly to stage2_data[1]
|
||||
if((lane_write_dq_late[index] && (data_start_index[index] != 0)) && (STAGE2_DATA_DEPTH > 1)) begin
|
||||
if(late_dq[index]) begin
|
||||
{unaligned_data[index], {
|
||||
stage2_data[1][((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data[1][((DQ_BITS*LANES)*6 + 8*index) +: 8],
|
||||
stage2_data[1][((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data[1][((DQ_BITS*LANES)*4 + 8*index) +: 8],
|
||||
|
|
@ -1266,8 +1267,10 @@ module ddr3_controller #(
|
|||
<< (data_start_index[index]>>3)) | unaligned_dm[index];
|
||||
/* verilator lint_on WIDTH */
|
||||
end // end of if statement (dq for this lane is late)
|
||||
|
||||
else begin // DQ is not late so we will forward stage2_data_unaligned to stage2_data[0]
|
||||
end // end of for loop to forward stage2_unaligned to stage2 by lane
|
||||
|
||||
for(index = 0; index < LANES; index = index + 1) begin
|
||||
if(!late_dq[index]) begin // DQ is not late so we will forward stage2_data_unaligned to stage2_data[0]
|
||||
/* verilator lint_off WIDTH */
|
||||
// stage2_data_unaligned is the DQ_BITS*LANES*8 raw data from stage 1 so not yet aligned
|
||||
// unaligned_data is 64 bits
|
||||
|
|
@ -1333,6 +1336,11 @@ module ddr3_controller #(
|
|||
end
|
||||
end
|
||||
end
|
||||
always @* begin
|
||||
for(index = 0; index < LANES; index = index + 1) begin
|
||||
late_dq[index] = (lane_write_dq_late[index] && (data_start_index[index] != 0)) && (STAGE2_DATA_DEPTH > 1);
|
||||
end
|
||||
end
|
||||
|
||||
// generate signals to be received by stage1
|
||||
generate
|
||||
|
|
@ -2870,7 +2878,12 @@ module ddr3_controller #(
|
|||
state_calibrate <= CHECK_STARTING_DATA;
|
||||
`ifdef UART_DEBUG_ALIGN
|
||||
uart_start_send <= 1'b1;
|
||||
uart_text <= {"state=ANALYZE_DATA, lane=",hex_to_ascii(lane), ", First Assumption wrong, Start second assumption: Read too early",8'h0a,8'h0a};
|
||||
uart_text <= {"state=ANALYZE_DATA, lane=",hex_to_ascii(lane), ", First Assumption wrong, Start second assumption: Read too early",8'h0a,8'h0a,
|
||||
8'h0a,8'h0a,
|
||||
{read_data_store[((DQ_BITS*LANES)*7 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*6 + 8*lane) +: 8],
|
||||
read_data_store[((DQ_BITS*LANES)*5 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*4 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*3 + 8*lane) +: 8],
|
||||
read_data_store[((DQ_BITS*LANES)*2 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*1 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*0 + 8*lane) +: 8] },
|
||||
8'h0a,8'h0a,8'h0a,8'h0a};
|
||||
state_calibrate <= WAIT_UART;
|
||||
state_calibrate_next <= CHECK_STARTING_DATA;
|
||||
`endif
|
||||
|
|
@ -2895,7 +2908,12 @@ module ddr3_controller #(
|
|||
else begin
|
||||
uart_start_send <= 1'b1;
|
||||
uart_text <= {"state=ANALYZE_DATA, lane=",hex_to_ascii(lane), ", data_start_index[lane]=0x",
|
||||
hex_to_ascii(data_start_index[lane][6:4]),hex_to_ascii(data_start_index[lane][3:0]),8'h0a};
|
||||
hex_to_ascii(data_start_index[lane][6:4]),hex_to_ascii(data_start_index[lane][3:0]),8'h0a,8'h0a,8'h0a,8'h0a,
|
||||
{read_data_store[((DQ_BITS*LANES)*7 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*6 + 8*lane) +: 8],
|
||||
read_data_store[((DQ_BITS*LANES)*5 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*4 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*3 + 8*lane) +: 8],
|
||||
read_data_store[((DQ_BITS*LANES)*2 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*1 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*0 + 8*lane) +: 8] },
|
||||
8'h0a,8'h0a,8'h0a,8'h0a
|
||||
};
|
||||
state_calibrate <= WAIT_UART;
|
||||
state_calibrate_next <= ANALYZE_DATA;
|
||||
end
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ module ddr3_dimm_micron_sim;
|
|||
TEST_SELF_REFRESH = 0,
|
||||
SECOND_WISHBONE = 0,
|
||||
BIST_MODE = 2, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
|
||||
DLL_OFF = 1;
|
||||
DLL_OFF = 0;
|
||||
|
||||
reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
|
||||
reg i_rst_n;
|
||||
|
|
|
|||
|
|
@ -1,805 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="ddr3_dimm_micron_sim_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="ddr3_dimm_micron_sim" />
|
||||
<top_module name="glbl" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="60.369478 us"></ZoomStartTime>
|
||||
<ZoomEndTime time="168.769479 us"></ZoomEndTime>
|
||||
<Cursor1Time time="150.702812 us"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="272"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="113"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="69" />
|
||||
<wave_markers>
|
||||
<marker label="" time="37605000" />
|
||||
<marker label="" time="37825000" />
|
||||
<marker label="" time="35865000" />
|
||||
</wave_markers>
|
||||
<wvobject fp_name="divider869" type="divider">
|
||||
<obj_property name="label">Clocks and Reset</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_rst_n">
|
||||
<obj_property name="ElementShortName">i_rst_n</obj_property>
|
||||
<obj_property name="ObjectShortName">i_rst_n</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_controller_clk">
|
||||
<obj_property name="ElementShortName">i_controller_clk</obj_property>
|
||||
<obj_property name="ObjectShortName">i_controller_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ddr3_clk">
|
||||
<obj_property name="ElementShortName">i_ddr3_clk</obj_property>
|
||||
<obj_property name="ObjectShortName">i_ddr3_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ddr3_clk_90">
|
||||
<obj_property name="ElementShortName">i_ddr3_clk_90</obj_property>
|
||||
<obj_property name="ObjectShortName">i_ddr3_clk_90</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ref_clk">
|
||||
<obj_property name="ElementShortName">i_ref_clk</obj_property>
|
||||
<obj_property name="ObjectShortName">i_ref_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_rst_n">
|
||||
<obj_property name="ElementShortName">i_rst_n</obj_property>
|
||||
<obj_property name="ObjectShortName">i_rst_n</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/sync_rst">
|
||||
<obj_property name="ElementShortName">sync_rst</obj_property>
|
||||
<obj_property name="ObjectShortName">sync_rst</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider869" type="divider">
|
||||
<obj_property name="label">Self-refresh</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/i_user_self_refresh">
|
||||
<obj_property name="ElementShortName">i_user_self_refresh</obj_property>
|
||||
<obj_property name="ObjectShortName">i_user_self_refresh</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/user_self_refresh_q">
|
||||
<obj_property name="ElementShortName">user_self_refresh_q</obj_property>
|
||||
<obj_property name="ObjectShortName">user_self_refresh_q</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cke">
|
||||
<obj_property name="ElementShortName">o_ddr3_cke[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_cke[0:0]</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/refresh_counter">
|
||||
<obj_property name="ElementShortName">refresh_counter[8:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">refresh_counter[8:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_wb_stall">
|
||||
<obj_property name="ElementShortName">o_wb_stall</obj_property>
|
||||
<obj_property name="ObjectShortName">o_wb_stall</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_stb">
|
||||
<obj_property name="ElementShortName">i_wb_stb</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_stb</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/cmd_ck_en">
|
||||
<obj_property name="ElementShortName">cmd_ck_en[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">cmd_ck_en[0:0]</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/cmd_ck_en[0]">
|
||||
<obj_property name="ElementShortName">[0]</obj_property>
|
||||
<obj_property name="ObjectShortName">[0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF0080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/prev_cmd_ck_en">
|
||||
<obj_property name="ElementShortName">prev_cmd_ck_en[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">prev_cmd_ck_en[0:0]</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/prev_cmd_ck_en[0]">
|
||||
<obj_property name="ElementShortName">[0]</obj_property>
|
||||
<obj_property name="ObjectShortName">[0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd">
|
||||
<obj_property name="ElementShortName">i_controller_cmd[103:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">i_controller_cmd[103:0]</obj_property>
|
||||
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|
||||
<obj_property name="ObjectShortName">[39]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[38]">
|
||||
<obj_property name="ElementShortName">[38]</obj_property>
|
||||
<obj_property name="ObjectShortName">[38]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[37]">
|
||||
<obj_property name="ElementShortName">[37]</obj_property>
|
||||
<obj_property name="ObjectShortName">[37]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[36]">
|
||||
<obj_property name="ElementShortName">[36]</obj_property>
|
||||
<obj_property name="ObjectShortName">[36]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[35]">
|
||||
<obj_property name="ElementShortName">[35]</obj_property>
|
||||
<obj_property name="ObjectShortName">[35]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[34]">
|
||||
<obj_property name="ElementShortName">[34]</obj_property>
|
||||
<obj_property name="ObjectShortName">[34]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[33]">
|
||||
<obj_property name="ElementShortName">[33]</obj_property>
|
||||
<obj_property name="ObjectShortName">[33]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[32]">
|
||||
<obj_property name="ElementShortName">[32]</obj_property>
|
||||
<obj_property name="ObjectShortName">[32]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[31]">
|
||||
<obj_property name="ElementShortName">[31]</obj_property>
|
||||
<obj_property name="ObjectShortName">[31]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[30]">
|
||||
<obj_property name="ElementShortName">[30]</obj_property>
|
||||
<obj_property name="ObjectShortName">[30]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[29]">
|
||||
<obj_property name="ElementShortName">[29]</obj_property>
|
||||
<obj_property name="ObjectShortName">[29]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[28]">
|
||||
<obj_property name="ElementShortName">[28]</obj_property>
|
||||
<obj_property name="ObjectShortName">[28]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[27]">
|
||||
<obj_property name="ElementShortName">[27]</obj_property>
|
||||
<obj_property name="ObjectShortName">[27]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[26]">
|
||||
<obj_property name="ElementShortName">[26]</obj_property>
|
||||
<obj_property name="ObjectShortName">[26]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[25]">
|
||||
<obj_property name="ElementShortName">[25]</obj_property>
|
||||
<obj_property name="ObjectShortName">[25]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[24]">
|
||||
<obj_property name="ElementShortName">[24]</obj_property>
|
||||
<obj_property name="ObjectShortName">[24]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[23]">
|
||||
<obj_property name="ElementShortName">[23]</obj_property>
|
||||
<obj_property name="ObjectShortName">[23]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[22]">
|
||||
<obj_property name="ElementShortName">[22]</obj_property>
|
||||
<obj_property name="ObjectShortName">[22]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[21]">
|
||||
<obj_property name="ElementShortName">[21]</obj_property>
|
||||
<obj_property name="ObjectShortName">[21]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[20]">
|
||||
<obj_property name="ElementShortName">[20]</obj_property>
|
||||
<obj_property name="ObjectShortName">[20]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF00FF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[19]">
|
||||
<obj_property name="ElementShortName">[19]</obj_property>
|
||||
<obj_property name="ObjectShortName">[19]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[18]">
|
||||
<obj_property name="ElementShortName">[18]</obj_property>
|
||||
<obj_property name="ObjectShortName">[18]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[17]">
|
||||
<obj_property name="ElementShortName">[17]</obj_property>
|
||||
<obj_property name="ObjectShortName">[17]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[16]">
|
||||
<obj_property name="ElementShortName">[16]</obj_property>
|
||||
<obj_property name="ObjectShortName">[16]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[15]">
|
||||
<obj_property name="ElementShortName">[15]</obj_property>
|
||||
<obj_property name="ObjectShortName">[15]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[14]">
|
||||
<obj_property name="ElementShortName">[14]</obj_property>
|
||||
<obj_property name="ObjectShortName">[14]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[13]">
|
||||
<obj_property name="ElementShortName">[13]</obj_property>
|
||||
<obj_property name="ObjectShortName">[13]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[12]">
|
||||
<obj_property name="ElementShortName">[12]</obj_property>
|
||||
<obj_property name="ObjectShortName">[12]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[11]">
|
||||
<obj_property name="ElementShortName">[11]</obj_property>
|
||||
<obj_property name="ObjectShortName">[11]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[10]">
|
||||
<obj_property name="ElementShortName">[10]</obj_property>
|
||||
<obj_property name="ObjectShortName">[10]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[9]">
|
||||
<obj_property name="ElementShortName">[9]</obj_property>
|
||||
<obj_property name="ObjectShortName">[9]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[8]">
|
||||
<obj_property name="ElementShortName">[8]</obj_property>
|
||||
<obj_property name="ObjectShortName">[8]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[7]">
|
||||
<obj_property name="ElementShortName">[7]</obj_property>
|
||||
<obj_property name="ObjectShortName">[7]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[6]">
|
||||
<obj_property name="ElementShortName">[6]</obj_property>
|
||||
<obj_property name="ObjectShortName">[6]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[5]">
|
||||
<obj_property name="ElementShortName">[5]</obj_property>
|
||||
<obj_property name="ObjectShortName">[5]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[4]">
|
||||
<obj_property name="ElementShortName">[4]</obj_property>
|
||||
<obj_property name="ObjectShortName">[4]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[3]">
|
||||
<obj_property name="ElementShortName">[3]</obj_property>
|
||||
<obj_property name="ObjectShortName">[3]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[2]">
|
||||
<obj_property name="ElementShortName">[2]</obj_property>
|
||||
<obj_property name="ObjectShortName">[2]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[1]">
|
||||
<obj_property name="ElementShortName">[1]</obj_property>
|
||||
<obj_property name="ObjectShortName">[1]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[0]">
|
||||
<obj_property name="ElementShortName">[0]</obj_property>
|
||||
<obj_property name="ObjectShortName">[0]</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider869" type="divider">
|
||||
<obj_property name="label">Calibration</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/odelay_cntvalue_halfway">
|
||||
<obj_property name="ElementShortName">odelay_cntvalue_halfway</obj_property>
|
||||
<obj_property name="ObjectShortName">odelay_cntvalue_halfway</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/write_level_fail">
|
||||
<obj_property name="ElementShortName">write_level_fail[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">write_level_fail[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/prev_write_level_feedback">
|
||||
<obj_property name="ElementShortName">prev_write_level_feedback</obj_property>
|
||||
<obj_property name="ObjectShortName">prev_write_level_feedback</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/stored_write_level_feedback">
|
||||
<obj_property name="ElementShortName">stored_write_level_feedback</obj_property>
|
||||
<obj_property name="ObjectShortName">stored_write_level_feedback</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/sample_clk_repeat">
|
||||
<obj_property name="ElementShortName">sample_clk_repeat[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">sample_clk_repeat[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/initial_calibration_done">
|
||||
<obj_property name="ElementShortName">initial_calibration_done</obj_property>
|
||||
<obj_property name="ObjectShortName">initial_calibration_done</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/state_calibrate">
|
||||
<obj_property name="ElementShortName">state_calibrate[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">state_calibrate[4:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/instruction_address">
|
||||
<obj_property name="ElementShortName">instruction_address[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">instruction_address[4:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/calibration_state">
|
||||
<obj_property name="ElementShortName">calibration_state[319:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">calibration_state[319:0]</obj_property>
|
||||
<obj_property name="Radix">ASCIIRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/command_used">
|
||||
<obj_property name="ElementShortName">command_used[23:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">command_used[23:0]</obj_property>
|
||||
<obj_property name="Radix">ASCIIRADIX</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFD700</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/o_phy_odelay_dqs_cntvaluein">
|
||||
<obj_property name="ElementShortName">o_phy_odelay_dqs_cntvaluein[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_phy_odelay_dqs_cntvaluein[4:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/o_phy_idelay_dqs_cntvaluein">
|
||||
<obj_property name="ElementShortName">o_phy_idelay_dqs_cntvaluein[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_phy_idelay_dqs_cntvaluein[4:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ddr3_clk">
|
||||
<obj_property name="ElementShortName">i_ddr3_clk</obj_property>
|
||||
<obj_property name="ObjectShortName">i_ddr3_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_clk_n">
|
||||
<obj_property name="ElementShortName">o_ddr3_clk_n[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_clk_n[0:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_clk_p">
|
||||
<obj_property name="ElementShortName">o_ddr3_clk_p[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_clk_p[0:0]</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_clk_p[0]">
|
||||
<obj_property name="ElementShortName">[0]</obj_property>
|
||||
<obj_property name="ObjectShortName">[0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF0080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs">
|
||||
<obj_property name="ElementShortName">io_ddr3_dqs[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">io_ddr3_dqs[7:0]</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[7]">
|
||||
<obj_property name="ElementShortName">[7]</obj_property>
|
||||
<obj_property name="ObjectShortName">[7]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[6]">
|
||||
<obj_property name="ElementShortName">[6]</obj_property>
|
||||
<obj_property name="ObjectShortName">[6]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[5]">
|
||||
<obj_property name="ElementShortName">[5]</obj_property>
|
||||
<obj_property name="ObjectShortName">[5]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[4]">
|
||||
<obj_property name="ElementShortName">[4]</obj_property>
|
||||
<obj_property name="ObjectShortName">[4]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[3]">
|
||||
<obj_property name="ElementShortName">[3]</obj_property>
|
||||
<obj_property name="ObjectShortName">[3]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[2]">
|
||||
<obj_property name="ElementShortName">[2]</obj_property>
|
||||
<obj_property name="ObjectShortName">[2]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[1]">
|
||||
<obj_property name="ElementShortName">[1]</obj_property>
|
||||
<obj_property name="ObjectShortName">[1]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFFF00</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[0]">
|
||||
<obj_property name="ElementShortName">[0]</obj_property>
|
||||
<obj_property name="ObjectShortName">[0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF0080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs_n">
|
||||
<obj_property name="ElementShortName">io_ddr3_dqs_n[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">io_ddr3_dqs_n[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dq">
|
||||
<obj_property name="ElementShortName">io_ddr3_dq[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">io_ddr3_dq[63:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/idelay_dqs">
|
||||
<obj_property name="ElementShortName">idelay_dqs[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">idelay_dqs[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/lane">
|
||||
<obj_property name="ElementShortName">lane[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">lane[2:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF00FF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/instruction_address">
|
||||
<obj_property name="ElementShortName">instruction_address[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">instruction_address[4:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/read_test_address_counter">
|
||||
<obj_property name="ElementShortName">read_test_address_counter[25:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">read_test_address_counter[25:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/write_test_address_counter">
|
||||
<obj_property name="ElementShortName">write_test_address_counter[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">write_test_address_counter[31:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/correct_read_data">
|
||||
<obj_property name="ElementShortName">correct_read_data[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">correct_read_data[31:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/wrong_read_data">
|
||||
<obj_property name="ElementShortName">wrong_read_data[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">wrong_read_data[31:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider869" type="divider">
|
||||
<obj_property name="label">WIshbone Interface</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_controller_clk">
|
||||
<obj_property name="ElementShortName">i_controller_clk</obj_property>
|
||||
<obj_property name="ObjectShortName">i_controller_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/calibration_state">
|
||||
<obj_property name="ElementShortName">calibration_state[319:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">calibration_state[319:0]</obj_property>
|
||||
<obj_property name="Radix">ASCIIRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_cyc">
|
||||
<obj_property name="ElementShortName">i_wb_cyc</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_cyc</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_stb">
|
||||
<obj_property name="ElementShortName">i_wb_stb</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_stb</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_we">
|
||||
<obj_property name="ElementShortName">i_wb_we</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_we</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_addr">
|
||||
<obj_property name="ElementShortName">i_wb_addr[25:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_addr[25:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_data">
|
||||
<obj_property name="ElementShortName">i_wb_data[511:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_data[511:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_sel">
|
||||
<obj_property name="ElementShortName">i_wb_sel[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_sel[63:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_wb_stall">
|
||||
<obj_property name="ElementShortName">o_wb_stall</obj_property>
|
||||
<obj_property name="ObjectShortName">o_wb_stall</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_wb_ack">
|
||||
<obj_property name="ElementShortName">o_wb_ack</obj_property>
|
||||
<obj_property name="ObjectShortName">o_wb_ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_wb_data">
|
||||
<obj_property name="ElementShortName">o_wb_data[511:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_wb_data[511:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider869" type="divider">
|
||||
<obj_property name="label">DDR3 Interface</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cke">
|
||||
<obj_property name="ElementShortName">o_ddr3_cke[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_cke[0:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cs_n">
|
||||
<obj_property name="ElementShortName">o_ddr3_cs_n[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_cs_n[0:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_ras_n">
|
||||
<obj_property name="ElementShortName">o_ddr3_ras_n</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_ras_n</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cas_n">
|
||||
<obj_property name="ElementShortName">o_ddr3_cas_n</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_cas_n</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_we_n">
|
||||
<obj_property name="ElementShortName">o_ddr3_we_n</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_we_n</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_addr">
|
||||
<obj_property name="ElementShortName">o_ddr3_addr[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_addr[15:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_ba_addr">
|
||||
<obj_property name="ElementShortName">o_ddr3_ba_addr[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_ba_addr[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dq">
|
||||
<obj_property name="ElementShortName">io_ddr3_dq[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">io_ddr3_dq[63:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs">
|
||||
<obj_property name="ElementShortName">io_ddr3_dqs[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">io_ddr3_dqs[7:0]</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs_n">
|
||||
<obj_property name="ElementShortName">io_ddr3_dqs_n[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">io_ddr3_dqs_n[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_dm">
|
||||
<obj_property name="ElementShortName">o_ddr3_dm[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_dm[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_odt">
|
||||
<obj_property name="ElementShortName">o_ddr3_odt[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_ddr3_odt[0:0]</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue