 Hunter Nichols
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eaf285639a
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Added debug measurements along main delay paths in SRAM. WIP.
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2020-11-17 12:43:17 -08:00 |
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Hunter Nichols
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84ba5c55d1
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Merged with dev
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2020-11-10 15:47:56 -08:00 |
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 mrg
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56c2222c2b
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Temp comment Magic GDS filter code.
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2020-11-10 13:37:18 -08:00 |
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mrg
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57e708a6e1
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Add 200 cycles. Can be commented out or run for shorter.
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2020-11-09 15:20:36 -08:00 |
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mrg
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2c203530ad
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Merge branch 'drclvs' into dev
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2020-11-09 14:36:36 -08:00 |
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mrg
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0ba2feee53
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Fix errors in new run_sim calls and corners
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2020-11-09 13:59:46 -08:00 |
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mrg
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e31cbeaa6f
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Don't check for file to determine if it is included.
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2020-11-09 12:11:47 -08:00 |
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mrg
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532492d5ae
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Output functional stimulus to output directory.
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2020-11-09 12:00:25 -08:00 |
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mrg
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31d21e169f
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Skip LEF test as correct output keeps changing.
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2020-11-09 11:14:55 -08:00 |
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mrg
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10542d6cc3
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Output DRC and LVS run files to output directory.
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2020-11-09 11:12:31 -08:00 |
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mrg
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66633a843b
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Add PDK layer names to tech file
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2020-11-09 09:10:43 -08:00 |
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mrg
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2da9c307db
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Disable 4x16 decoder test for now
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2020-11-06 13:50:04 -08:00 |
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mrg
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147649e142
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Why was single port decoder test a dual port?
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2020-11-06 12:21:30 -08:00 |
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mrg
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493c9125f1
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Read different modules overrides for different num ports
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2020-11-06 11:09:50 -08:00 |
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mrg
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8be1436d51
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Use OPTS.bitcell everywhere
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2020-11-05 16:55:08 -08:00 |
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mrg
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18d2987805
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Cleanup
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2020-11-05 16:30:15 -08:00 |
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mrg
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a40716dd48
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Cleanup imports
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2020-11-05 14:32:08 -08:00 |
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mrg
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0118b73eec
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Cleanup imports
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2020-11-05 14:31:53 -08:00 |
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mrg
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681b3a91aa
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Drop to debug in debug module when -d
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2020-11-05 13:20:54 -08:00 |
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mrg
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2c76a2680f
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Adjust openram options.
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
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2020-11-05 13:12:26 -08:00 |
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mrg
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a52aac5f31
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Add gds flatten option for Magic
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2020-11-05 13:12:08 -08:00 |
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mrg
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ce7be7466f
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Model as subckt for Magic too
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2020-11-05 13:11:36 -08:00 |
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mrg
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b160c4a35d
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-11-04 14:31:42 -08:00 |
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mrg
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9a38f7a5f4
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Enable gds readonly in Magic DRC/LVS
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2020-11-04 10:50:53 -08:00 |
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mrg
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fb0b285652
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-11-04 10:40:20 -08:00 |
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mrg
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6e12d4d46c
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Skip tri gate array test
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2020-11-04 06:57:51 -08:00 |
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Matt Guthaus
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844b850b74
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Fix typo in 1w_1r bitcell
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2020-11-03 17:14:45 -08:00 |
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mrg
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3315fe32ba
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Improve nominal corner message
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2020-11-03 16:49:49 -08:00 |
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mrg
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45cdecdea9
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Improve error message about missing DRC/LVS tools.
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2020-11-03 15:47:04 -08:00 |
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mrg
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6335bc3784
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Do not drop to pdb shell when verbose
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2020-11-03 15:46:46 -08:00 |
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mrg
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29f4ee492b
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Fix missing imports in replica bitcells.
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2020-11-03 15:24:44 -08:00 |
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mrg
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2f12c77668
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Create single port memory config examples.
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2020-11-03 14:42:56 -08:00 |
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mrg
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fb9956fe96
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Fix missing include
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2020-11-03 13:50:45 -08:00 |
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mrg
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d209e8d9a3
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Disable perimeter pins for now
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2020-11-03 13:35:34 -08:00 |
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mrg
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1de545fc8e
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Fix row and col cap custom names by adding default.
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2020-11-03 13:32:15 -08:00 |
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mrg
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29ac541b28
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Refactor dynamic cell name to utilize base class
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2020-11-03 13:18:46 -08:00 |
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mrg
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a128e0501e
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Use cell_name in col and row caps too.
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2020-11-03 12:10:18 -08:00 |
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mrg
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1890385be1
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Use custom cells when needed.
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2020-11-03 11:58:25 -08:00 |
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mrg
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87419bd640
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Fix bitcell and pbitcell with different cell names
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2020-11-03 11:30:40 -08:00 |
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mrg
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cb3e9517bb
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Use cell_properties to override cell names
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2020-11-03 07:06:01 -08:00 |
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mrg
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da721a677d
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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mrg
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8c4584daa1
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Missing import fix.
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2020-11-03 06:09:42 -08:00 |
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mrg
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aec5865d71
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Fix base class error
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2020-11-02 17:41:14 -08:00 |
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mrg
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f9787eb878
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Use bitcell_base for all bitcells. Fix missing setup_bitcell call
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2020-11-02 17:00:15 -08:00 |
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mrg
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fa89b73ef8
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PR from mithro + other changable GDS file names
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2020-11-02 16:00:16 -08:00 |
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mrg
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1caecf5a69
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Undo version and traceback
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2020-11-02 10:44:49 -08:00 |
|
 Tim 'mithro' Ansell
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bb164d915d
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Allow overriding the cell size layer name.
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2020-11-02 10:03:52 -08:00 |
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Tim 'mithro' Ansell
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232f754c73
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Adding traceback printing to tech file import.
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2020-11-02 09:52:00 -08:00 |
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Tim 'mithro' Ansell
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95d77119c7
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Add caches to GDS related functions in utils.py
* Cache the GDS reader.
* Cache the properties (size / pins / etc) measured from the GDS files.
Signed-off-by: Tim 'mithro' Ansell <[email protected]>
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2020-11-02 09:52:00 -08:00 |
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Tim 'mithro' Ansell
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6514bcb4c1
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Use default bitcell name if one isn't provided.
Signed-off-by: Tim 'mithro' Ansell <[email protected]>
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2020-11-02 09:52:00 -08:00 |
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