OpenRAM/compiler
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
..
base Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
bitcells Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
characterizer Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
custom Use custom cells when needed. 2020-11-03 11:58:25 -08:00
datasheet Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
drc Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
example_configs Fixed nominal_corner_only parameter. 2020-10-30 15:52:07 -07:00
gdsMill Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
modules Use custom cells when needed. 2020-11-03 11:58:25 -08:00
pgates Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
riscv single port progess 2020-09-14 18:11:38 -07:00
router Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
sram Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
tests Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
verify Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
Makefile Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
debug.py DRC/LVS and errors fixes. 2020-06-30 07:16:05 -07:00
gen_stimulus.py Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
globals.py Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
openram.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
options.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram_factory.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
view_profile.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00