OpenRAM/compiler
Tim 'mithro' Ansell 232f754c73 Adding traceback printing to tech file import. 2020-11-02 09:52:00 -08:00
..
base Add caches to GDS related functions in utils.py 2020-11-02 09:52:00 -08:00
bitcells Use default bitcell name if one isn't provided. 2020-11-02 09:52:00 -08:00
characterizer Require either device models or device library. Remove sky130 flag. 2020-10-23 14:07:26 -07:00
custom move sky130 specific stuff to tech module lib 2020-10-13 04:48:10 -07:00
datasheet Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
drc PEP8 cleanup 2020-04-15 11:24:28 -07:00
example_configs Fixed nominal_corner_only parameter. 2020-10-30 15:52:07 -07:00
gdsMill Search all shapes for boundary rather than specify structure 2020-10-08 14:04:19 -07:00
modules Fix copy pasta: decoder to predecode 2020-10-28 15:46:10 -07:00
pgates Fix spice model bin parameter error 2020-10-28 10:39:54 -07:00
riscv single port progess 2020-09-14 18:11:38 -07:00
router Names in skiptests changed. Reduce grid router verbosity. 2020-10-23 09:22:59 -07:00
sram Allow 16-way column mux 2020-10-06 16:27:02 -07:00
tests Names in skiptests changed. Reduce grid router verbosity. 2020-10-23 09:22:59 -07:00
verify Initial pex sram test. 2020-10-02 13:32:52 -07:00
Makefile Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
debug.py DRC/LVS and errors fixes. 2020-06-30 07:16:05 -07:00
gen_stimulus.py Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
globals.py Adding traceback printing to tech file import. 2020-11-02 09:52:00 -08:00
openram.py Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
options.py Add load/slew scale option to config files 2020-10-16 13:52:36 -07:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram_factory.py Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
view_profile.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00