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base
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Fix typo in 1w_1r bitcell
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2020-11-03 17:14:45 -08:00 |
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bitcells
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Fix missing imports in replica bitcells.
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2020-11-03 15:24:44 -08:00 |
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characterizer
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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custom
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Use custom cells when needed.
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2020-11-03 11:58:25 -08:00 |
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datasheet
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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drc
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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example_configs
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Create single port memory config examples.
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2020-11-03 14:42:56 -08:00 |
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gdsMill
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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modules
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Use custom cells when needed.
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2020-11-03 11:58:25 -08:00 |
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pgates
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Model as subckt for Magic too
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2020-11-05 13:11:36 -08:00 |
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riscv
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single port progess
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2020-09-14 18:11:38 -07:00 |
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router
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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sram
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Refactor dynamic cell name to utilize base class
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2020-11-03 13:18:46 -08:00 |
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tests
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-11-04 10:40:20 -08:00 |
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verify
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Enable gds readonly in Magic DRC/LVS
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2020-11-04 10:50:53 -08:00 |
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Makefile
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Clean up Makefile for unit tests
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2018-12-05 12:58:10 -08:00 |
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debug.py
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Do not drop to pdb shell when verbose
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2020-11-03 15:46:46 -08:00 |
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gen_stimulus.py
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Fixed errors in extra rows characterization
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2020-03-22 20:54:49 +00:00 |
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globals.py
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Improve nominal corner message
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2020-11-03 16:49:49 -08:00 |
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openram.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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options.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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run_profile.sh
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Convert pin map to a set for faster membership.
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2019-04-01 15:45:44 -07:00 |
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sram_factory.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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view_profile.py
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Remove some flake8 errors/warnings.
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2019-10-02 23:26:02 +00:00 |
ce7be7466f