OpenRAM/compiler
mrg e31cbeaa6f Don't check for file to determine if it is included. 2020-11-09 12:11:47 -08:00
..
base Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
bitcells Fix missing imports in replica bitcells. 2020-11-03 15:24:44 -08:00
characterizer Don't check for file to determine if it is included. 2020-11-09 12:11:47 -08:00
custom Use custom cells when needed. 2020-11-03 11:58:25 -08:00
datasheet Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
drc Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
example_configs Create single port memory config examples. 2020-11-03 14:42:56 -08:00
gdsMill Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
modules Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
pgates Read different modules overrides for different num ports 2020-11-06 11:09:50 -08:00
riscv single port progess 2020-09-14 18:11:38 -07:00
router Adjust openram options. 2020-11-05 13:12:26 -08:00
sram Output functional stimulus to output directory. 2020-11-09 12:00:25 -08:00
tests Output functional stimulus to output directory. 2020-11-09 12:00:25 -08:00
verify Output DRC and LVS run files to output directory. 2020-11-09 11:12:31 -08:00
Makefile Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
debug.py Cleanup imports 2020-11-05 14:32:08 -08:00
gen_stimulus.py Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
globals.py Read different modules overrides for different num ports 2020-11-06 11:09:50 -08:00
openram.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
options.py Adjust openram options. 2020-11-05 13:12:26 -08:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram_factory.py Read different modules overrides for different num ports 2020-11-06 11:09:50 -08:00
view_profile.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00