mrg 45cdecdea9 Improve error message about missing DRC/LVS tools.

2020-11-03 15:47:04 -08:00

..

base

Fix row and col cap custom names by adding default.

2020-11-03 13:32:15 -08:00

bitcells

Fix missing imports in replica bitcells.

2020-11-03 15:24:44 -08:00

characterizer

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

custom

Use custom cells when needed.

2020-11-03 11:58:25 -08:00

datasheet

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

drc

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

example_configs

Create single port memory config examples.

2020-11-03 14:42:56 -08:00

gdsMill

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

modules

Use custom cells when needed.

2020-11-03 11:58:25 -08:00

pgates

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

riscv

single port progess

2020-09-14 18:11:38 -07:00

router

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

sram

Refactor dynamic cell name to utilize base class

2020-11-03 13:18:46 -08:00

tests

Refactor dynamic cell name to utilize base class

2020-11-03 13:18:46 -08:00

verify

Improve error message about missing DRC/LVS tools.

2020-11-03 15:47:04 -08:00

debug.py

Do not drop to pdb shell when verbose

2020-11-03 15:46:46 -08:00

gen_stimulus.py

Fixed errors in extra rows characterization

2020-03-22 20:54:49 +00:00

globals.py

Improve error message about missing DRC/LVS tools.

2020-11-03 15:47:04 -08:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

options.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

run_profile.sh

Convert pin map to a set for faster membership.

2019-04-01 15:45:44 -07:00

sram_factory.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

view_profile.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00