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OpenRAM
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451 Commits

Author SHA1 Message Date
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg 5bff641c0a Multiport constants can't be static 2020-10-27 09:28:21 -07:00
mrg 575f504e4b Remove static method call 2020-10-27 09:26:40 -07:00
mrg 07ef43eaf8 Convert design class data to static 2020-10-27 09:23:11 -07:00
mrg f23fe07893 Add custom layers without defaults 2020-10-26 16:37:00 -07:00
mrg b45a7902c0 PEP8 cleanup 2020-10-26 13:13:38 -07:00
mrg fcb7f42e48 Remove split_wl 2020-10-12 17:27:20 -07:00
mrg 3c2e8754e0 Search all shapes for boundary rather than specify structure 2020-10-08 14:04:19 -07:00
jcirimel d40c3588ed no wl for col end 2020-10-08 03:34:16 -07:00
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00
mrg 27d921d2db Fix run-time bug for duplicate instance check 2020-10-06 16:26:35 -07:00
jcirimel 888646cdf9 merge in wlbuf and begin work on 32kb memory 2020-10-06 05:03:59 -07:00
mrg b81cdab0d6 Use unique instance names for channel routes. 2020-10-01 07:43:06 -07:00
mrg bd125e2ed3 Check for duplicate instance names. 2020-10-01 07:17:16 -07:00
mrg 0c280e062a Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
mrg 4b5bbe755f PEP8 cleanup. Fix cur_slew bug. 2020-09-29 11:13:58 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 4a987bef9a Merge branch 'wlbuffer' into dev 2020-09-28 15:51:45 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
jcirimel 7f8edf6d7c fix replica bitcell col 2020-09-23 00:36:08 -07:00
jcirimel efdc171b14 make split wl specific to each port 2020-09-23 00:08:34 -07:00
jcirimel fb6a665514 removed references to technology name 2020-09-22 18:33:03 -07:00
mrg c7d32089f3 Create RBL wordline buffer with correct polarity. 2020-09-17 14:45:49 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
mrg 71d86f88b0 Merge branch 'dev' into wlbuffer 2020-09-10 13:05:14 -07:00
mrg 8e91ec1770 Add check_pins function 2020-09-08 13:31:50 -07:00
Hunter Nichols 8bcbf005bf Merge branch 'dev' into characterizer_bug_fixes 2020-09-04 02:25:01 -07:00
Hunter Nichols 13b1d4613c Moved spice naming checking code from design to the spice base module 2020-08-31 14:36:13 -07:00
mrg c1c1535210 Merge branch 'wlbuffer' into dev 2020-08-27 15:44:29 -07:00
Hunter Nichols 42f2ff679e Removed dead code from delay and base module related to characterization 2020-08-27 15:40:41 -07:00
mrg 11a82b7283 Fixed local bitcell array for single and dual port 2020-08-27 14:03:05 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
jcirimel 714b57d48e Merge branch 'dev' into pex 2020-08-17 17:48:21 -07:00
mrg 3a692e2846 Comment updates 2020-08-17 14:35:39 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 2ccf3aea3b Set channel route height and width (of routes, not pins) 2020-07-20 13:25:47 -07:00
mrg f87b427f76 Add parent to channel route for dumpign debug gds. 2020-07-20 12:03:25 -07:00
mrg 7385decbff Add channel route cyclic VCG debugging. 2020-07-20 12:02:30 -07:00
mrg 9d5d632d1a Pins may be below the channel. 2020-07-16 14:23:48 -07:00
mrg ba3d32fa0c Starting to implement minimizing channel router (not done) 2020-07-16 13:21:44 -07:00
mrg e49236f8fc Default drc and lvs errors is skipped. 2020-07-13 14:08:00 -07:00
mrg 716798baae Convert all DRC and LVS routines to set member variables for drc_errors and lvs_errors. 2020-07-13 13:01:00 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
mrg 27166c75f0 Don't remove temp files during regular openram runs. 2020-07-03 07:00:56 -07:00
mrg c340870ba0 Channel route dout wires as well in read write ports 2020-07-01 14:44:01 -07:00
mrg 3d0f29ff3a Fix missing via LVS issues. LVS passing for some 20 tests. 2020-07-01 09:22:59 -07:00
mrg c1fedda575 Modifications for min area metal. 
Made add_via_stack_center iterative instead of recursive.
Removed add_via_stack (non-center) since it isn't used.
Add min area metal during iterative via insertion.
 2020-06-30 15:07:34 -07:00
mrg 8cedeeb3d9 Widen pitch of control bus in bank. 2020-06-30 10:57:41 -07:00
Matt Guthaus 9b939c9a1a DRC/LVS and errors fixes. 
Only enact pdb if assert fails in debug.error.
Only run drc/lvs one time in parse_info by saving result.
Cleanup drc/lvs output.
 2020-06-30 07:16:05 -07:00
Matt Guthaus e97644c424 Only do reverse lookup on valid interconnect layers since layer numbers can be shared. 2020-06-29 14:42:24 -07:00
mrg 07d0f3af8e Only copy end-cap pins to the bank level 2020-06-29 11:46:59 -07:00
mrg 47f541df0e Fix bugs in channel route. 2020-06-28 16:58:28 -07:00
mrg 709535f90f Fix right perimeter pin coordinate bug 2020-06-28 14:47:17 -07:00
mrg bc3de9db05 Pick correct side of pin in channel route. 2020-06-28 14:28:18 -07:00
mrg 94d7000717 Reduce output clutter from gds write 2020-06-26 12:16:54 -07:00
mrg 567675ab31 PEP8 cleanup 2020-06-26 11:47:12 -07:00
mrg d53abba479 Always route the channel route since it is it's own design. 2020-06-25 17:43:44 -07:00
mrg f11afaa63d Refactor channel route to be a design. 2020-06-25 17:30:03 -07:00
mrg 4bc3df8931 Add get_tx_insts and expand add_enclosure 2020-06-24 11:54:36 -07:00
mrg cddb16dabc Separate active and poly contact to gate rule 2020-06-24 09:17:39 -07:00
mrg 83001e1ab5 PEP8 formatting 2020-06-23 15:39:26 -07:00
mrg e849a9b973 Use different LVS libs based on tech and sky130 2020-06-23 14:53:24 -07:00
mrg 031862c749 Add metal enclosure to base case of center via stack. 2020-06-23 11:56:50 -07:00
mrg 54120f8405 Add option for removing subckt/instances of cells for row/col caps 2020-06-22 12:35:37 -07:00
mrg a13d535945 PEP8 cleanup 2020-06-22 11:33:02 -07:00
mrg 78be9f367a Add brain-dead router pins to perimeter 2020-06-14 15:52:09 -07:00
mrg 8f1dc7eeea Include mirror/rotate on translate_all boundary update 2020-06-13 06:50:53 -07:00
mrg 33a32101c9 DRC and LVS fixes for pinv_dec 2020-06-12 15:23:51 -07:00
mrg 443b8fbe23 Change s8 to sky130 2020-06-12 14:23:26 -07:00
mrg e9780ea599 Add non-preferred directions for channel routes 2020-06-11 15:03:36 -07:00
mrg 7ad2d54a69 Add pin and label purposes 2020-06-11 11:54:51 -07:00
mrg 089331ced3 Add stdc bounding box too 2020-06-11 11:54:16 -07:00
mrg 098219d56c Add npc enclosure to poly contacts 2020-06-11 11:53:59 -07:00
mrg 5e3332453b Allow power pins to start on any layer besides m1 2020-06-10 10:15:23 -07:00
mrg a28e747a02 Fix precharge offset. Move well rules to design class. 2020-06-09 15:28:50 -07:00
mrg 148521c458 Remove stdc layer 2020-06-09 13:48:47 -07:00
mrg 9cc36c6d3a Bus code converted to pins. Fix layers on control signal routes in bank. 2020-06-08 11:01:14 -07:00
mrg 2fcecb7227 Variable zjog. 512 port address test. s8 port address working. 2020-06-04 16:01:32 -07:00
Joey Kunzler 7a602b75a4 keep dev routing changes to hierarchy_layout 2020-06-03 12:54:15 -07:00
Joey Kunzler 84021c9ccb merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg 620604603c Fixed offset jogs 2020-06-02 10:08:37 -07:00
Joey Kunzler b39579c109 temp drc fix for regression tests 2020-06-01 20:55:15 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
Joey Kunzler 9a6b38b67e merge conflict 2020-05-26 16:03:36 -07:00
mrg 848241a3ad PEP8 cleanup 2020-05-11 16:22:17 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
Joey Kunzler e642b8521b increase col_mux bitline spacing to fix cyclic vcg 2020-05-06 13:02:33 -07:00
Joey Kunzler 91dbbed9ba added horizontal trunk route edit to vertical trunk route 2020-05-05 12:18:26 -07:00
Joey Kunzler 1b6634bb97 port data routing fix 2020-04-29 15:48:15 -07:00
Joey Kunzler 0bae652be9 fix merge conflicts 2020-04-23 11:51:46 -07:00
mrg ab91d0ab1d Add purpose to string output 2020-04-21 15:20:30 -07:00
mrg dfbf6fe45c Default is to use preferred layer directions 2020-04-20 15:33:53 -07:00
mrg 7f65176908 Configured bitline directions into prot_data 2020-04-20 14:23:40 -07:00
Joey Kunzler 7920b0cef9 m3 min area rounding fix 2020-04-17 12:36:48 -07:00
mrg d1319d633d Don't widen too short wires either 2020-04-16 11:02:54 -07:00
mrg b347e3f7a8 Try both layers for reversed layer stacks. 2020-04-15 16:49:04 -07:00
mrg 94eb2afa36 Change to callable DRC rule. Use bottom coordinate for bus offsets. 2020-04-15 15:29:55 -07:00