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OpenRAM
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1839 Commits

Author SHA1 Message Date
Matt Guthaus 38213d998f Add separate layer and purpose pairs to tech layers. 2019-10-25 10:03:25 -07:00
Matt Guthaus 764d4da1bd Clean up config file organization. Improve gdsMill debug output. 2019-10-23 10:48:18 -07:00
Matt Guthaus ccc6a67021 Update version to 1.1.2 2019-10-07 12:28:02 -07:00
Matt Guthaus 84c7146792 Fix some pep8 errors/warnings in pgate and examples. 2019-10-06 17:30:16 +00:00
vagrant 67c768d22c Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
Hunter Nichols d722311822 Merge branch 'dev' into update_scmos_models 2019-10-03 13:16:32 -07:00
mrg d583695959 Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
Hunter Nichols b420f77ff1 Updated leakage power golden data in hspice delay test. 2019-10-01 15:26:34 -07:00
Hunter Nichols 19a09470d4 Merged with dev, conflict in golden data of hspice delay test. 2019-10-01 14:26:34 -07:00
Hunter Nichols 7b029a4582 Updated golden values in delay tests due to model changes. 2019-09-30 14:02:00 -07:00
Matt Guthaus b0dcfb5b2d Fix leakage mismatch in results. 2019-09-27 15:14:01 -07:00
Matt Guthaus 289d3b3988 Feedthru port edits. 
Comment about write driver size for write through to work, but
disable write through in functional simulation.
Provide warning in Verilog about write throughs.
 2019-09-27 14:18:49 -07:00
Matt Guthaus cbbcb97a10 Merge branch 'dev' into feedthru 2019-09-27 09:42:51 -07:00
Matt Guthaus 99507ba5c5 Remove rbl_bl_delay_bar from w_en logic inputs. 2019-09-07 23:22:01 -07:00
Matt Guthaus 9ec663e0b1 Write all write ports first cycle. Don't check feedthru. 2019-09-07 20:20:44 -07:00
Matt Guthaus 35a8dd2eec Factor out masking function 2019-09-07 20:05:05 -07:00
Matt Guthaus 322af0ec09 Remove sense enable during writes 2019-09-07 20:04:48 -07:00
Matt Guthaus e5db02f7d8 Fix wrong function. Except unknown ports. 2019-09-06 14:59:23 -07:00
Matt Guthaus 93c89895c9 Remove unused test structures 2019-09-06 14:58:47 -07:00
Matt Guthaus b5b0e35c8a Fix syntax error. 2019-09-06 12:29:28 -07:00
Matt Guthaus 86c22c8904 Clean and simplify simulation code. Feedthru check added. 2019-09-06 12:09:12 -07:00
Matt Guthaus 6bee66f9dc Forgot to add cs_bar to rw port rails. 2019-09-06 09:29:23 -07:00
Matt Guthaus 969cca28e4 Enable sensing during writes. Need to add dedicated test. 2019-09-06 07:16:50 -07:00
jsowash 1c65b90c70 Merge branch 'dev' into add_wmask 2019-09-05 09:15:05 -07:00
Matt Guthaus 678b2cc3fa Fix functional test clk name 2019-09-04 18:59:08 -07:00
Matt Guthaus 4c3b171b72 Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
jsowash 8c33749223 Uncommented offset_all_coordinates. 2019-09-04 16:41:27 -07:00
jsowash febc053587 Moved SRAM macro in LEF file to origin and removed poly. 2019-09-04 16:11:12 -07:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
Matt Guthaus 8c601ce939 Model tests don't need layout 2019-09-04 16:06:12 -07:00
Matt Guthaus c5568e86fe Enable spice and don't purge option to test 30 2019-09-04 14:33:25 -07:00
jsowash fbecb9bc02 Added poly to LEF files. 2019-09-04 14:06:17 -07:00
jsowash d6e7047e2f Added metal4 to lef files since it's now used with a wmask. 2019-09-04 13:04:51 -07:00
Matt Guthaus eadb5d5e48 Allow gds file for front end with new options 2019-09-04 10:26:54 -07:00
jsowash 496a9919b8 Added wmask as a type group to .lib. 2019-09-04 09:45:11 -07:00
jsowash 452cc5e443 Added wmask to lib.py. 2019-09-04 09:29:45 -07:00
jsowash 1a72070f04 Removed LVS error where w_en went over whole AND array in 2 port. 2019-09-03 17:14:31 -07:00
jsowash 4c40804b8f Moved via in write driver up for 2 port. 2019-09-03 15:14:41 -07:00
jsowash abb86c338b Added port specification. 2019-09-03 14:52:43 -07:00
jsowash dd67490823 Changed routing to allow for 2 write port with write mask. 2019-09-03 14:43:03 -07:00
jsowash 01bdea23ae Merge branch 'add_wmask' of https://github.com/VLSIDA/PrivateRAM into add_wmask 2019-09-03 11:50:57 -07:00
jsowash b5ca417b26 Added fix for column mux lib generation.: 2019-09-03 11:50:39 -07:00
jsowash 4a8ec7a687 Added 2 port test for wmask. 2019-09-03 11:49:37 -07:00
Matt Guthaus 69c5608b53 Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
jsowash e8435d0d83 Added test for picorv32 memory without characterization. 2019-08-30 11:24:20 -07:00
jsowash e3b42430bd Changed max_gap_size_wmask to take into account column ffs. 2019-08-29 17:09:17 -07:00
jsowash bbe235074c Added max gap size for wmask and edited max gap size for data ff's to take into account m3 spacing. 2019-08-29 16:41:58 -07:00
Matt Guthaus a78245786c Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-29 16:06:39 -07:00
Matt Guthaus 7fe9e5704d Convert vcg and nets to ordered dict 2019-08-29 16:06:34 -07:00
jsowash 37116ce9d8 Increased spacing between wmask and data dffs. 2019-08-29 16:00:50 -07:00
jsowash c1906ade3f Removed A pin's via connection since it's created in the SRAM level and rearranged the SRAM flip flop creation. 2019-08-29 14:48:13 -07:00
jsowash af3d2af0ec Merge branch 'dev' into add_wmask 2019-08-29 12:56:11 -07:00
jsowash f13c8eae8d Moved column mux ff's to be horizontal with wmask flip flops and adjusted wmask AND array en pin location starting point. 2019-08-29 11:07:42 -07:00
jsowash 5099ff6f6c Changed A/Z pins to copy_layout_pin and made en (B) pin a single pin. 2019-08-29 09:01:35 -07:00
Matt Guthaus 64fc771fc4 Simplify is not None 2019-08-22 15:02:52 -07:00
Matt Guthaus ee2456f433 Merge branch 'add_wmask' into dev 2019-08-22 15:01:41 -07:00
Matt Guthaus bdf29c3a26 Fix non-preferred route width again. This time it is likely right. 2019-08-22 13:57:14 -07:00
Matt Guthaus 560d768010 Fix syntax error in router 2019-08-22 13:46:32 -07:00
Matt Guthaus afaa946f9c Fix width of non-preferred trunk wire 2019-08-22 12:03:38 -07:00
jsowash 27ec617315 Fixed M1.5 error in 8mux tests which came from pdriver. 2019-08-22 09:34:53 -07:00
Matt Guthaus 2ffdfb18a4 Fix trunks less than a pitch in channel route 2019-08-21 17:11:02 -07:00
jsowash a8df5528f9 Added 2 mux test for wmask. 2019-08-21 16:06:36 -07:00
Matt Guthaus 98f526427e Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-21 15:33:03 -07:00
Matt Guthaus 9ada9a7dfa Fix pitch in channel router to support M3/M4. 2019-08-21 15:32:49 -07:00
jsowash 737e873923 Changed via direction for via1 in flip flops. 2019-08-21 14:49:54 -07:00
Matt Guthaus 9f54afbf2c Fix capitalization in verilog golden files 2019-08-21 14:29:57 -07:00
jsowash 980760b724 Add preferred direction to via1, routed between supply lines in wmask AND array, and only uses m3 for channel route with a write mask. 2019-08-21 14:02:57 -07:00
Matt Guthaus 5f3ffdb8ba Output name and version in help 2019-08-21 14:00:55 -07:00
Matt Guthaus d0f04405a6 Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
jsowash 4f01eeb3c1 Combined changes to the pin locations and vias. 2019-08-21 12:36:53 -07:00
jsowash c2015335b0 Fixed merge issues. 2019-08-21 11:54:22 -07:00
jsowash 4813c01d56 Moved dff's up and moved wmask_AND/wdriver pins left/down, respectively. 2019-08-21 11:50:28 -07:00
Matt Guthaus b0821a5a0e Re-add simplified power pins on edges 2019-08-21 11:42:56 -07:00
Matt Guthaus b94af3e3fd Add vias for new channel routes 2019-08-21 11:33:43 -07:00
Matt Guthaus f281510828 Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-21 11:20:42 -07:00
Matt Guthaus 2b7025335c Use pand2 of correct size. Simplify width checking of AND array. 2019-08-21 11:20:35 -07:00
jsowash 43d45fba98 Moved pwr/gnd pins to the right of the rail. 2019-08-21 10:44:04 -07:00
Matt Guthaus c39b09c736 Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-21 10:18:59 -07:00
Matt Guthaus 54ab9440db Use pdriver instead of pinv in pand gates. 2019-08-21 10:18:46 -07:00
jsowash 0cbc4a7acf Moved wmask dff above data dff and changed channel route to m3/m4 for data and m1/m2 for wmask. 2019-08-21 10:07:20 -07:00
Matt Guthaus 53d0544291 Minor cleanup and additional assertion checking. 2019-08-21 08:50:12 -07:00
Matt Guthaus f2568fec80 Change permissions on tests to +x. Add single bank wmask test. 2019-08-21 08:49:46 -07:00
jsowash 71af70a636 Moved pwr/gnd vias and corrected width boundary. 2019-08-20 09:14:23 -07:00
jsowash 316132a33c Sized inverter for number of driven write drivers. 2019-08-19 13:31:49 -07:00
jsowash c19bada8df Performed clean up and added comments. 2019-08-19 08:57:05 -07:00
jsowash a28c9fed8b Fixed bug for more than 2 wmasks and changed test to test 4 wmasks. 2019-08-16 14:27:44 -07:00
jsowash d02ea06ff2 Added method to route between the output of wmask AND array and en of write driver. 2019-08-16 14:12:41 -07:00
jsowash aaa1e3a614 Added change to route wmask en between driver and AND gates. Need to apply it to all cases. 2019-08-16 10:23:51 -07:00
jsowash 92e0671e15 Removed DRC error with AND array in freepdk45 and moved pin on en_{} pin in port data. 2019-08-15 12:36:17 -07:00
jsowash f0f811bad9 Added a condiitonal to only route wmask dff when there's a write size. 2019-08-14 12:40:14 -07:00
jsowash 858fbb062d Placed wmask dff and added connections for wmask pins. 2019-08-14 11:45:22 -07:00
jsowash 0d7170eb95 Created wmask AND array en pin to go through to top layer. 2019-08-14 09:59:40 -07:00
jsowash aa4803f3c4 Increased enable pin's width for larger # of column mux ways. 2019-08-11 15:25:05 -07:00
jsowash 2573b5f48b Fixed merge conflict. 2019-08-11 14:39:36 -07:00
jsowash d259efbcda Connected wdriver_sel between write_mask_and_array and write_driver_array. 2019-08-11 14:33:08 -07:00
Matt Guthaus e5618b88af Don't add sense amp to write only port. Fix write_and None define. 2019-08-11 08:46:36 -07:00
Matt Guthaus d56a972d61 Update ngspice tests due to new version 2019-08-10 17:59:30 -07:00
Matt Guthaus c09005dab9 Redo logic for detecting bad bitlines 2019-08-10 17:32:36 -07:00
Matt Guthaus 6cf7366c56 Gate sen during first half period 2019-08-10 16:30:02 -07:00
Matt Guthaus 8d6a4c74e7 Merge branch 'dev' into control_fix 2019-08-10 13:07:30 -07:00