mirror of https://github.com/VLSIDA/OpenRAM.git
Don't add sense amp to write only port. Fix write_and None define.
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d56a972d61
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@ -156,11 +156,14 @@ class port_data(design.design):
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bitcell_bl=self.bl_names[self.port],
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bitcell_br=self.br_names[self.port])
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self.add_mod(self.precharge_array)
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self.sense_amp_array = factory.create(module_type="sense_amp_array",
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word_size=self.word_size,
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words_per_row=self.words_per_row)
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self.add_mod(self.sense_amp_array)
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if self.port in self.read_ports:
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self.sense_amp_array = factory.create(module_type="sense_amp_array",
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word_size=self.word_size,
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words_per_row=self.words_per_row)
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self.add_mod(self.sense_amp_array)
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else:
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self.sense_amp_array = None
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if self.col_addr_size > 0:
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@ -187,7 +190,7 @@ class port_data(design.design):
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write_size=self.write_size)
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self.add_mod(self.write_mask_and_array)
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else:
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self.write_mask_and_array_inst = None
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self.write_mask_and_array = None
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else:
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self.write_driver_array = None
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