mirror of https://github.com/VLSIDA/OpenRAM.git
Feedthru port edits.
Comment about write driver size for write through to work, but disable write through in functional simulation. Provide warning in Verilog about write throughs.
This commit is contained in:
Matt Guthaus
parent
cbbcb97a10
commit
289d3b3988
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@ -122,6 +122,9 @@ class verilog:
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if self.write_size:
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self.vf.write(" wmask{0}_reg = wmask{0};\n".format(port))
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self.vf.write(" addr{0}_reg = addr{0};\n".format(port))
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if port in self.read_ports:
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self.add_write_read_checks(port)
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if port in self.write_ports:
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self.vf.write(" din{0}_reg = din{0};\n".format(port))
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if port in self.read_ports:
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@ -211,4 +214,29 @@ class verilog:
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self.vf.write(" if (!csb{0}_reg)\n".format(port))
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self.vf.write(" dout{0} <= #(DELAY) mem[addr{0}_reg];\n".format(port))
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self.vf.write(" end\n")
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def add_address_check(self, wport, rport):
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""" Output a warning if the two addresses match """
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# If the rport is actually reading... and addresses match.
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if rport in self.readwrite_ports:
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rport_control = "!csb{0} && web{0}".format(rport)
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else:
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rport_control = "!csb{0}".format(rport)
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if wport in self.readwrite_ports:
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wport_control = "!csb{0} && !web{0}".format(wport)
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else:
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wport_control = "!csb{0}".format(wport)
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self.vf.write(" if ({1} && {3} && (addr{0} == addr{2}))\n".format(wport,wport_control,rport,rport_control))
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self.vf.write(" $display($time,\" WARNING: Writing and reading addr{0}=%b and addr{1}=%b simultaneously!\",addr{0},addr{1});\n".format(wport,rport))
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def add_write_read_checks(self, rport):
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"""
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Add a warning if we read from an address that we are currently writing.
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Can be fixed if we appropriately size the write drivers to do this .
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"""
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for wport in self.write_ports:
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if wport == rport:
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continue
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else:
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self.add_address_check(wport,rport)
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@ -180,14 +180,16 @@ class functional(simulation):
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w_addrs.append(addr)
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else:
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(addr,word) = random.choice(list(self.stored_words.items()))
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## cannot read from an address that is currently being written to
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# Yes, you can!!
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#if addr in w_addrs:
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# self.add_noop_one_port(port)
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#else:
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comment = self.gen_cycle_comment("read", word, addr, "0"*self.num_wmasks, port, self.t_current)
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self.add_read_one_port(comment, addr, port)
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self.add_read_check(word, port)
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# The write driver is not sized sufficiently to drive through the two
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# bitcell access transistors to the read port. So, for now, we do not allow
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# a simultaneous write and read to the same address on different ports. This
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# could be even more difficult with multiple simultaneous read ports.
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if addr in w_addrs:
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self.add_noop_one_port(port)
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else:
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comment = self.gen_cycle_comment("read", word, addr, "0"*self.num_wmasks, port, self.t_current)
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self.add_read_one_port(comment, addr, port)
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self.add_read_check(word, port)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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@ -125,7 +125,7 @@ class control_logic(design.design):
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self.add_mod(self.wl_en_driver)
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# w_en drives every write driver
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self.wen_and = factory.create(module_type="pand2",
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self.wen_and = factory.create(module_type="pand3",
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size=self.word_size+8,
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height=dff_height)
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self.add_mod(self.wen_and)
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@ -344,11 +344,11 @@ class control_logic(design.design):
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# list of output control signals (for making a vertical bus)
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if self.port_type == "rw":
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self.internal_bus_list = ["rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "clk_buf", "we_bar", "cs"]
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "clk_buf", "we_bar", "cs"]
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elif self.port_type == "r":
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self.internal_bus_list = ["rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"]
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"]
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else:
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self.internal_bus_list = ["rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"]
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"]
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# leave space for the bus plus one extra space
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self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch
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@ -382,6 +382,7 @@ class control_logic(design.design):
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self.create_gated_clk_buf_row()
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self.create_wlen_row()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.create_rbl_delay_row()
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self.create_wen_row()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.create_sen_row()
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@ -419,6 +420,9 @@ class control_logic(design.design):
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row += 1
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self.place_pen_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.place_rbl_delay_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.place_sen_row(row)
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row += 1
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@ -443,6 +447,7 @@ class control_logic(design.design):
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self.route_dffs()
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self.route_wlen()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.route_rbl_delay()
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self.route_wen()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.route_sen()
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@ -671,7 +676,34 @@ class control_logic(design.design):
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self.connect_output(self.s_en_gate_inst, "Z", "s_en")
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def create_rbl_delay_row(self):
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self.rbl_bl_delay_inv_inst = self.add_inst(name="rbl_bl_delay_inv",
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mod=self.inv)
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self.connect_inst(["rbl_bl_delay", "rbl_bl_delay_bar", "vdd", "gnd"])
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def place_rbl_delay_row(self,row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.rbl_bl_delay_inv_inst, x_offset, row)
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self.row_end_inst.append(self.rbl_bl_delay_inv_inst)
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def route_rbl_delay(self):
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# Connect from delay line
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# Connect to rail
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rbl_map = zip(["Z"], ["rbl_bl_delay_bar"])
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self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets, ("metal3", "via2", "metal2"))
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# The pin is on M1, so we need another via as well
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=self.rbl_bl_delay_inv_inst.get_pin("Z").center())
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rbl_map = zip(["A"], ["rbl_bl_delay"])
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self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets)
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def create_wen_row(self):
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# input: we (or cs) output: w_en
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@ -685,7 +717,7 @@ class control_logic(design.design):
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self.w_en_gate_inst = self.add_inst(name="w_en_and",
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mod=self.wen_and)
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# Only drive the writes in the second half of the clock cycle during a write operation.
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self.connect_inst([input_name, "gated_clk_bar", "w_en", "vdd", "gnd"])
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self.connect_inst([input_name, "rbl_bl_delay_bar", "gated_clk_bar", "w_en", "vdd", "gnd"])
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def place_wen_row(self,row):
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@ -702,7 +734,7 @@ class control_logic(design.design):
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# No we for write-only reports, so use cs
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input_name = "cs"
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wen_map = zip(["A", "B"], [input_name, "gated_clk_bar"])
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wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay_bar", "gated_clk_bar"])
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self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.rail_offsets)
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self.connect_output(self.w_en_gate_inst, "Z", "w_en")
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