mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'dev' into add_wmask
This commit is contained in:
jsowash
commit
1c65b90c70
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@ -392,7 +392,7 @@ class spice():
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"""Returns delay increase due to voltage.
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Implemented as linear factor based off nominal voltage.
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"""
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return tech.spice['vdd_nominal']/voltage
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return tech.spice["nom_supply_voltage"]/voltage
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def get_temp_delay_factor(self, temp):
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"""Returns delay increase due to temperature (in C).
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@ -400,11 +400,11 @@ class spice():
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"""
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#Some portions of equation condensed (phi_t = k*T/q for T in Kelvin) in mV
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#(k/q)/100 = .008625, The division 100 simplifies the conversion from C to K and mV to V
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thermal_voltage_nom = .008625*tech.spice["temp_nominal"]
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thermal_voltage = .008625*temp
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vthresh = (tech.spice["v_threshold_typical"]+2*(thermal_voltage-thermal_voltage_nom))
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thermal_voltage_nom = 0.008625*tech.spice["nom_temperature"]
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thermal_voltage = 0.008625*temp
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vthresh = (tech.spice["nom_threshold"]+2*(thermal_voltage-thermal_voltage_nom))
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#Calculate effect on Vdd-Vth. The current vdd is not used here. A separate vdd factor is calculated.
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return (tech.spice['vdd_nominal'] - tech.spice["v_threshold_typical"])/(tech.spice['vdd_nominal']-vthresh)
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return (tech.spice["nom_supply_voltage"] - tech.spice["nom_threshold"])/(tech.spice["nom_supply_voltage"]-vthresh)
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def return_delay(self, delay, slew):
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return delay_data(delay, slew)
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@ -259,7 +259,7 @@ class delay(simulation):
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"""Sets important names for characterization such as Sense amp enable and internal bit nets."""
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port = self.read_ports[0]
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self.graph.get_all_paths('{}{}'.format(tech.spice["clk"], port),
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, self.probe_data))
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self.sen_name = self.get_sen_name(self.graph.all_paths)
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@ -1291,7 +1291,7 @@ class delay(simulation):
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self.create_measurement_names()
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port = self.read_ports[0]
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self.graph.get_all_paths('{}{}'.format(tech.spice["clk"], port),
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, self.probe_data))
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# Select the path with the bitline (bl)
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@ -349,7 +349,7 @@ class functional(simulation):
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# Generate CLK signals
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for port in self.all_ports:
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self.stim.gen_pulse(sig_name="{0}{1}".format(tech.spice["clk"], port),
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self.stim.gen_pulse(sig_name="{0}{1}".format("clk", port),
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v1=self.gnd_voltage,
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v2=self.vdd_voltage,
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offset=self.period,
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@ -402,7 +402,7 @@ class functional(simulation):
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# For now, only testing these using first read port.
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port = self.read_ports[0]
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self.graph.get_all_paths('{}{}'.format(tech.spice["clk"], port),
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, 0).lower())
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self.sen_name = self.get_sen_name(self.graph.all_paths)
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@ -336,10 +336,10 @@ class setup_hold():
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for self.related_input_slew in related_slews:
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for self.constrained_input_slew in constrained_slews:
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# convert from ps to ns
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LH_setup.append(tech.spice["msflop_setup"]/1e3)
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HL_setup.append(tech.spice["msflop_setup"]/1e3)
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LH_hold.append(tech.spice["msflop_hold"]/1e3)
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HL_hold.append(tech.spice["msflop_hold"]/1e3)
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LH_setup.append(tech.spice["dff_setup"]/1e3)
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HL_setup.append(tech.spice["dff_setup"]/1e3)
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LH_hold.append(tech.spice["dff_hold"]/1e3)
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HL_hold.append(tech.spice["dff_hold"]/1e3)
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times = {"setup_times_LH": LH_setup,
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"setup_times_HL": HL_setup,
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@ -46,10 +46,10 @@ class simulation():
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""" sets feasible timing parameters """
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self.period = tech.spice["feasible_period"]
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self.slew = tech.spice["rise_time"]*2
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self.load = tech.spice["msflop_in_cap"]*4
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self.load = tech.spice["dff_in_cap"]*4
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self.v_high = self.vdd_voltage - tech.spice["v_threshold_typical"]
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self.v_low = tech.spice["v_threshold_typical"]
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self.v_high = self.vdd_voltage - tech.spice["nom_threshold"]
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self.v_low = tech.spice["nom_threshold"]
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self.gnd_voltage = 0
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def create_signal_names(self):
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@ -301,7 +301,7 @@ class simulation():
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pin_names.append("WEB{0}".format(port))
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for port in range(total_ports):
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pin_names.append("{0}{1}".format(tech.spice["clk"], port))
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pin_names.append("{0}{1}".format("clk", port))
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if self.write_size:
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for port in write_index:
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@ -312,7 +312,7 @@ class simulation():
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for i in range(dbits):
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pin_names.append("{0}{1}_{2}".format(dout_name,read_output, i))
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pin_names.append("{0}".format(tech.spice["vdd_name"]))
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pin_names.append("{0}".format(tech.spice["gnd_name"]))
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pin_names.append("{0}".format("vdd"))
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pin_names.append("{0}".format("gnd"))
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return pin_names
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@ -24,12 +24,12 @@ class stimuli():
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""" Class for providing stimuli functions """
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def __init__(self, stim_file, corner):
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self.vdd_name = tech.spice["vdd_name"]
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self.gnd_name = tech.spice["gnd_name"]
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self.vdd_name = "vdd"
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self.gnd_name = "gnd"
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self.pmos_name = tech.spice["pmos"]
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self.nmos_name = tech.spice["nmos"]
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self.tx_width = tech.spice["minwidth_tx"]
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self.tx_length = tech.spice["channel"]
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self.tx_width = tech.drc["minwidth_tx"]
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self.tx_length = tech.drc["minlength_channel"]
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self.sf = stim_file
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@ -157,7 +157,7 @@ class bitcell_array(design.design):
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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bl_swing = OPTS.rbl_delay_percentage
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freq = spice["default_event_rate"]
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freq = spice["default_event_frequency"]
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bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
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#Calculate the bitcell power which currently only includes leakage
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@ -33,9 +33,9 @@ class dff(design.design):
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_rate"]
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["msflop_leakage"]
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power_leak = spice["dff_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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@ -44,8 +44,8 @@ class dff(design.design):
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"""Computes effective capacitance. Results in fF"""
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from tech import parameter
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c_load = load
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c_para = spice["flop_para_cap"]#ff
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transition_prob = spice["flop_transition_prob"]
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c_para = spice["dff_out_cap"]#ff
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transition_prob = 0.5
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return transition_prob*(c_load + c_para)
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def get_clk_cin(self):
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@ -57,4 +57,4 @@ class dff(design.design):
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets)
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@ -382,7 +382,7 @@ class replica_bitcell_array(design.design):
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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bl_swing = OPTS.rbl_delay_percentage
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freq = spice["default_event_rate"]
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freq = spice["default_event_frequency"]
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bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
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#Calculate the bitcell power which currently only includes leakage
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@ -258,7 +258,7 @@ class pinv(pgate.pgate):
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_rate"]
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["inv_leakage"]
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@ -269,7 +269,7 @@ class pinv(pgate.pgate):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transition_prob = spice["inv_transition_prob"]
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transition_prob = 0.5
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return transition_prob*(c_load + c_para)
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def input_load(self):
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@ -233,7 +233,7 @@ class pnand2(pgate.pgate):
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_rate"]
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["nand2_leakage"]
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@ -244,7 +244,7 @@ class pnand2(pgate.pgate):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transition_prob = spice["nand2_transition_prob"]
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transition_prob = 0.1875
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return transition_prob*(c_load + c_para)
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def input_load(self):
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@ -246,7 +246,7 @@ class pnand3(pgate.pgate):
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_rate"]
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["nand3_leakage"]
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@ -257,7 +257,7 @@ class pnand3(pgate.pgate):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transition_prob = spice["nand3_transition_prob"]
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transition_prob = 0.1094
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return transition_prob*(c_load + c_para)
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def input_load(self):
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@ -230,7 +230,7 @@ class pnor2(pgate.pgate):
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_rate"]
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["nor2_leakage"]
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@ -241,7 +241,7 @@ class pnor2(pgate.pgate):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transition_prob = spice["nor2_transition_prob"]
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transition_prob = 0.1875
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return transition_prob*(c_load + c_para)
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def build_graph(self, graph, inst_name, port_nets):
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@ -54,7 +54,7 @@ class timing_sram_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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d = delay(s.s, tempspice, corner)
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import tech
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loads = [tech.spice["msflop_in_cap"]*4]
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loads = [tech.spice["dff_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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data, port_data = d.analyze(probe_address, probe_data, slews, loads)
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#Combine info about port into all data
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@ -49,7 +49,7 @@ class model_delay_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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d = delay(s.s, tempspice, corner)
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import tech
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loads = [tech.spice["msflop_in_cap"]*4]
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loads = [tech.spice["dff_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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# Run a spice characterization
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|
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@ -47,7 +47,7 @@ class timing_sram_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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d = delay(s.s, tempspice, corner)
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import tech
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loads = [tech.spice["msflop_in_cap"]*4]
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loads = [tech.spice["dff_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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data, port_data = d.analyze(probe_address, probe_data, slews, loads)
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#Combine info about port into all data
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|
|
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@ -19,6 +19,7 @@ class lib_model_corners_lib_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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OPTS.netlist_only = True
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from characterizer import lib
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from sram import sram
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|
|
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@ -19,7 +19,8 @@ class lib_sram_model_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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OPTS.netlist_only = True
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|
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from characterizer import lib
|
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from sram import sram
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from sram_config import sram_config
|
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|
|
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@ -38,9 +38,12 @@ class openram_back_end_test(openram_test):
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os.chmod(out_path, 0o0750)
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# specify the same verbosity for the system call
|
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verbosity = ""
|
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options = ""
|
||||
for i in range(OPTS.debug_level):
|
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verbosity += " -v"
|
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options += " -v"
|
||||
|
||||
if OPTS.spice_name:
|
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options += " -s {}".format(OPTS.spice_name)
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||||
|
||||
# Always perform code coverage
|
||||
if OPTS.coverage == 0:
|
||||
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|
@ -52,7 +55,7 @@ class openram_back_end_test(openram_test):
|
|||
cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name,
|
||||
out_file,
|
||||
out_path,
|
||||
verbosity,
|
||||
options,
|
||||
config_name,
|
||||
out_path)
|
||||
debug.info(1, cmd)
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||||
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|
@ -83,10 +86,11 @@ class openram_back_end_test(openram_test):
|
|||
|
||||
|
||||
# now clean up the directory
|
||||
if os.path.exists(out_path):
|
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shutil.rmtree(out_path, ignore_errors=True)
|
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self.assertEqual(os.path.exists(out_path),False)
|
||||
|
||||
if OPTS.purge_temp:
|
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if os.path.exists(out_path):
|
||||
shutil.rmtree(out_path, ignore_errors=True)
|
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self.assertEqual(os.path.exists(out_path),False)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
# run the test from the command line
|
||||
|
|
|
|||
|
|
@ -39,10 +39,12 @@ class openram_front_end_test(openram_test):
|
|||
os.chmod(out_path, 0o0750)
|
||||
|
||||
# specify the same verbosity for the system call
|
||||
verbosity = ""
|
||||
options = ""
|
||||
for i in range(OPTS.debug_level):
|
||||
verbosity += " -v"
|
||||
options += " -v"
|
||||
|
||||
if OPTS.spice_name:
|
||||
options += " -s {}".format(OPTS.spice_name)
|
||||
|
||||
# Always perform code coverage
|
||||
if OPTS.coverage == 0:
|
||||
|
|
@ -54,7 +56,7 @@ class openram_front_end_test(openram_test):
|
|||
cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name,
|
||||
out_file,
|
||||
out_path,
|
||||
verbosity,
|
||||
options,
|
||||
config_name,
|
||||
out_path)
|
||||
debug.info(1, cmd)
|
||||
|
|
@ -84,10 +86,11 @@ class openram_front_end_test(openram_test):
|
|||
self.assertEqual(len(re.findall('WARNING',output)),0)
|
||||
|
||||
|
||||
# now clean up the directory
|
||||
if os.path.exists(out_path):
|
||||
shutil.rmtree(out_path, ignore_errors=True)
|
||||
self.assertEqual(os.path.exists(out_path),False)
|
||||
# now clean up the directory
|
||||
if OPTS.purge_temp:
|
||||
if os.path.exists(out_path):
|
||||
shutil.rmtree(out_path, ignore_errors=True)
|
||||
self.assertEqual(os.path.exists(out_path),False)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
|
|
|
|||
|
|
@ -303,37 +303,16 @@ spice["fall_time"] = 0.005 # fall time in [Nano-seconds]
|
|||
spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
|
||||
spice["nom_temperature"] = 25 # Nominal temperature (celcius)
|
||||
|
||||
|
||||
#sram signal names
|
||||
#FIXME: We don't use these everywhere...
|
||||
spice["vdd_name"] = "vdd"
|
||||
spice["gnd_name"] = "gnd"
|
||||
spice["control_signals"] = ["CSB", "WEB"]
|
||||
spice["data_name"] = "DATA"
|
||||
spice["addr_name"] = "ADDR"
|
||||
spice["minwidth_tx"] = drc["minwidth_tx"]
|
||||
spice["channel"] = drc["minlength_channel"]
|
||||
spice["clk"] = "clk"
|
||||
|
||||
# analytical delay parameters
|
||||
spice["vdd_nominal"] = 1.0 # Typical Threshold voltage in Volts
|
||||
spice["temp_nominal"] = 25.0 # Typical Threshold voltage in Volts
|
||||
spice["v_threshold_typical"] = 0.4 # Typical Threshold voltage in Volts
|
||||
spice["nom_threshold"] = 0.4 # Typical Threshold voltage in Volts
|
||||
spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square
|
||||
spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2
|
||||
spice["min_tx_r"] = 9250.0 # Minimum transistor on resistance in ohms
|
||||
spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
|
||||
spice["min_tx_gate_c"] = 0.2 # Minimum transistor gate capacitance in ff
|
||||
spice["msflop_setup"] = 9 # DFF setup time in ps
|
||||
spice["msflop_hold"] = 1 # DFF hold time in ps
|
||||
spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
||||
spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["msflop_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
spice["dff_setup"] = 9 # DFF setup time in ps
|
||||
spice["dff_hold"] = 1 # DFF hold time in ps
|
||||
spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
||||
spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["dff_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
spice["dff_in_cap"] = 0.2091 # Input capacitance (D) [Femto-farad]
|
||||
spice["dff_out_cap"] = 2 # Output capacitance (Q) [Femto-farad]
|
||||
|
||||
# analytical power parameters, many values are temporary
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
|
||||
|
|
@ -341,19 +320,13 @@ spice["inv_leakage"] = 1 # Leakage power of inverter in nW
|
|||
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
|
||||
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
|
||||
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
|
||||
spice["msflop_leakage"] = 1 # Leakage power of flop in nW
|
||||
spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF
|
||||
spice["dff_leakage"] = 1 # Leakage power of flop in nW
|
||||
|
||||
spice["default_event_rate"] = 100 # Default event activity of every gate. MHz
|
||||
spice["flop_transition_prob"] = 0.5 # Transition probability of inverter.
|
||||
spice["inv_transition_prob"] = 0.5 # Transition probability of inverter.
|
||||
spice["nand2_transition_prob"] = 0.1875 # Transition probability of 2-input nand.
|
||||
spice["nand3_transition_prob"] = 0.1094 # Transition probability of 3-input nand.
|
||||
spice["nor2_transition_prob"] = 0.1875 # Transition probability of 2-input nor.
|
||||
spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz
|
||||
|
||||
#Parameters related to sense amp enable timing and delay chain/RBL sizing
|
||||
parameter['le_tau'] = 2.25 #In pico-seconds.
|
||||
parameter['cap_relative_per_ff'] = 7.5 #Units of Relative Capacitance/ Femto-Farad
|
||||
parameter["le_tau"] = 2.25 #In pico-seconds.
|
||||
parameter["cap_relative_per_ff"] = 7.5 #Units of Relative Capacitance/ Femto-Farad
|
||||
parameter["dff_clk_cin"] = 30.6 #relative capacitance
|
||||
parameter["6tcell_wl_cin"] = 3 #relative capacitance
|
||||
parameter["min_inv_para_delay"] = 2.4 #Tau delay units
|
||||
|
|
@ -361,7 +334,7 @@ parameter["sa_en_pmos_size"] = 0.72 #micro-meters
|
|||
parameter["sa_en_nmos_size"] = 0.27 #micro-meters
|
||||
parameter["sa_inv_pmos_size"] = 0.54 #micro-meters
|
||||
parameter["sa_inv_nmos_size"] = 0.27 #micro-meters
|
||||
parameter['bitcell_drain_cap'] = 0.1 #In Femto-Farad, approximation of drain capacitance
|
||||
parameter["bitcell_drain_cap"] = 0.1 #In Femto-Farad, approximation of drain capacitance
|
||||
|
||||
###################################################
|
||||
##END Spice Simulation Parameters
|
||||
|
|
|
|||
|
|
@ -219,8 +219,6 @@ spice["nmos"]="n"
|
|||
spice["pmos"]="p"
|
||||
# This is a map of corners to model files
|
||||
SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
|
||||
# FIXME: Uncomment when we have the new spice models
|
||||
#spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] }
|
||||
spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
|
||||
"FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
|
||||
"FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
|
||||
|
|
@ -242,37 +240,17 @@ spice["fall_time"] = 0.05 # fall time in [Nano-seconds]
|
|||
spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
|
||||
spice["nom_temperature"] = 25 # Nominal temperature (celcius)
|
||||
|
||||
#sram signal names
|
||||
#FIXME: We don't use these everywhere...
|
||||
spice["vdd_name"] = "vdd"
|
||||
spice["gnd_name"] = "gnd"
|
||||
spice["control_signals"] = ["CSB", "WEB"]
|
||||
spice["data_name"] = "DATA"
|
||||
spice["addr_name"] = "ADDR"
|
||||
spice["minwidth_tx"] = drc["minwidth_tx"]
|
||||
spice["channel"] = drc["minlength_channel"]
|
||||
spice["clk"] = "clk"
|
||||
|
||||
# analytical delay parameters
|
||||
spice["nom_threshold"] = 1.3 # Typical Threshold voltage in Volts
|
||||
# FIXME: These need to be updated for SCMOS, they are copied from FreePDK45.
|
||||
spice["vdd_nominal"] = 5.0 # Typical Threshold voltage in Volts
|
||||
spice["temp_nominal"] = 25.0 # Typical Threshold voltage in Volts
|
||||
spice["v_threshold_typical"] = 1.3 # Typical Threshold voltage in Volts
|
||||
spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square
|
||||
spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2
|
||||
spice["min_tx_r"] = 9250.0 # Minimum transistor on resistance in ohms
|
||||
spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
|
||||
spice["min_tx_gate_c"] = 0.1 # Minimum transistor gate capacitance in ff
|
||||
spice["msflop_setup"] = 9 # DFF setup time in ps
|
||||
spice["msflop_hold"] = 1 # DFF hold time in ps
|
||||
spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
||||
spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
spice["dff_setup"] = 9 # DFF setup time in ps
|
||||
spice["dff_hold"] = 1 # DFF hold time in ps
|
||||
spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
||||
spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
spice["dff_in_cap"] = 9.8242 # Input capacitance (D) [Femto-farad]
|
||||
spice["dff_out_cap"] = 2 # Output capacitance (Q) [Femto-farad]
|
||||
|
||||
# analytical power parameters, many values are temporary
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
|
||||
|
|
@ -280,27 +258,21 @@ spice["inv_leakage"] = 1 # Leakage power of inverter in nW
|
|||
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
|
||||
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
|
||||
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
|
||||
spice["msflop_leakage"] = 1 # Leakage power of flop in nW
|
||||
spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF
|
||||
spice["dff_leakage"] = 1 # Leakage power of flop in nW
|
||||
|
||||
spice["default_event_rate"] = 100 # Default event activity of every gate. MHz
|
||||
spice["flop_transition_prob"] = 0.5 # Transition probability of inverter.
|
||||
spice["inv_transition_prob"] = 0.5 # Transition probability of inverter.
|
||||
spice["nand2_transition_prob"] = 0.1875 # Transition probability of 2-input nand.
|
||||
spice["nand3_transition_prob"] = 0.1094 # Transition probability of 3-input nand.
|
||||
spice["nor2_transition_prob"] = 0.1875 # Transition probability of 2-input nor.
|
||||
spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz
|
||||
|
||||
#Logical Effort relative values for the Handmade cells
|
||||
parameter['le_tau'] = 23 #In pico-seconds.
|
||||
parameter["le_tau"] = 23 #In pico-seconds.
|
||||
parameter["min_inv_para_delay"] = 0.73 #In relative delay units
|
||||
parameter['cap_relative_per_ff'] = 0.91 #Units of Relative Capacitance/ Femto-Farad
|
||||
parameter["cap_relative_per_ff"] = 0.91 #Units of Relative Capacitance/ Femto-Farad
|
||||
parameter["dff_clk_cin"] = 27.5 #In relative capacitance units
|
||||
parameter["6tcell_wl_cin"] = 2 #In relative capacitance units
|
||||
parameter["sa_en_pmos_size"] = 24*_lambda_
|
||||
parameter["sa_en_nmos_size"] = 9*_lambda_
|
||||
parameter["sa_inv_pmos_size"] = 18*_lambda_
|
||||
parameter["sa_inv_nmos_size"] = 9*_lambda_
|
||||
parameter['bitcell_drain_cap'] = 0.2 #In Femto-Farad, approximation of drain capacitance
|
||||
parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of drain capacitance
|
||||
|
||||
###################################################
|
||||
##END Spice Simulation Parameters
|
||||
|
|
|
|||
|
|
@ -70,6 +70,7 @@ parameter={}
|
|||
parameter["min_tx_size"] = 4*_lambda_
|
||||
parameter["beta"] = 2
|
||||
|
||||
# These 6T sizes are used in the parameterized bitcell.
|
||||
parameter["6T_inv_nmos_size"] = 8*_lambda_
|
||||
parameter["6T_inv_pmos_size"] = 3*_lambda_
|
||||
parameter["6T_access_size"] = 4*_lambda_
|
||||
|
|
@ -246,8 +247,6 @@ spice["nmos"]="n"
|
|||
spice["pmos"]="p"
|
||||
# This is a map of corners to model files
|
||||
SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
|
||||
# FIXME: Uncomment when we have the new spice models
|
||||
#spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] }
|
||||
spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
|
||||
"FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
|
||||
"FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
|
||||
|
|
@ -269,37 +268,17 @@ spice["fall_time"] = 0.05 # fall time in [Nano-seconds]
|
|||
spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
|
||||
spice["nom_temperature"] = 25 # Nominal temperature (celcius)
|
||||
|
||||
#sram signal names
|
||||
#FIXME: We don't use these everywhere...
|
||||
spice["vdd_name"] = "vdd"
|
||||
spice["gnd_name"] = "gnd"
|
||||
spice["control_signals"] = ["CSB", "WEB"]
|
||||
spice["data_name"] = "DATA"
|
||||
spice["addr_name"] = "ADDR"
|
||||
spice["minwidth_tx"] = drc["minwidth_tx"]
|
||||
spice["channel"] = drc["minlength_channel"]
|
||||
spice["clk"] = "clk"
|
||||
|
||||
# analytical delay parameters
|
||||
spice["nom_threshold"] = 1.3 # Nominal Threshold voltage in Volts
|
||||
# FIXME: These need to be updated for SCMOS, they are copied from FreePDK45.
|
||||
spice["vdd_nominal"] = 5.0 # Typical Threshold voltage in Volts
|
||||
spice["temp_nominal"] = 25.0 # Typical Threshold voltage in Volts
|
||||
spice["v_threshold_typical"] = 1.3 # Typical Threshold voltage in Volts
|
||||
spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square
|
||||
spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2
|
||||
spice["min_tx_r"] = 9250.0 # Minimum transistor on resistance in ohms
|
||||
spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
|
||||
spice["min_tx_gate_c"] = 0.1 # Minimum transistor gate capacitance in ff
|
||||
spice["msflop_setup"] = 9 # DFF setup time in ps
|
||||
spice["msflop_hold"] = 1 # DFF hold time in ps
|
||||
spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
||||
spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
spice["dff_setup"] = 9 # DFF setup time in ps
|
||||
spice["dff_hold"] = 1 # DFF hold time in ps
|
||||
spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
||||
spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
spice["dff_in_cap"] = 9.8242 # Input capacitance (D) [Femto-farad]
|
||||
spice["dff_out_cap"] = 2 # Output capacitance (Q) [Femto-farad]
|
||||
|
||||
# analytical power parameters, many values are temporary
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
|
||||
|
|
@ -307,27 +286,21 @@ spice["inv_leakage"] = 1 # Leakage power of inverter in nW
|
|||
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
|
||||
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
|
||||
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
|
||||
spice["msflop_leakage"] = 1 # Leakage power of flop in nW
|
||||
spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF
|
||||
spice["dff_leakage"] = 1 # Leakage power of flop in nW
|
||||
|
||||
spice["default_event_rate"] = 100 # Default event activity of every gate. MHz
|
||||
spice["flop_transition_prob"] = .5 # Transition probability of inverter.
|
||||
spice["inv_transition_prob"] = .5 # Transition probability of inverter.
|
||||
spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand.
|
||||
spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand.
|
||||
spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor.
|
||||
spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz
|
||||
|
||||
#Logical Effort relative values for the Handmade cells
|
||||
parameter['le_tau'] = 23 #In pico-seconds.
|
||||
parameter["le_tau"] = 23 #In pico-seconds.
|
||||
parameter["min_inv_para_delay"] = .73 #In relative delay units
|
||||
parameter['cap_relative_per_ff'] = .91 #Units of Relative Capacitance/ Femto-Farad
|
||||
parameter["cap_relative_per_ff"] = .91 #Units of Relative Capacitance/ Femto-Farad
|
||||
parameter["dff_clk_cin"] = 27.5 #In relative capacitance units
|
||||
parameter["6tcell_wl_cin"] = 2 #In relative capacitance units
|
||||
parameter["sa_en_pmos_size"] = 24*_lambda_
|
||||
parameter["sa_en_nmos_size"] = 9*_lambda_
|
||||
parameter["sa_inv_pmos_size"] = 18*_lambda_
|
||||
parameter["sa_inv_nmos_size"] = 9*_lambda_
|
||||
parameter['bitcell_drain_cap'] = 0.2 #In Femto-Farad, approximation of drain capacitance
|
||||
parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of drain capacitance
|
||||
|
||||
###################################################
|
||||
##END Spice Simulation Parameters
|
||||
|
|
|
|||
Loading…
Reference in New Issue