mirror of https://github.com/VLSIDA/OpenRAM.git
Fix pitch in channel router to support M3/M4.
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980760b724
commit
9ada9a7dfa
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@ -680,7 +680,19 @@ class layout():
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self.add_via_center(layers=layer_stack,
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offset=bus_pos,
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rotate=90)
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def get_layer_pitch(self, layer):
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""" Return the track pitch on a given layer """
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if layer=="metal1":
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return self.m1_pitch
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elif layer=="metal2":
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return self.m2_pitch
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elif layer=="metal3":
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return self.m3_pitch
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elif layer=="metal4":
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return self.m4_pitch
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else:
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debug.error("Cannot find layer pitch.")
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def add_horizontal_trunk_route(self,
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pins,
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trunk_offset,
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@ -690,7 +702,7 @@ class layout():
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Create a trunk route for all pins with the trunk located at the given y offset.
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"""
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if not pitch:
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pitch = self.m1_pitch
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pitch = self.get_layer_pitch(layer_stack[0])
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max_x = max([pin.center().x for pin in pins])
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min_x = min([pin.center().x for pin in pins])
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@ -728,7 +740,7 @@ class layout():
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Create a trunk route for all pins with the trunk located at the given x offset.
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"""
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if not pitch:
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pitch = self.m2_pitch
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pitch = self.get_layer_pitch(layer_stack[2])
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max_y = max([pin.center().y for pin in pins])
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min_y = min([pin.center().y for pin in pins])
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@ -762,7 +774,6 @@ class layout():
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def create_channel_route(self, netlist,
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offset,
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layer_stack=("metal1", "via1", "metal2"),
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pitch=None,
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vertical=False):
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"""
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The net list is a list of the nets. Each net is a list of pins
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@ -786,7 +797,7 @@ class layout():
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g[other_pin]=conflicts
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return g
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def vcg_nets_overlap(net1, net2, vertical):
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def vcg_nets_overlap(net1, net2, vertical, pitch):
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"""
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Check all the pin pairs on two nets and return a pin
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overlap if any pin overlaps
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@ -794,12 +805,12 @@ class layout():
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for pin1 in net1:
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for pin2 in net2:
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if vcg_pin_overlap(pin1, pin2, vertical):
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if vcg_pin_overlap(pin1, pin2, vertical, pitch):
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return True
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return False
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def vcg_pin_overlap(pin1, pin2, vertical):
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def vcg_pin_overlap(pin1, pin2, vertical, pitch):
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""" Check for vertical or horizontal overlap of the two pins """
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# FIXME: If the pins are not in a row, this may break.
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# However, a top pin shouldn't overlap another top pin, for example, so the
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@ -813,10 +824,10 @@ class layout():
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overlaps = (not vertical and x_overlap) or (vertical and y_overlap)
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return overlaps
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if not pitch:
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pitch = self.m2_pitch
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if vertical:
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pitch = self.get_layer_pitch(layer_stack[2])
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else:
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pitch = self.get_layer_pitch(layer_stack[0])
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# FIXME: Must extend this to a horizontal conflict graph too if we want to minimize the
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@ -846,7 +857,7 @@ class layout():
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# Skip yourself
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if net_name1 == net_name2:
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continue
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if vcg_nets_overlap(nets[net_name1], nets[net_name2], vertical):
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if vcg_nets_overlap(nets[net_name1], nets[net_name2], vertical, pitch):
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vcg[net_name2].append(net_name1)
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# list of routes to do
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@ -882,20 +893,18 @@ class layout():
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def create_vertical_channel_route(self, netlist, offset,
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layer_stack=("metal1", "via1", "metal2"),
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pitch=None):
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layer_stack=("metal1", "via1", "metal2")):
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"""
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Wrapper to create a vertical channel route
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"""
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self.create_channel_route(netlist, offset, layer_stack, pitch, vertical=True)
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self.create_channel_route(netlist, offset, layer_stack, vertical=True)
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def create_horizontal_channel_route(self, netlist, offset,
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layer_stack=("metal1", "via1", "metal2"),
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pitch=None):
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layer_stack=("metal1", "via1", "metal2")):
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"""
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Wrapper to create a horizontal channel route
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"""
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self.create_channel_route(netlist, offset, layer_stack, pitch, vertical=False)
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self.create_channel_route(netlist, offset, layer_stack, vertical=False)
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def add_boundary(self, offset=vector(0,0)):
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""" Add boundary for debugging dimensions """
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