mirror of https://github.com/VLSIDA/OpenRAM.git
Remove unused test structures
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b5b0e35c8a
commit
93c89895c9
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@ -96,22 +96,6 @@ class stimuli():
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self.sf.write(".ENDS test_{0}\n\n".format(buffer_name))
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def inst_buffer(self, buffer_name, signal_list):
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""" Adds buffers to each top level signal that is in signal_list (only for sim purposes) """
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for signal in signal_list:
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self.sf.write("X{0}_buffer {0} {0}_buf {1} {2} test_{3}\n".format(signal,
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"test"+self.vdd_name,
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"test"+self.gnd_name,
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buffer_name))
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def inst_inverter(self, signal_list):
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""" Adds inv for each signal that needs its inverted version (only for sim purposes) """
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for signal in signal_list:
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self.sf.write("X{0}_inv {0} {0}_inv {1} {2} test_inv\n".format(signal,
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"test"+self.vdd_name,
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"test"+self.gnd_name))
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def gen_pulse(self, sig_name, v1, v2, offset, period, t_rise, t_fall):
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"""
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@ -276,9 +260,6 @@ class stimuli():
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""" Writes supply voltage statements """
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gnd_node_name = "0"
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self.sf.write("V{0} {0} {1} {2}\n".format(self.vdd_name, gnd_node_name, self.voltage))
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# This is for the test power supply
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self.sf.write("V{0} {0} {1} {2}\n".format("test"+self.vdd_name, gnd_node_name, self.voltage))
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self.sf.write("V{0} {0} {1} {2}\n".format("test"+self.gnd_name, gnd_node_name, 0.0))
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#Adding a commented out supply for simulators where gnd and 0 are not global grounds.
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self.sf.write("\n*Nodes gnd and 0 are the same global ground node in ngspice/hspice/xa. Otherwise, this source may be needed.\n")
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