Added fix for column mux lib generation.:

compiler/base/hierarchy_spice.py

@@ -319,13 +319,13 @@ class spice():
         corner_slew = SLEW_APPROXIMATION*corner_delay
         return delay_data(corner_delay, corner_slew)
 
-    def get_stage_effort(self, corner, slew, load=0.0):
+    def get_stage_effort(self, cout, inp_is_rise=True):
         """Inform users undefined delay module while building new modules"""
         debug.warning("Design Class {0} logical effort function needs to be defined"
                       .format(self.__class__.__name__))
         debug.warning("Class {0} name {1}"
-                      .format(self.__class__.__name__, 
-                              self.name))         
+                      .format(self.__class__.__name__,
+                              self.name))
         return None   
         
     def get_cin(self):

compiler/characterizer/delay.py

@@ -1050,7 +1050,7 @@ class delay(simulation):
 
     def get_address_row_number(self, probe_address):
         """Calculates wordline row number of data bit under test using address and column mux size"""
-        
+
         return int(probe_address[self.sram.col_addr_size:],2)
 
     def prepare_netlist(self):
@@ -1285,7 +1285,7 @@ class delay(simulation):
             debug.warning("Analytical characterization results are not supported for multiport.")
         
         # Probe set to 0th bit, does not matter for analytical delay.
-        self.set_probe('0', 0)
+        self.set_probe('0'*self.addr_size, 0)
         self.create_graph()
         self.set_internal_spice_names()
         self.create_measurement_names()