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Enable sensing during writes. Need to add dedicated test.

This commit is contained in:
Matt Guthaus 2019-09-06 07:16:50 -07:00
parent 678b2cc3fa
commit 969cca28e4
2 changed files with 6 additions and 14 deletions
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6
compiler/characterizer/functional.py
View File

@ -70,7 +70,7 @@ class functional(simulation):
if feasible_period: #period defaults to tech.py feasible period otherwise.
self.period = feasible_period
# Generate a random sequence of reads and writes
self.write_random_memory_sequence()
self.create_random_memory_sequence()
# Run SPICE simulation
self.write_functional_stimulus()
@ -84,7 +84,7 @@ class functional(simulation):
# Check read values with written values. If the values do not match, return an error.
return self.check_stim_results()
def write_random_memory_sequence(self):
def create_random_memory_sequence(self):
if self.write_size:
rw_ops = ["noop", "write", "partial_write", "read"]
w_ops = ["noop", "write", "partial_write"]
@ -187,7 +187,7 @@ class functional(simulation):
self.add_noop_all_ports(comment, "0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks)
def read_stim_results(self):
# Extrat dout values from spice timing.lis
# Extract dout values from spice timing.lis
for (word, dout_port, eo_period, check) in self.write_check:
sp_read_value = ""
for bit in range(self.word_size):

14
compiler/modules/control_logic.py
View File

@ -639,14 +639,11 @@ class control_logic(design.design):
def create_sen_row(self):
""" Create the sense enable buffer. """
if self.port_type=="rw":
input_name = "we_bar"
else:
input_name = "cs_bar"
# GATE FOR S_EN
# Uses cs_bar (not we_bar) for feed-thru reads
self.s_en_gate_inst = self.add_inst(name="buf_s_en_and",
mod=self.sen_and3)
self.connect_inst(["rbl_bl_delay", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
self.connect_inst(["rbl_bl_delay", "gated_clk_bar", "cs_bar", "s_en", "vdd", "gnd"])
def place_sen_row(self,row):
@ -659,12 +656,7 @@ class control_logic(design.design):
def route_sen(self):
if self.port_type=="rw":
input_name = "we_bar"
else:
input_name = "cs_bar"
sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name])
sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", "cs_bar"])
self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets)
self.connect_output(self.s_en_gate_inst, "Z", "s_en")