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OpenRAM
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133 Commits

Author SHA1 Message Date
mrg 902b92223f Small fix for finding pin names in timing graph. 2020-11-16 13:57:31 -08:00
mrg 86799ae3ff Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
mrg 1d729e8f02 Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
mrg 93e94e26ec Get vdd/gnd from properties if it is defined. 2020-11-16 10:14:37 -08:00
mrg e4bc2c4914 Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
mrg 2f994b8c0a Change custom cells to use set_ports setter 2020-11-14 07:15:27 -08:00
mrg e9420d57c2 Fix missing attributes 2020-11-13 19:04:26 -08:00
mrg b4342ac527 More cleanup 2020-11-13 17:29:20 -08:00
mrg a2b17a271c Port type order generated on the fly 2020-11-13 16:41:02 -08:00
mrg 01d191da40 clk_pin is redundant in DFFs 2020-11-13 16:23:27 -08:00
mrg 620e271562 Fix various typos and errors 2020-11-13 16:04:07 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg 3567a3e913 Remove 1rw_1r 2020-11-13 08:10:16 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg 29f4ee492b Fix missing imports in replica bitcells. 2020-11-03 15:24:44 -08:00
mrg fb9956fe96 Fix missing include 2020-11-03 13:50:45 -08:00
mrg d209e8d9a3 Disable perimeter pins for now 2020-11-03 13:35:34 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg a128e0501e Use cell_name in col and row caps too. 2020-11-03 12:10:18 -08:00
mrg 87419bd640 Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg aec5865d71 Fix base class error 2020-11-02 17:41:14 -08:00
mrg f9787eb878 Use bitcell_base for all bitcells. Fix missing setup_bitcell call 2020-11-02 17:00:15 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
Tim 'mithro' Ansell bb164d915d Allow overriding the cell size layer name. 2020-11-02 10:03:52 -08:00
Tim 'mithro' Ansell 6514bcb4c1 Use default bitcell name if one isn't provided. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-11-02 09:52:00 -08:00
Tim 'mithro' Ansell 5c1250191c Fixup the bitcell.py to make subclassing work. 
Read in the GDS properties inside the __init__ method.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-11-02 09:51:54 -08:00
mrg acfec369d6 Add ptx cell properties 2020-10-28 09:54:15 -07:00
mrg 07ef43eaf8 Convert design class data to static 2020-10-27 09:23:11 -07:00
mrg 20be7caf98 Make conditional wl and bl for dummy rows/cols. 2020-10-15 13:56:37 -07:00
mrg fcb7f42e48 Remove split_wl 2020-10-12 17:27:20 -07:00
jcirimel 7f8edf6d7c fix replica bitcell col 2020-09-23 00:36:08 -07:00
jcirimel efdc171b14 make split wl specific to each port 2020-09-23 00:08:34 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
jcirimel 854d51c721 merge dev 2020-08-19 14:25:41 -07:00
jcirimel e7c9914d77 decoder passing except for bus route 2020-08-13 16:20:39 -07:00
jcirimel 3221b4ec57 update to new metal stack names 2020-07-31 05:27:19 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 40edbfa51f Error out on single port in sky130 2020-06-22 15:41:59 -07:00
mrg 54120f8405 Add option for removing subckt/instances of cells for row/col caps 2020-06-22 12:35:37 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
Joey Kunzler 7505fa5aef update for end caps 2020-05-27 20:03:11 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg 3074cf3b86 Small format cleanup 2020-04-01 11:15:29 -07:00
Bastian Koppelmann 87b5a48f9e bitcell: Remove hardcoded signal pins 
use names provided by the tech file, which can be overriden by the
technology.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:37:51 +01:00
Jesse Cirimelli-Low aedbc5f968 merge custom cell and module properties 2020-02-12 04:09:40 +00:00
jcirimel 27eced1fbe netlist_only done 2020-02-09 23:51:01 -08:00
jcirimel b212b3e85a s8 gdsless netlist only working up to dff array 2020-02-09 21:37:09 -08:00