 mrg
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5ee3f4cc66
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Many edits.
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
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2020-11-22 08:24:47 -08:00 |
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mrg
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6e51c3cda0
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PEP8 cleanup bitcell_base
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2020-11-22 07:11:08 -08:00 |
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mrg
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95573c858c
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Can redefine number of ports in custom_cell_properties
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2020-11-21 08:05:49 -08:00 |
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mrg
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aa03eec943
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Fix syntax error.
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2020-11-21 07:16:45 -08:00 |
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mrg
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4c75bc003e
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Fix bounding box of replica array to include wordline grounds.
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2020-11-21 07:03:59 -08:00 |
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mrg
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718c327527
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Fix iteration bug with new type
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2020-11-20 17:33:15 -08:00 |
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mrg
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e134e07522
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-11-20 16:57:14 -08:00 |
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mrg
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f729e9fca7
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Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions.
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2020-11-20 16:56:07 -08:00 |
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mrg
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27a652ac1b
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Fix bounding box of cap arrays
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2020-11-20 16:54:53 -08:00 |
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 Hunter Nichols
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53e64fb696
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Merge branch 'dev' into characterizer_bug_fixes
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2020-11-20 11:16:41 -08:00 |
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Hunter Nichols
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9fd473ce70
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Fixed issue with selection of column address when checking bitline names.
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2020-11-20 01:11:08 -08:00 |
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Hunter Nichols
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b201fa4bca
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Fixed path measurement in delay
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2020-11-19 22:53:38 -08:00 |
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mrg
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b77f168270
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Fix original pin name bug in bitcell too.
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2020-11-19 15:12:02 -08:00 |
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mrg
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033111a5f3
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Default to no hierarchical word lines.
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2020-11-19 10:48:35 -08:00 |
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mrg
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35c162acbd
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Use internal pin names in path names for signal traces.
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2020-11-19 08:45:09 -08:00 |
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mrg
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fbed738b4a
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Merge multiple cell_name fix.
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2020-11-18 16:27:28 -08:00 |
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mrg
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8c72d3f2e7
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PEP8 and small fix
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2020-11-18 14:01:25 -08:00 |
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mrg
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8507881ea8
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Merge branch 's8_single_port' into dev
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2020-11-18 13:59:43 -08:00 |
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 jcirimel
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50a0b88ef8
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fix typo
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2020-11-18 11:02:40 -08:00 |
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jcirimel
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520b496611
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check for cell prop names list
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2020-11-18 10:47:05 -08:00 |
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mrg
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6cfa20731c
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Consistent naming in example configs
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2020-11-18 09:59:38 -08:00 |
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mrg
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305b546ad5
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PEP8 cleanup
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2020-11-17 16:56:00 -08:00 |
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mrg
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02c1fac3b8
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Remove partial Verilog output
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2020-11-17 16:51:08 -08:00 |
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Hunter Nichols
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7a0f5e15db
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Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later.
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2020-11-17 15:05:07 -08:00 |
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Hunter Nichols
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35e1a523cc
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Changed named on delay chain sizing variable. Automatic sizing default is False.
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2020-11-17 14:29:01 -08:00 |
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Hunter Nichols
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df4c2bad1f
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Disabled debug measures that are WIP.
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2020-11-17 13:30:18 -08:00 |
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Hunter Nichols
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ac425643a0
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Merge branch 'dev' into characterizer_bug_fixes
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2020-11-17 13:22:56 -08:00 |
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Hunter Nichols
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eaf285639a
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Added debug measurements along main delay paths in SRAM. WIP.
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2020-11-17 12:43:17 -08:00 |
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mrg
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baae28194b
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Add custom cell custom port order code. Update setup/hold to use it.
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2020-11-17 11:12:59 -08:00 |
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mrg
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80333ffacb
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Fix setup/hold characterization to use custom cell and pin names/orders.
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2020-11-17 09:44:03 -08:00 |
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jcirimel
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825375d76d
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Merge branch 'dev' into s8_single_port
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2020-11-17 04:41:19 -08:00 |
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mrg
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902b92223f
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Small fix for finding pin names in timing graph.
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2020-11-16 13:57:31 -08:00 |
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mrg
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86799ae3ff
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Small bug fixes related to new name mapping.
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2020-11-16 13:42:42 -08:00 |
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mrg
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1d729e8f02
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Move pin name mapping to layout class.
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2020-11-16 11:04:03 -08:00 |
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mrg
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93e94e26ec
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Get vdd/gnd from properties if it is defined.
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2020-11-16 10:14:37 -08:00 |
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mrg
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7512aa6e70
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Skip test 50 which is too slow
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2020-11-16 08:59:25 -08:00 |
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mrg
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e4bc2c4914
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Update property settings with getters/setters
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2020-11-14 08:08:42 -08:00 |
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mrg
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2f994b8c0a
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Change custom cells to use set_ports setter
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2020-11-14 07:15:27 -08:00 |
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mrg
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1624d50ca9
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Fix props bug again.
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2020-11-13 20:35:19 -08:00 |
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mrg
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e9420d57c2
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Fix missing attributes
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2020-11-13 19:04:26 -08:00 |
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mrg
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b4342ac527
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More cleanup
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2020-11-13 17:29:20 -08:00 |
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mrg
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a2b17a271c
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Port type order generated on the fly
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2020-11-13 16:41:02 -08:00 |
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mrg
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01d191da40
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clk_pin is redundant in DFFs
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2020-11-13 16:23:27 -08:00 |
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mrg
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620e271562
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Fix various typos and errors
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2020-11-13 16:04:07 -08:00 |
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mrg
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8021430122
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Fix pbitcell erros
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2020-11-13 15:55:55 -08:00 |
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mrg
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c472a94f1e
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Rework bitcells.
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
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2020-11-13 10:07:40 -08:00 |
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mrg
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3567a3e913
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Remove 1rw_1r
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2020-11-13 08:10:16 -08:00 |
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mrg
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cf63499e76
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Convert bitcells to 1port and 2port
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2020-11-13 08:09:21 -08:00 |
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mrg
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198c0faf85
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Remove special s8 6t names
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2020-11-13 07:45:31 -08:00 |
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mrg
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662d4ea724
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Merge remote-tracking branch 'private/drclvs' into dev
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2020-11-12 16:01:07 -08:00 |
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