 mrg
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01fe02bd90
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Fixes to replica bitline array.
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
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2020-10-08 14:53:44 -07:00 |
|
 jcirimel
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1e7ae06b7e
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fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end
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2020-10-08 05:32:03 -07:00 |
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jcirimel
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d40c3588ed
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no wl for col end
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2020-10-08 03:34:16 -07:00 |
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jcirimel
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4a1a7e637e
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merge in dev
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2020-10-07 11:54:07 -07:00 |
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mrg
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483f6b187c
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RBL driver supply location differs for sky130 and other techs
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2020-10-06 16:47:32 -07:00 |
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mrg
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c2629edc1b
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Allow 16-way column mux
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2020-10-06 16:27:02 -07:00 |
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|
jcirimel
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13e2a9f5f7
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fix missed self.left_rbl refactor
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2020-10-06 05:11:15 -07:00 |
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jcirimel
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888646cdf9
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merge in wlbuf and begin work on 32kb memory
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2020-10-06 05:03:59 -07:00 |
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mrg
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da83824a70
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Merge branch 'wlbuffer' into dev
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2020-10-05 15:33:54 -07:00 |
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|
mrg
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4a58f09c1c
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Use 4x16 decoder with dual port bitcell in tests.
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2020-10-05 10:52:56 -07:00 |
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mrg
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c06b02e6fc
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Rename single_level_column_mux to just column_mux
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2020-10-05 08:56:51 -07:00 |
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mrg
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f8146e3f69
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Add decoder4x16
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2020-10-02 15:52:09 -07:00 |
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mrg
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8ce23d7f17
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Provide unique WL driver instance name
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2020-10-01 07:17:32 -07:00 |
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|
Matt Guthaus
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112d57d90a
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Enable riscv tests
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2020-09-30 12:39:40 -07:00 |
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mrg
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f4e6a8895b
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Update riscv unit test
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2020-09-30 08:50:58 -07:00 |
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jcirimel
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7cbf456a4f
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sky130 rba done
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2020-09-30 07:34:05 -07:00 |
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|
mrg
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b147e8485c
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PEP8 formatting
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2020-09-29 16:52:27 -07:00 |
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|
mrg
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066570bfeb
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Fix length of write driver
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2020-09-29 16:51:55 -07:00 |
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mrg
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449a4c2660
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Exclude bitcells in other local areas not of interest
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2020-09-29 12:15:42 -07:00 |
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|
mrg
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d7e2340e62
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Lots of PEP8 cleanup. Refactor path graph to simulation class.
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2020-09-29 10:26:31 -07:00 |
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mrg
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b2dab486fc
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Add draft of path exclusion calls
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2020-09-28 16:05:21 -07:00 |
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mrg
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4a987bef9a
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Merge branch 'wlbuffer' into dev
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2020-09-28 15:51:45 -07:00 |
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mrg
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159c04a25d
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-09-28 15:51:35 -07:00 |
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|
mrg
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70c90ca7fb
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Replica bitcell array bbox to include unused WL gnd pins.
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2020-09-28 14:49:33 -07:00 |
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mrg
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9c6d8d7aed
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Zjob to bottom.
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2020-09-28 13:16:03 -07:00 |
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mrg
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5ab0d01779
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Remove zjog and go with L shape.
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2020-09-28 12:48:37 -07:00 |
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mrg
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d65eb16513
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Zjog the WL enable. Min driver is 1.
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2020-09-28 12:24:55 -07:00 |
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mrg
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6f06bb9dd5
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Create sized RBL WL driver in port_address
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2020-09-28 11:30:21 -07:00 |
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|
mrg
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88731ccd8e
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Fix rounding error for wmask with various word_size
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2020-09-28 09:53:01 -07:00 |
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|
jcirimel
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3dd72cdeac
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progress with rba pin mismatch
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2020-09-23 08:37:32 -07:00 |
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|
jcirimel
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17e6e5eb16
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row end col done
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2020-09-23 08:02:56 -07:00 |
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|
jcirimel
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5c263e0001
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rep col done w/o power pins
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2020-09-23 06:24:52 -07:00 |
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|
jcirimel
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7afe3ea52c
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replica col arrangement done
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2020-09-23 04:51:09 -07:00 |
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|
jcirimel
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efdc171b14
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make split wl specific to each port
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2020-09-23 00:08:34 -07:00 |
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|
jcirimel
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fb6a665514
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removed references to technology name
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2020-09-22 18:33:03 -07:00 |
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|
jcirimel
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de33ab3761
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fix single port bitcell pattern
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2020-09-22 15:08:53 -07:00 |
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mrg
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c7d32089f3
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Create RBL wordline buffer with correct polarity.
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2020-09-17 14:45:49 -07:00 |
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|
jcirimel
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559dfbc7a6
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single port bitcell array done
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2020-09-16 05:46:14 -07:00 |
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|
mrg
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e7ad22ff69
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Separate WL via from bitell array to avoid grounded WLs
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2020-09-15 13:38:28 -07:00 |
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|
mrg
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5e94d76127
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Make global bitline only as wide as needed rather than whole array
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2020-09-15 13:24:38 -07:00 |
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mrg
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aff3cd2aab
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Update length of control bus
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2020-09-15 09:49:00 -07:00 |
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|
jcirimel
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d22164bd48
|
single port progess
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2020-09-14 18:11:38 -07:00 |
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mrg
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f25b6ffa61
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Make control bus height of port data
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2020-09-14 15:42:17 -07:00 |
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mrg
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7b24d1f012
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Use pins for write_driver dimensions
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2020-09-14 14:42:28 -07:00 |
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|
mrg
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55dd4d0c47
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Global bitcell array working
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2020-09-14 14:35:52 -07:00 |
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|
mrg
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deaaec1ede
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Fix width of write enable with spare columns
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2020-09-14 13:09:45 -07:00 |
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|
mrg
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c12720a93f
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Extend pin correct length in new array.
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2020-09-14 12:53:59 -07:00 |
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|
mrg
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e95ab66916
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Update to space according to the bitcell array.
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2020-09-14 12:05:45 -07:00 |
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|
mrg
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4482c63d6f
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Fix sense amp offset index error
|
2020-09-11 17:12:29 -07:00 |
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|
mrg
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8909ad7165
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Update modules to use variable bit offsets.
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
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2020-09-11 15:36:22 -07:00 |
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