| .. |
|
bank.py
|
Create sized RBL WL driver in port_address
|
2020-09-28 11:30:21 -07:00 |
|
bank_select.py
|
Change inheritance inits to use super
|
2020-08-06 11:33:26 -07:00 |
|
bitcell_array.py
|
Merge branch 'dev' into wlbuffer
|
2020-09-10 13:05:14 -07:00 |
|
bitcell_base_array.py
|
Update to space according to the bitcell array.
|
2020-09-14 12:05:45 -07:00 |
|
col_cap_array.py
|
Allow replica_bitcell_array without the replica columns for local wordlines.
|
2020-07-27 16:22:21 -07:00 |
|
control_logic.py
|
Removed dead code related to older characterization scheme
|
2020-08-27 17:30:58 -07:00 |
|
delay_chain.py
|
Removed dead code related to older characterization scheme
|
2020-08-27 17:30:58 -07:00 |
|
dff_array.py
|
Removed dead code related to older characterization scheme
|
2020-08-27 17:30:58 -07:00 |
|
dff_buf.py
|
Removed dead code related to older characterization scheme
|
2020-08-27 17:30:58 -07:00 |
|
dff_buf_array.py
|
Removed dead code related to older characterization scheme
|
2020-08-27 17:30:58 -07:00 |
|
dff_inv.py
|
Removed dead code related to older characterization scheme
|
2020-08-27 17:30:58 -07:00 |
|
dff_inv_array.py
|
Removed dead code related to older characterization scheme
|
2020-08-27 17:30:58 -07:00 |
|
dummy_array.py
|
Merge branch 'dev' into wlbuffer
|
2020-09-10 13:05:14 -07:00 |
|
global_bitcell_array.py
|
Create sized RBL WL driver in port_address
|
2020-09-28 11:30:21 -07:00 |
|
hierarchical_decoder.py
|
Create RBL wordline buffer with correct polarity.
|
2020-09-17 14:45:49 -07:00 |
|
hierarchical_predecode.py
|
Change inheritance inits to use super
|
2020-08-06 11:33:26 -07:00 |
|
hierarchical_predecode2x4.py
|
Change inheritance inits to use super
|
2020-08-06 11:33:26 -07:00 |
|
hierarchical_predecode3x8.py
|
Change inheritance inits to use super
|
2020-08-06 11:33:26 -07:00 |
|
hierarchical_predecode4x16.py
|
Change inheritance inits to use super
|
2020-08-06 11:33:26 -07:00 |
|
local_bitcell_array.py
|
Create sized RBL WL driver in port_address
|
2020-09-28 11:30:21 -07:00 |
|
module_type.py
|
Cleanup and rename vias.
|
2020-01-30 01:45:33 +00:00 |
|
multibank.py
|
Change inheritance inits to use super
|
2020-08-06 11:33:26 -07:00 |
|
port_address.py
|
Create sized RBL WL driver in port_address
|
2020-09-28 11:30:21 -07:00 |
|
port_data.py
|
Update to space according to the bitcell array.
|
2020-09-14 12:05:45 -07:00 |
|
precharge_array.py
|
Update to space according to the bitcell array.
|
2020-09-14 12:05:45 -07:00 |
|
replica_bitcell_array.py
|
Separate WL via from bitell array to avoid grounded WLs
|
2020-09-15 13:38:28 -07:00 |
|
replica_column.py
|
Use default names for replica_column too
|
2020-09-10 12:04:46 -07:00 |
|
row_cap_array.py
|
Allow replica_bitcell_array without the replica columns for local wordlines.
|
2020-07-27 16:22:21 -07:00 |
|
sense_amp.py
|
Removed dead code related to older characterization scheme
|
2020-08-27 17:30:58 -07:00 |
|
sense_amp_array.py
|
Extend pin correct length in new array.
|
2020-09-14 12:53:59 -07:00 |
|
single_level_column_mux_array.py
|
Update to space according to the bitcell array.
|
2020-09-14 12:05:45 -07:00 |
|
tri_gate_array.py
|
Change inheritance inits to use super
|
2020-08-06 11:33:26 -07:00 |
|
wordline_buffer_array.py
|
Create RBL wordline buffer with correct polarity.
|
2020-09-17 14:45:49 -07:00 |
|
wordline_driver_array.py
|
Create RBL wordline buffer with correct polarity.
|
2020-09-17 14:45:49 -07:00 |
|
write_driver_array.py
|
Use pins for write_driver dimensions
|
2020-09-14 14:42:28 -07:00 |
|
write_mask_and_array.py
|
Update modules to use variable bit offsets.
|
2020-09-11 15:36:22 -07:00 |
6f06bb9dd5