jcirimel efdc171b14 make split wl specific to each port

2020-09-23 00:08:34 -07:00

..

bank_select.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

bank.py

Merge branch 'wlbuffer' into dev

2020-08-26 10:00:34 -07:00

bitcell_array.py

make split wl specific to each port

2020-09-23 00:08:34 -07:00

bitcell_base_array.py

make split wl specific to each port

2020-09-23 00:08:34 -07:00

col_cap_array.py

Allow replica_bitcell_array without the replica columns for local wordlines.

2020-07-27 16:22:21 -07:00

control_logic.py

Merge branch 'dev' into pex

2020-08-17 17:49:41 -07:00

custom_cell.py

single port progess

2020-09-14 18:11:38 -07:00

delay_chain.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

dff_array.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

dff_buf_array.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

dff_buf.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

dff_inv_array.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

dff_inv.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

dummy_array.py

Draft local and global arrays. Ensure rows before cols in usage.

2020-07-23 14:43:14 -07:00

global_bitcell_array.py

Still working on array refactor

2020-08-25 11:50:44 -07:00

hierarchical_decoder.py

merge dev

2020-08-19 14:25:41 -07:00

hierarchical_predecode2x4.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

hierarchical_predecode3x8.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

hierarchical_predecode4x16.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

hierarchical_predecode.py

fix column decoder

2020-08-25 02:46:16 -07:00

local_bitcell_array.py

Fixed local bitcell array for single and dual port

2020-08-27 14:03:05 -07:00

module_type.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

multibank.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

orig_bitcell_array.py

single port progess

2020-09-14 18:11:38 -07:00

port_address.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

port_data.py

Still working on array refactor

2020-08-25 11:50:44 -07:00

precharge_array.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

replica_bitcell_array.py

single port progess

2020-09-14 18:11:38 -07:00

replica_column.py

Fix disconnected replica pins

2020-08-25 14:51:49 -07:00

row_cap_array.py

Allow replica_bitcell_array without the replica columns for local wordlines.

2020-07-27 16:22:21 -07:00

sense_amp_array.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

sense_amp.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

single_level_column_mux_array.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

tri_gate_array.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

wordline_buffer_array.py

Replica bitcell with all the fixings

2020-08-11 15:00:29 -07:00

wordline_driver_array.py

Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

2020-08-17 14:20:34 -07:00

write_driver_array.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

write_mask_and_array.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00