4039 Commits

Include renames

Author	SHA1	Message	Date
Sam Crow	efbb658784	add no rbl support to port address	2023-04-05 16:04:20 -07:00
Sam Crow	ae6d271602	add support for no rbl to port data	2023-04-05 15:33:45 -07:00
Sam Crow	d00ba73bc9	add no rbl support to global array	2023-04-05 14:47:15 -07:00
Sage Walker	b2bcbddd01	ROM binary file support	2023-04-03 16:04:12 -07:00
Sam Crow	83b25138d0	apply 14* standard to 15_local tests	2023-04-03 10:11:49 -07:00
Sam Crow	9181f6a218	standardize 14* test structure	2023-04-03 10:08:57 -07:00
Jacob Walker	0b056dca54	fixed rom bank test name	2023-03-30 18:44:55 -07:00
Jacob Walker	52791a2719	a space	2023-03-30 11:30:50 -07:00
Jacob Walker	c1fb3cab6c	1kb rom DRC clean	2023-03-30 11:30:50 -07:00
Jacob Walker	7805fcb21e	more top level routing cleanup	2023-03-30 11:30:50 -07:00
Jacob Walker	fef9902c45	rom base passing tests with top level routing	2023-03-30 11:30:50 -07:00
mrg	7c453e80be	Simplify ROM test.	2023-03-30 11:30:50 -07:00
mrg	af0a6d32fb	Remove old skip tests	2023-03-30 11:30:50 -07:00
mrg	2075d244cb	Change ROM test permissions to include x	2023-03-30 11:30:50 -07:00
Jacob Walker	4c34a54d32	top level boundary fixes	2023-03-30 11:30:50 -07:00
Jacob Walker	7fe5ed5c41	edge routing	2023-03-30 11:30:50 -07:00
Jacob Walker	09f9c4cc20	some rom bank cleanup	2023-03-30 11:30:50 -07:00
mrg	56e14113aa	Change rom_base_bank name and top pin names	2023-03-30 11:30:50 -07:00
mrg	d2b5be0130	Add exclude tests for ROMs	2023-03-30 11:30:50 -07:00
mrg	fe65a20431	Rename ROM unit tests.	2023-03-30 11:30:50 -07:00
Jacob Walker	eec0f02bb8	skip test file	2023-03-30 11:30:50 -07:00
Jacob Walker	b50ec272da	updated top level rom unit tests	2023-03-30 11:30:50 -07:00
Jacob Walker	41f0b9a412	rom compiler top level	2023-03-30 11:30:50 -07:00
Jacob Walker	2d5199961d	revert changes to pinvbuf	2023-03-30 11:30:50 -07:00
Jacob Walker	382c91f342	precharge array test passing sky130	2023-03-30 11:30:50 -07:00
Jacob Walker	92251fe61e	more code cleaning	2023-03-30 11:30:50 -07:00
Jacob Walker	90cf382a43	removed hardcoded DRC rule	2023-03-30 11:30:50 -07:00
Jacob Walker	0cb4459b4b	changed ROM test data path	2023-03-30 11:30:50 -07:00
Jacob Walker	af0209ec96	passing code style	2023-03-30 11:30:50 -07:00
Jacob Walker	79efff9ca6	code cleanup and updated copyright	2023-03-30 11:30:50 -07:00
Jacob Walker	bbf2cd2913	Changes for test generation and simulation	2023-03-30 11:30:50 -07:00
Jacob Walker	89c7d50bd1	added row of nmos to end of array for precharge	2023-03-30 11:30:50 -07:00
SWalker	f847721500	changes to control logic, invert polarity of precharge	2023-03-30 11:30:50 -07:00
SWalker	9cefe5da7c	added unrouted output buffers	2023-03-30 11:30:50 -07:00
SWalker	764601a721	added binning to precharge pmos	2023-03-30 11:30:50 -07:00
Jesse Cirimelli-Low	6981cfa58b	add example of writing out simulation netlist	2023-03-30 11:30:50 -07:00
Jacob Walker	736bd51fe1	add top level pins for sim	2023-03-30 11:30:50 -07:00
Jacob Walker	81bf2d7ae7	fixed decode lvs	2023-03-30 11:30:50 -07:00
Jacob Walker	16df8e0e43	fixing decoder lvs	2023-03-30 11:30:50 -07:00
Jacob Walker	559300e5cc	taps in main array and decoder	2023-03-30 11:30:50 -07:00
Jacob Walker	f7aed247fd	column control and address precharge	2023-03-30 11:30:50 -07:00
Jacob Walker	ce8197d206	pitch match decoder and array	2023-03-30 11:30:50 -07:00
Jacob Walker	e697efa5f6	fixed base array lvs	2023-03-30 11:30:50 -07:00
Jacob Walker	b2631b60ff	updated imports to match upstream dev openram	2023-03-30 11:30:50 -07:00
Jacob Walker	63925bd48e	Decoder array and start of rom bank	2023-03-30 11:30:50 -07:00
Jacob Walker	bc8d564dbf	array with poly straps passing drc/lvs	2023-03-30 11:30:50 -07:00
Jacob Walker	aea3c0ad01	passing drc/lvs on 4x4 rom array	2023-03-30 11:30:50 -07:00
Jacob Walker	a3e271f6fb	reoriented cell and added tap cell	2023-03-30 11:30:50 -07:00
Jacob Walker	7309af7e29	base and dummy array alignment in sky130	2023-03-30 11:30:50 -07:00
Jacob Walker	d7ac26a053	array generation and bitline routing with array module	2023-03-30 11:30:50 -07:00