 Eren Dogan
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6b0b4c2def
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Create fake pins on the ring and route others to them
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2023-07-10 09:24:16 -07:00 |
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Eren Dogan
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4a61874888
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Add supply ring pins around the layout area
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2023-07-09 18:53:21 -07:00 |
|
 Bugra Onal
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7220e0a483
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sim_exe will be found everytime with func and char
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2023-07-07 12:39:19 -07:00 |
|
 Sam Crow
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b91c628acf
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Merge branch 'dev' into delay_ctrl
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2023-07-06 08:45:03 -07:00 |
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Sam Crow
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468c972acb
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add optional guard band to delay chain sizing
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2023-07-05 16:34:42 -07:00 |
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Sam Crow
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d65ccfcc95
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fix column mux without rbl start_bit to 0
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2023-07-05 13:17:46 -07:00 |
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Sam Crow
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b4a9784835
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model vth delay swing delay
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2023-07-05 12:17:48 -07:00 |
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Sam Crow
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5235cf9667
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model p_en and wl_en delays in delay chain sizing
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2023-07-03 17:02:11 -07:00 |
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Eren Dogan
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bb35ac2f90
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Include new wires while routing the pins
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2023-07-03 14:04:26 -07:00 |
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Eren Dogan
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0938e7ec9a
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Fix probes not being blocked correctly
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2023-07-03 13:34:27 -07:00 |
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Eren Dogan
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78be525ea0
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Use minimum spanning tree to route same type of pins together
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2023-07-01 16:14:56 -07:00 |
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Sam Crow
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e1865083d7
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incomplete work on improved delay modeling
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2023-06-29 14:44:42 -07:00 |
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Eren Dogan
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5bf629f3e5
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Prevent DRC violations for vdd and gnd pins
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2023-06-28 20:55:49 -07:00 |
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Sam Crow
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91694fdae3
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add fixme note for unit conversion
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2023-06-28 14:05:42 -07:00 |
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Sam Crow
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28ea93bd0a
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convert 1-indexing to 0-indexing
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2023-06-25 11:03:10 -07:00 |
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Sam Crow
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006eacd6d0
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add pinout message output
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2023-06-25 10:46:58 -07:00 |
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Sam Crow
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8992c0fb68
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first approximation of delay values
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2023-06-20 16:22:03 -07:00 |
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Eren Dogan
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a47bc7ebee
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Prevent multiple dog-legs in non-preferred direction
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2023-06-15 11:08:13 -07:00 |
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Sam Crow
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dbc9de6c9a
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implement relationship between delay pinouts
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2023-06-14 17:10:07 -07:00 |
|
 Gary Mejia
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9a36cce7ae
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Fixed formatting on all files
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2023-06-14 12:28:36 -07:00 |
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Gary Mejia
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b9e61f346a
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Merge branch 'dev' into openROM-verilogoutput
To test recent changes with ROM verilog output
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2023-06-14 12:26:07 -07:00 |
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Gary Mejia
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a3284e8b47
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Fixed module from writing syntax issues
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2023-06-13 17:30:38 -07:00 |
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Sam Crow
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bf516a927d
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add skeleton for delay chain sizing
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2023-06-13 13:44:32 -07:00 |
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Sam Crow
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fee90283b9
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add spacing and a comment
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2023-06-12 16:56:44 -07:00 |
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Gary Mejia
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692acd2066
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Verilog ROM model created for testing
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2023-06-12 15:35:54 -07:00 |
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Sam Crow
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96a1d400fa
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add single port bank test for norbl
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2023-06-12 12:50:50 -07:00 |
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Sam Crow
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266bcd9cf2
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consolidate failing xyce delay tests to one in skip list
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2023-06-11 14:52:26 -07:00 |
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Sam Crow
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854bff9dce
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add norbl bank tests to sky130 skipped tests
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2023-06-08 13:22:12 -07:00 |
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Sam Crow
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7048a072e2
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add local/global array sky130 skipped tests
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2023-06-08 13:16:27 -07:00 |
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Sam Crow
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44ed72b50d
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add has_rbl=True arg to tests
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2023-06-08 13:10:03 -07:00 |
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Sam Crow
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ce622952ef
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route rbl conditionally
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2023-06-08 12:36:31 -07:00 |
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Sam Crow
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a51b71d460
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update copyright
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2023-06-08 12:36:12 -07:00 |
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Sam Crow
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973b5512f0
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add new failing sky130 tests to skip list
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2023-06-07 17:29:58 -07:00 |
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Sam Crow
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dcf95460d0
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sort sky130 skipped tests numerically
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2023-06-07 16:09:18 -07:00 |
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Sam Crow
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9256ae8c00
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fix typos and standardize multiport control logic tests
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2023-06-07 16:04:54 -07:00 |
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samuelkcrow
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afd3b782b9
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remove cs_bar signal bus from all control logics
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2023-06-07 15:53:15 -07:00 |
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samuelkcrow
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a48842ff72
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fix code format issues from 00 test
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2023-06-07 15:52:25 -07:00 |
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samuelkcrow
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b9492051b6
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use control_logic_base in control_logic_delay
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2023-06-07 15:51:19 -07:00 |
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Sam Crow
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a70dcc5c85
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reword comments in replica bitcell array module
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2023-06-06 14:43:18 -07:00 |
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Sam Crow
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9fdf8a8341
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ommit rbl pins in sram_1bank when appropriate
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2023-06-06 13:15:17 -07:00 |
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Sam Crow
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157935c915
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update test/module imports related to delay control
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2023-06-06 13:12:20 -07:00 |
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Eren Dogan
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15b4e4dbe8
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Fix DRC spacing in Hanan router
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2023-06-05 19:33:45 -07:00 |
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Sam Crow
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5fef78dbfa
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Merge branch 'no_rbl' into delay_ctrl
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2023-06-05 16:31:07 -07:00 |
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Sam Crow
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2f5d3b6faf
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Merge branch 'dev' into delay_ctrl
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2023-06-05 16:24:48 -07:00 |
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Sam Crow
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df827fbd3d
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add norbl whole sram test
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2023-06-05 15:26:26 -07:00 |
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Sam Crow
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5b10f06be6
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place wl_en pin on wl drivers in absence of rbl_wl driver
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2023-06-05 15:26:11 -07:00 |
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Sam Crow
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0b5039cc89
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make norbl bank test executable
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2023-06-05 12:08:22 -07:00 |
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Eren Dogan
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48a148003a
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Include other pins as blockages in Hanan router
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2023-06-05 11:27:05 -07:00 |
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Sam Crow
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23232fd376
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Merge branch 'dev' into no_rbl
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2023-06-05 11:03:22 -07:00 |
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Eren Dogan
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8f1af0ebb7
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Reduce the number of shapes on Hanan paths
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2023-06-04 10:56:50 -07:00 |
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