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prjxray
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299 Commits

Author SHA1 Message Date
litghost 0e8ff9b64e
Merge pull request #1157 from antmicro/iostandard_minitest 
Minitest for different IOSTANDARDs
 2019-12-09 11:09:33 -08:00
Maciej Kurc eef8ec93cb Added ignoring of PUDC_B pin. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-09 14:40:35 +01:00
Maciej Kurc 75c6ff27de A minitest for Zynq7 EMIO PS->PL interface. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-03 15:39:13 +01:00
Maciej Kurc 20475bfd6a Review comments. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-03 12:07:04 +01:00
Maciej Kurc d9fc7b3f7e Fixed semicolon 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-02 10:34:37 +01:00
Maciej Kurc 0fb79b8753 Fixed bug with diff pair loc-ing. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-02 10:16:21 +01:00
Maciej Kurc c396b0f9cc Added support for differential standards. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-11-29 16:29:41 +01:00
Maciej Kurc e8b05c6b27 Minitest for different IOSTANDARDs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-11-29 13:55:14 +01:00
Tim 'mithro' Ansell 7386641d9b Fix trailing white space. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-11-03 15:07:24 -08:00
litghost daf284151c
Merge pull request #1119 from antmicro/litex_litedram 
minitests: Add test for Litex DRAM memory interface
 2019-10-30 10:40:01 -07:00
litghost 78cf96be0f
Merge pull request #1122 from JakeMercer/whitespace 
Whitespace
 2019-10-29 15:04:39 -07:00
Maciej Kurc 4a6930694f Reworked fuzzer, added README.md 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Jake Mercer c05b4b0406 MAKE - Format Trailing Whitespace 
Add `make format-trailing-ws`.  This recipe finds all _files_ (not
links) known to Git and uses `sed` to remove trailing whitespace.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-10-26 10:04:52 +01:00
Tomasz Michalak 43fe925ff3 minitests: Add test for Litex DRAM memory interface 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-10-24 14:28:37 +02:00
litghost c94cb0224c
Revert "Whitespace" 2019-10-23 14:22:17 -07:00
Jake Mercer bf11f43390 FORMAT - Run `make format` 
Changes after running `make format`.  Future commits which add
whitespace should be caught by CI at the PR stage.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-10-22 19:35:24 +01:00
Leonardo Romor c138c156ed
Applied requested changes to use XRAY_UTILS_DIR 
Signed-off-by: Leonardo Romor <leonardo.romor@gmail.com>
 2019-10-10 19:50:02 +02:00
Leonardo Romor 48755a1128
Updated wrong string path added in syspath before import 
Signed-off-by: Leonardo Romor <leonardo.romor@gmail.com>
 2019-10-10 19:20:32 +02:00
Tim Ansell ecfd250a28
Merge pull request #1068 from antmicro/litex_readme 
Updated README.md for LiteX minitest
 2019-09-30 10:08:47 +02:00
litghost 22750bc2ce
Merge pull request #1058 from antmicro/pll_minitest 
Minitest for PLLE2_ADV
 2019-09-26 10:06:53 -07:00
Maciej Kurc dd26790d65 Updated README.md, added different phase settings to the PLL. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-26 09:47:58 +02:00
Tim Ansell d78b50af8b
Merge pull request #1040 from antmicro/fix-sphinx-xref-links 
Fixing documentation cross-reference links
 2019-09-25 10:29:07 -07:00
Maciej Kurc 1f31c98265 Updated README.md 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-25 12:13:11 +02:00
Alessandro Comodi 2fab112c71 docs: fixed some READMEs and removed empty .md file generation 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-09-25 09:54:28 +02:00
Maciej Kurc 32feed6640 Removed BUFR and BUFMR, clock division implemented on logic. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-24 10:45:09 +02:00
Maciej Kurc 31ba200080 Minitest for PLLE2_ADV. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-20 11:20:30 +02:00
Maciej Kurc 2b3ca04914 Removed the need for physical pin loopback. The design now transmitts and receives using the same pins. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-12 15:08:05 +02:00
Maciej Kurc e722712661 Formatting 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-12 14:35:37 +02:00
Maciej Kurc 0ebe592dca Updated docs. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-12 14:35:37 +02:00
Maciej Kurc b878a2e651 A minitest for ISERDES in NETWORKING SDR/DDR modes. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-12 14:35:37 +02:00
litghost 6d21194b56
Merge pull request #1047 from antmicro/oserdes_minitest 
OSERDES minitest
 2019-09-11 09:13:48 -07:00
Maciej Kurc b31345010c OSERDES minitest without the need for hardware loopbacks. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-11 13:34:07 +02:00
Maciej Kurc 2f143b18b8 Code polish 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-03 16:36:07 +02:00
Maciej Kurc baf288ad24 A minitest for ISERDES+IDELAY 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-03 16:23:45 +02:00
Keith Rothman 6c4e6aa718 Update HCLK_IOI offset to match tilegrid 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 17:18:48 -07:00
Keith Rothman 2c7b64ea22 Create script for generating remaining bit report. 
This report is fairly fragile, but works well enough for the remaining
LiteX bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 15:04:29 -07:00
Keith Rothman fa2f61f914 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 17:21:26 -07:00
Keith Rothman a7ba547acb Filter out non-IOB bits. 
Also add output from LiteX to verify IOB FASM features.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 13:38:03 -07:00
Keith Rothman 3345f30817 Fix D9/B8 in arty-swbut harness. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-10 17:15:18 -07:00
litghost 559f840097
Merge pull request #916 from antmicro/srl_minitests 
Minitests for SRLs
 2019-07-09 09:10:36 -07:00
Maciej Kurc 5c60639442 Added generation of sorted and "uniqued" FASM output 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-05 12:03:30 +02:00
Maciej Kurc cbbf46112f Updated EDIF write to include cell attributes 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-02 16:03:02 +02:00
Maciej Kurc 4d6f75e8ad Added packing tests for SRL32+LUT6 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-28 10:53:27 +02:00
Maciej Kurc 98bcd3f447 Added full vivado flow to the Makefile 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-28 10:53:22 +02:00
Maciej Kurc 4c2b0a5395 Added minitests for SRLs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-27 15:13:18 +02:00
Keith Rothman e697365c7d Add ROI base file that adds a clock divider. 
This cannot be used for an ROI harness until
https://github.com/SymbiFlow/prjxray/issues/891 is complete.

Command to build new harness
```
XRAY_ROIV=../roi_base_div2.v make
```

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-25 12:05:44 -07:00
Maciej Kurc 68c810ce3b Added source files dependencies to Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-25 10:14:20 +02:00
Maciej Kurc 64a05b4fa2 Changed makefiles to use XRAY_DIR 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-19 09:19:28 +02:00
Maciej Kurc bf1c7d3183 Fixed invication of prjxray scripts in Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 13:00:23 +02:00
Maciej Kurc 728a6a76d2 Added bitread and segprint to the Makefile flow 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-17 14:52:06 +02:00
Maciej Kurc 3783e7b2e3 Fixed the LiteX generated SoC to be Linux capable 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-17 13:45:11 +02:00
Maciej Kurc 4798c08ad8 Changed Vivado invocation 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-14 09:40:21 +02:00
Maciej Kurc 4f459cfde3 Ran format-tcl 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:39:49 +02:00
Maciej Kurc 421af109b1 Added bit2fasm targets to Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:29:20 +02:00
Maciej Kurc 0c244f242d Added submodule with Yosys and integrated it with the LiteX minitest 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:16:11 +02:00
Maciej Kurc 01f77fd2b2 Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 15:58:06 +02:00
Keith Rothman 259894f81d Add README for timing minitest. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-05-29 15:05:18 -07:00
Keith Rothman 992280f3b1 Add timing model minitest. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-05-29 14:55:04 -07:00
Keith Rothman 36177e9599 Add make targets to build additional outputs from each database. 
These targets are for:
 - Generating additional database outputs that are part, e.g. yaml files.
 - Generating harnesses

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-10 11:55:39 -07:00
Tim 'mithro' Ansell 5c61326d8b minitest/roi_harness: Move comments around to improve formatting. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-03-26 19:08:49 -07:00
Tim 'mithro' Ansell a3a5ffd45b minitests/roi_harness: Updating README. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-03-26 18:29:07 -07:00
Tim 'mithro' Ansell a8ff30b32f minitest/roi_harness: Strip trailing spaces 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-03-26 18:29:07 -07:00
Tim 'mithro' Ansell 9fc2649e86 minitest/roi_harness: Fixing comment indenting. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-03-26 18:29:07 -07:00
Tim 'mithro' Ansell 1123f2458f minitests/roi_harness: Adding harness configs. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-03-26 18:29:02 -07:00
Tomasz Michalak 6d818dc0ad add bits outside ROI to required features 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-03-21 16:43:59 +01:00
Lukasz Dalek ef9226e969 roi_harness: Add ARTY-A7-UART configuration 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2019-03-13 17:13:18 +01:00
Lukasz Dalek 49c8aac143 zybo: Fix Zybq Zynq-7 roi_harness 
Fixed ROI_GRID range and Y_DOUT_BASE. Updated INPUT and OUTPUT pads.

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2019-03-12 09:48:06 +01:00
Keith Rothman 2a114a9726 Output required_features as a list rather than a string with newlines. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-02-21 15:40:07 -08:00
Keith Rothman 1b4b2152db Format harness JSON file. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-02-20 11:45:03 -08:00
Keith Rothman b1c822cb98 Fix review comments. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-02-14 08:27:43 -08:00
Keith Rothman 8387eb8c32 Update FASM tools to use new required_features. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-02-12 17:58:42 -08:00
Keith Rothman f0f29956d7 Add FASM features that are outside ROI grid, but inside used frames. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-02-12 17:25:52 -08:00
Alessandro Comodi b73f1c2161 roi_harness: added arty.sh settings 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-02-05 15:48:52 +01:00
Alessandro Comodi 50d20918e1 roi_harness: adding env variables for INT_LR tiles and PIPs 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-02-05 12:40:37 +01:00
Alessandro Comodi c1be26f053 roi_harness: update runme.tcl to have variable y_offset 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-02-04 14:17:16 +01:00
Alessandro Comodi 3c1de3617e roi_harness: fix basys3 and arty settings 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-02-04 13:39:31 +01:00
Alessandro Comodi a84cb88b1e roi_harness: added zybo support 
Fixed also basys3 settings to produce a correct harness for the basys

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-02-04 12:45:27 +01:00
Karol Gugala 9ca49d1979 minitests: ROI harness: call python interpreter explicitly 
The scripts do not have execution rights, so the build fails on calling them.
Explicit interpreter call solves the issue.

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-18 10:21:00 +01:00
Keith Rothman 30edf041b8 Call bit2fasm.py instead of bits2fasm.py 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-01-17 11:15:28 -08:00
Keith Rothman 2ba905130a Remove old bit2fasm files. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-01-11 13:13:05 -08:00
John McMaster 1cc5b72ca5 minitest: clean up folders 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2019-01-07 23:31:44 +01:00
Karol Gugala 1839f4eac0 minitests: roi_harness: use XRAY_DATABASE env 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-02 16:42:26 +01:00
Karol Gugala 3f0e0bd828 minitests: roi_harness: add zybo Z7 settings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-01 21:26:33 +01:00
Karol Gugala fe0f1f2248 minitests: roi_harness: runme.tcl add ZYBO-Z7 support 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-01 21:23:35 +01:00
Karol Gugala 743641960a minitests: roi: runme.sh: do not hardcode artix7 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-01 21:23:06 +01:00
Felix Held 0d6e327229 introduce vivado wrapper 
This fixes the problem that when sourcing the vivado settings file the
library search path is modified resulting in non-vivado binaries not working
due to being dynamically linked against the vivado libraries instead of the
system ones.

Signed-off-by: Felix Held <felix-github@felixheld.de>
 2018-12-28 19:05:49 +01:00
John McMaster eb3ab79dfc iob: move minitest to fuzzer 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-12-10 17:30:06 -08:00
John McMaster 54dcdf1f2e tcl: reformat existing code 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-12-05 16:52:56 -08:00
John McMaster a77f7bd12e tilegrid: generate products in parallel 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-12-03 12:00:56 -08:00
John McMaster 379ed08344 iob minitest 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-11-28 20:34:02 -08:00
John McMaster 3fa5df7cb1 iob minitest: sweep misc parameters 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-11-28 19:37:55 -08:00
John McMaster 661615a40a iob minitest 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-11-28 15:30:12 -08:00
John McMaster e18329c3ab clbnoutmux: move minitest to fuzzer 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-11-12 12:10:24 -08:00
Keith Rothman 4a2a78123d Add UART port to ROI harness. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2018-11-06 08:33:35 -08:00
John McMaster f13a2a4856 fuzzers: don't use EXCLUDE_PLACEMENT on ROI 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-10-31 17:53:42 -07:00
John McMaster 5396046644 bram minitest: split into fuzzer config, data 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-10-31 10:45:50 -07:00
John McMaster f9207b5618 bram minitest: clean up tests 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-10-31 10:02:00 -07:00
John McMaster 11c485cc1f bram minitest: delete unused files, simplify name 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-10-31 09:51:00 -07:00
litghost 26b95fb46e
Merge pull request #205 from litghost/larger_roi 
Expand ROI to all of CMT X0Y2.
 2018-10-30 17:16:43 -05:00
Keith Rothman 5bd793a8d2 Fixup clean target. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2018-10-30 15:06:19 -07:00