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Added packing tests for SRL32+LUT6 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-06-28 10:53:27 +02:00
parent 98bcd3f447
commit 4d6f75e8ad
3 changed files with 188 additions and 0 deletions
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62
minitests/srl/srl32_x1_and_lut6_x3.v Normal file
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module top
(
(* clock_buffer_type = "NONE" *)
input wire CLK,
input wire CE,
input wire D,
input wire [5:0] I,
input wire [4:0] A,
output wire [3:0] Q
);
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
SRLC32E srl_a
(
.CLK (CLK),
.CE (CE),
.D (D),
.A (A),
.Q (Q[0])
);
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="B6LUT" *)
LUT6 lut_b
(
.I0 (I[0]),
.I1 (I[1]),
.I2 (I[2]),
.I3 (I[3]),
.I4 (I[4]),
.I5 (I[5]),
.O (Q[1])
);
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="C6LUT" *)
LUT6 lut_c
(
.I0 (I[0]),
.I1 (I[1]),
.I2 (I[2]),
.I3 (I[3]),
.I4 (I[4]),
.I5 (I[5]),
.O (Q[2])
);
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="D6LUT" *)
LUT6 lut_d
(
.I0 (I[0]),
.I1 (I[1]),
.I2 (I[2]),
.I3 (I[3]),
.I4 (I[4]),
.I5 (I[5]),
.O (Q[3])
);
endmodule

63
minitests/srl/srl32_x2_and_lut6_x2.v Normal file
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module top
(
(* clock_buffer_type = "NONE" *)
input wire CLK,
input wire CE,
input wire D,
input wire [5:0] I,
input wire [4:0] A,
output wire [3:0] Q
);
wire srl_b_mc31;
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
SRLC32E srl_a
(
.CLK (CLK),
.CE (CE),
.D (srl_b_mc31),
.A (A),
.Q (Q[0])
);
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="B6LUT" *)
SRLC32E srl_b
(
.CLK (CLK),
.CE (CE),
.D (D),
.A (A),
.Q (Q[1]),
.Q31 (srl_b_mc31)
);
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="C6LUT" *)
LUT6 lut_c
(
.I0 (I[0]),
.I1 (I[1]),
.I2 (I[2]),
.I3 (I[3]),
.I4 (I[4]),
.I5 (I[5]),
.O (Q[2])
);
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="D6LUT" *)
LUT6 lut_d
(
.I0 (I[0]),
.I1 (I[1]),
.I2 (I[2]),
.I3 (I[3]),
.I4 (I[4]),
.I5 (I[5]),
.O (Q[3])
);
endmodule

63
minitests/srl/srl32_x3_and_lut6_x1.v Normal file
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module top
(
(* clock_buffer_type = "NONE" *)
input wire CLK,
input wire CE,
input wire D,
input wire [5:0] I,
input wire [4:0] A,
output wire [3:0] Q
);
wire srl_b_mc31;
wire srl_c_mc31;
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
SRLC32E srl_a
(
.CLK (CLK),
.CE (CE),
.D (srl_b_mc31),
.A (A),
.Q (Q[0])
);
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="B6LUT" *)
SRLC32E srl_b
(
.CLK (CLK),
.CE (CE),
.D (srl_c_mc31),
.A (A),
.Q (Q[1]),
.Q31 (srl_b_mc31)
);
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="C6LUT" *)
SRLC32E srl_c
(
.CLK (CLK),
.CE (CE),
.D (D),
.A (A),
.Q (Q[2]),
.Q31 (srl_c_mc31)
);
(* DONT_TOUCH="yes" *)
(* LOC="SLICE_X2Y0", BEL="D6LUT" *)
LUT6 lut_d
(
.I0 (I[0]),
.I1 (I[1]),
.I2 (I[2]),
.I3 (I[3]),
.I4 (I[4]),
.I5 (I[5]),
.O (Q[3])
);
endmodule