mirror of https://github.com/openXC7/prjxray.git
Merge pull request #205 from litghost/larger_roi
Expand ROI to all of CMT X0Y2.
This commit is contained in:
litghost
GitHub
commit
26b95fb46e
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@ -2,10 +2,13 @@ export XRAY_DATABASE="artix7"
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export XRAY_PART="xc7a50tfgg484-1"
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export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
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# Leave some CLBs to the left to allow easy ROI entering
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export XRAY_ROI="SLICE_X8Y100:SLICE_X27Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59"
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export XRAY_ROI_GRID_X1="18"
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export XRAY_ROI_GRID_X2="47"
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# All CLB's in part, all BRAM's in part, all DSP's in part.
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export XRAY_ROI="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
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# ROI is all of CMT X0Y2.
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export XRAY_ROI_GRID_X1="10"
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export XRAY_ROI_GRID_X2="58"
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# Y = 0 and Y 52 are VBRK rows, include them
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export XRAY_ROI_GRID_Y1="0"
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export XRAY_ROI_GRID_Y2="52"
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@ -3,7 +3,7 @@ database: build/tilegrid.json
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pushdb:
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cp build/tilegrid.json ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/tilegrid.json
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build/tilegrid.json: build/deltas
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build/tilegrid.json: build/deltas generate.py
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cd build && python3 ../generate.py design_*.delta > tilegrid.json
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build/deltas:
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@ -145,6 +145,23 @@ def make_tiles_by_grid(tiles):
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return tiles_by_grid
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def add_segment(
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database, segments, name, tiles, segtype, verbose, baseaddr=None):
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assert name not in segments
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segment = segments.setdefault(name, {})
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segment["tiles"] = tiles
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segment["type"] = segtype
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if baseaddr:
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verbose and print('make_segment: %s baseaddr %s' % (
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name,
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baseaddr,
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))
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segment["baseaddr"] = baseaddr
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for tile_name in tiles:
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database[tile_name]["segment"] = name
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def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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'''
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Create segments data structure
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@ -163,22 +180,6 @@ def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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grid_x = tile_data["grid_x"]
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grid_y = tile_data["grid_y"]
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def add_segment(name, tiles, segtype, baseaddr=None):
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assert name not in segments
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segment = segments.setdefault(name, {})
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segment["tiles"] = tiles
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segment["type"] = segtype
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if baseaddr:
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verbose and print(
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'make_segment: %s baseaddr %s' % (
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name,
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baseaddr,
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))
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segment["baseaddr"] = baseaddr
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for tile_name in tiles:
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database[tile_name]["segment"] = name
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def process_clb():
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if tile_type in ["CLBLL_L", "CLBLM_L"]:
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int_tile_name = tiles_by_grid[(grid_x + 1, grid_y)]
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@ -186,16 +187,24 @@ def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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int_tile_name = tiles_by_grid[(grid_x - 1, grid_y)]
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add_segment(
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database=database,
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segments=segments,
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name="SEG_" + tile_name,
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tiles=[tile_name, int_tile_name],
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segtype=tile_type.lower(),
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baseaddr=tile_baseaddrs.get(tile_name, None))
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baseaddr=tile_baseaddrs.get(tile_name, None),
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verbose=verbose,
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)
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def process_hclk():
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add_segment(
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database=database,
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segments=segments,
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name="SEG_" + tile_name,
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tiles=[tile_name],
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segtype=tile_type.lower())
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segtype=tile_type.lower(),
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verbose=verbose,
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)
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def process_bram_dsp():
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for k in range(5):
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@ -222,12 +231,16 @@ def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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baseaddr = None
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add_segment(
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database=database,
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segments=segments,
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# BRAM_L_X6Y70 => SEG_BRAM4_L_X6Y70
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name="SEG_" + tile_name.replace("_", "%d_" % k, 1),
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tiles=tiles,
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# BRAM_L => bram4_l
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segtype=tile_type.lower().replace("_", "%d_" % k, 1),
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baseaddr=baseaddr)
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baseaddr=baseaddr,
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verbose=verbose,
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)
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def process_default():
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#verbose and nolr(tile_type) not in ('VBRK', 'INT', 'NULL') and print('make_segment: drop %s' % (tile_type,))
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@ -263,6 +276,39 @@ def get_bramtile(database, segment):
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return inttiles[0]
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def create_segment_for_int_lr(
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database, segments, tile, tiles_by_grid, verbose):
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""" Creates INT_[LR] segment for interconnect's without direct connectivity. """
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# Some INT_[LR] tiles have no adjacent connectivity, create a segment.
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grid_x = database[tile]["grid_x"]
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grid_y = database[tile]["grid_y"]
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if database[tile]["type"] == "INT_L":
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grid_x -= 1
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adjacent_tile = tiles_by_grid[(grid_x, grid_y)]
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elif database[tile]["type"] == "INT_R":
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grid_x += 1
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adjacent_tile = tiles_by_grid[(grid_x, grid_y)]
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else:
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assert False, database[tile]["type"]
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if (database[adjacent_tile]['type'].startswith('INT_INTERFACE_') or
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database[adjacent_tile]['type'].startswith('PCIE_INT_INTERFACE_')
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or
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database[adjacent_tile]['type'].startswith('GTP_INT_INTERFACE')):
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# This INT_[LR] tile has no adjacent connectivity,
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# create a segment.
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add_segment(
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database=database,
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segments=segments,
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name='SEG_' + tile,
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tiles=[tile],
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segtype=database[tile]["type"],
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verbose=verbose,
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)
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else:
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assert False, database[adjacent_tile]['type']
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def seg_base_addr_lr_INT(database, segments, tiles_by_grid, verbose=False):
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'''Populate segment base addresses: L/R along INT column'''
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'''
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@ -312,7 +358,11 @@ def seg_base_addr_lr_INT(database, segments, tiles_by_grid, verbose=False):
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else:
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assert 0
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assert "segment" in database[tile]
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if 'segment' not in database[tile]:
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if database[tile]['type'] in ['T_TERM_INT']:
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continue
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create_segment_for_int_lr(
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database, segments, tile, tiles_by_grid, verbose)
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seg = database[tile]["segment"]
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@ -366,6 +416,9 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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for i in range(50):
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grid_y -= 1
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if grid_y < 0:
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break
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dst_tile = database[tiles_by_grid[(grid_x, grid_y)]]
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if wordbase == 50:
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@ -373,6 +426,14 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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else:
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wordbase += 2
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if 'segment' not in dst_tile:
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if dst_tile['type'] in ['T_TERM_INT']:
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continue
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create_segment_for_int_lr(
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database, segments, tiles_by_grid[(grid_x,
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grid_y)],
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tiles_by_grid, verbose)
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#verbose and print(' dst_tile', dst_tile)
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dst_segment_name = dst_tile["segment"]
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#verbose and print('up_INT: %s => %s' % (src_segment_name, dst_segment_name))
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@ -417,6 +478,9 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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grid_y -= 1
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wordbase += 1
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if (grid_x, grid_y) not in tiles_by_grid:
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continue
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dst_tile = database[tiles_by_grid[(grid_x, grid_y)]]
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assert nolr(dst_tile['type']) == 'BRAM', dst_tile
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@ -11,7 +11,10 @@ proc make_project {} {
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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foreach roi "$::env(XRAY_ROI)" {
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puts $roi
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resize_pblock [get_pblocks roi] -add "$roi"
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}
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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@ -27,20 +30,39 @@ proc loc_luts {} {
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set lut_index 0
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# LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per CMT column)
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set lut_columns ""
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foreach lut $luts {
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set tile [get_tile -of_objects $lut]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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regexp "SLICE_X([0-9]+)Y([0-9]+)/" $lut match slice_x slice_y
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# Only even SLICEs should be used as column bases.
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if { $slice_x % 2 != 0 } {
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continue
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}
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# 50 per column => 50, 100, 150, etc
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# ex: SLICE_X2Y50/A6LUT
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# Only take one of the CLBs within a slice
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if [regexp "X.*[02468]Y.*[05]0/" $lut] {
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set cell [get_cells roi/luts[$lut_index].lut]
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set_property LOC [get_sites -of_objects $lut] $cell
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set lut_index [expr $lut_index + 1]
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lappend selected_luts $lut
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set y_column [expr ($slice_y / 50) * 50]
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dict append lut_columns "X${slice_x}Y${y_column}" "$lut "
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}
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# Pick the smallest Y in each column.
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dict for {column luts_in_column} $lut_columns {
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set min_slice_y 9999999
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foreach lut $luts_in_column {
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regexp "SLICE_X([0-9]+)Y([0-9]+)/" $lut slice_x slice_y
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if { $slice_y < $min_slice_y } {
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set selected_lut $lut
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}
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}
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puts $selected_lut
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set cell [get_cells roi/luts[$lut_index].lut]
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set_property LOC [get_sites -of_objects [get_bels $selected_lut]] $cell
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set lut_index [expr $lut_index + 1]
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lappend selected_luts [get_bels $selected_lut]
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}
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return $selected_luts
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}
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@ -53,20 +75,38 @@ proc loc_brams {} {
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set bram_index 0
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# LOC one BRAM (a "selected_lut") into each BRAM segment configuration column (ie 10 per CMT column)
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set bram_columns ""
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foreach bram $brams {
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set tile [get_tile -of_objects $bram]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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regexp "RAMB36_X([0-9]+)Y([0-9]+)/" $bram match slice_x slice_y
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# 10 per column => 10, 20, ,etc
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# ex: RAMB36_X0Y10/RAMBFIFO36E1
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if [regexp "Y.*0/" $bram] {
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set cell [get_cells roi/brams[$bram_index].bram]
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set_property LOC [get_sites -of_objects $bram] $cell
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set bram_index [expr $bram_index + 1]
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lappend selected_brams $bram
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}
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set y_column [expr ($slice_y / 10) * 10]
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dict append lut_columns "X${slice_x}Y${y_column}" "$bram "
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}
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# Pick the smallest Y in each column.
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dict for {column brams_in_column} $lut_columns {
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set min_slice_y 9999999
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foreach bram $brams_in_column {
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regexp "RAMB36_X([0-9]+)Y([0-9]+)/" $bram match slice_x slice_y
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if { $slice_y < $min_slice_y } {
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set selected_bram $bram
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}
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}
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puts ""
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puts $selected_bram
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set cell [get_cells roi/brams[$bram_index].bram]
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set_property LOC [get_sites -of_objects [get_bels $selected_bram]] $cell
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puts $selected_bram
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set bram_index [expr $bram_index + 1]
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lappend selected_brams [get_bels $selected_bram]
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}
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return $selected_brams
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}
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@ -132,7 +172,7 @@ proc run {} {
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set selected_luts [loc_luts]
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puts "Selected LUTs: [llength $selected_luts]"
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set selected_brams [loc_brams]
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puts "Selected LUTs: [llength $selected_brams]"
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puts "Selected BRAMs: [llength $selected_brams]"
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place_design
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route_design
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@ -1,16 +1,24 @@
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BUILD_DIR=build
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HARNESS_DIR ?= harness
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export BUILD_DIR
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XRAY_PINCFG ?= BASYS3-SWBUT
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export XRAY_PINCFG
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HARNESS_FILES=$(BUILD_DIR)/design.bit $(BUILD_DIR)/design.txt $(BUILD_DIR)/design.json $(BUILD_DIR)/design.dcp
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# official demo configuration
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all:
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all: $(HARNESS_FILES)
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$(HARNESS_FILES): runme.sh runme.tcl
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./runme.sh
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copy: $(HARNESS_FILES)
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mkdir -p $(HARNESS_DIR)
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cp $(HARNESS_FILES) $(HARNESS_DIR)
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
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rm -rf $(BUILD_DIR) *~
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rm -rf $(BUILD_DIR) $(HARNESS_DIR)
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.PHONY: all clean
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.PHONY: all clean copy
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@ -3,5 +3,5 @@ set -ex
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BIT_IN=$1
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BITS=$(tempfile --suffix .bits)
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${BITS} -z -y ${BIT_IN}
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${BITS} -z -y ${BIT_IN} > /dev/null
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${XRAY_BITS2FASM} ${BITS}
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@ -2,6 +2,19 @@ import json
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import csv
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import argparse
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import sys
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from prjxray.db import Database
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from prjxray.roi import Roi
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from prjxray.util import get_db_root
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def set_port_wires(ports, name, pin, wires_outside_roi):
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for port in ports:
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if name == port['name']:
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port['wires_outside_roi'] = wires_outside_roi
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assert port['pin'] == pin
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return
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assert False, name
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def main():
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@ -10,6 +23,7 @@ def main():
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"Creates design.json from output of ROI generation tcl script.")
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parser.add_argument('--design_txt', required=True)
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parser.add_argument('--design_info_txt', required=True)
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parser.add_argument('--pad_wires', required=True)
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args = parser.parse_args()
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@ -26,6 +40,36 @@ def main():
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j['info'][name] = int(value)
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db = Database(get_db_root())
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grid = db.grid()
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roi = Roi(
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db=db,
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x1=j['info']['GRID_X_MIN'],
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y1=j['info']['GRID_Y_MIN'],
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x2=j['info']['GRID_X_MAX'],
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y2=j['info']['GRID_Y_MAX'],
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)
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with open(args.pad_wires) as f:
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for l in f:
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parts = l.strip().split(' ')
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name = parts[0]
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pin = parts[1]
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wires = parts[2:]
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wires_outside_roi = []
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|
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for wire in wires:
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tile = wire.split('/')[0]
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loc = grid.loc_of_tilename(tile)
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if not roi.tile_in_roi(loc):
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wires_outside_roi.append(wire)
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set_port_wires(j['ports'], name, pin, wires_outside_roi)
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json.dump(j, sys.stdout, indent=2, sort_keys=True)
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|
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|
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|
|
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|
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@ -30,14 +30,13 @@ if [ "$SMALL" = Y ] ; then
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export DIN_N=8
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||||
export DOUT_N=8
|
||||
export XRAY_ROI=SLICE_X12Y100:SLICE_X17Y117
|
||||
# 16x by 50y CLBs (800)
|
||||
# All of CMT X0Y2
|
||||
else
|
||||
echo "Design: large"
|
||||
export PITCH=3
|
||||
export DIN_N=8
|
||||
export DOUT_N=8
|
||||
export XRAY_ROI=SLICE_X12Y100:SLICE_X27Y149
|
||||
#export XRAY_ROI=SLICE_X12Y100:SLICE_X5Y149
|
||||
export PITCH=2
|
||||
export DIN_N=16
|
||||
export DOUT_N=16
|
||||
export XRAY_ROI=SLICE_X0Y100:SLICE_X35Y149
|
||||
fi
|
||||
|
||||
mkdir -p $BUILD_DIR
|
||||
|
|
@ -60,7 +59,7 @@ ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
|
|||
${XRAY_SEGPRINT} -zd design.bits >design.segp
|
||||
${XRAY_DIR}/utils/bits2fasm.py --verbose design.bits > design.fasm
|
||||
${XRAY_DIR}/utils/fasm2frames.py design.fasm design.frm
|
||||
python3 ../create_design_json.py --design_info_txt design_info.txt --design_txt design.txt > design.json
|
||||
python3 ../create_design_json.py --design_info_txt design_info.txt --design_txt design.txt --pad_wires design_pad_wires.txt > design.json
|
||||
|
||||
# Hack to get around weird clock error related to clk net not found
|
||||
# Remove following lines:
|
||||
|
|
|
|||
|
|
@ -31,7 +31,6 @@ set XRAY_ROI_Y1 [lindex [split "$::env(XRAY_ROI)" Y] 2]
|
|||
set X_BASE $XRAY_ROI_X0
|
||||
set Y_BASE $XRAY_ROI_Y0
|
||||
|
||||
# set Y_DIN_BASE 100
|
||||
set Y_CLK_BASE $Y_BASE
|
||||
# Clock lut in middle
|
||||
set Y_DIN_BASE [expr "$Y_CLK_BASE + $PITCH"]
|
||||
|
|
@ -282,22 +281,31 @@ if {$fixed_xdc eq ""} {
|
|||
|
||||
# Place ROI inputs
|
||||
puts "Placing ROI inputs"
|
||||
set y $Y_DIN_BASE
|
||||
set y_left $Y_DIN_BASE
|
||||
# Shift y_right up to avoid PCIe block that makes routing hard.
|
||||
set y_right [expr {$Y_DIN_BASE + 24}]
|
||||
for {set i 0} {$i < $DIN_N} {incr i} {
|
||||
loc_lut_in $i $x $y
|
||||
set y [expr {$y + $PITCH}]
|
||||
if {[net_bank_left "din[$i]"]} {
|
||||
loc_lut_in $i $XRAY_ROI_X0 $y_left
|
||||
set y_left [expr {$y_left + $PITCH}]
|
||||
} else {
|
||||
loc_lut_in $i $XRAY_ROI_X1 $y_right
|
||||
set y_right [expr {$y_right + $PITCH}]
|
||||
}
|
||||
}
|
||||
|
||||
# Place ROI outputs
|
||||
set y $Y_DOUT_BASE
|
||||
set y_left $Y_DOUT_BASE
|
||||
set y_right $Y_DOUT_BASE
|
||||
puts "Placing ROI outputs"
|
||||
for {set i 0} {$i < $DOUT_N} {incr i} {
|
||||
if {[net_bank_left "dout[$i]"]} {
|
||||
loc_lut_out $i $XRAY_ROI_X0 $y
|
||||
loc_lut_out $i $XRAY_ROI_X0 $y_left
|
||||
set y_left [expr {$y_left + $PITCH}]
|
||||
} else {
|
||||
loc_lut_out $i $XRAY_ROI_X1 $y
|
||||
loc_lut_out $i $XRAY_ROI_X1 $y_right
|
||||
set y_right [expr {$y_right + $PITCH}]
|
||||
}
|
||||
set y [expr {$y + $PITCH}]
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -373,6 +381,7 @@ close $fp
|
|||
|
||||
# XXX: maybe add IOB?
|
||||
set fp [open "design.txt" w]
|
||||
set fp_wires [open "design_pad_wires.txt" w]
|
||||
puts $fp "name node pin wire"
|
||||
# Manual routing
|
||||
if {$fixed_xdc eq ""} {
|
||||
|
|
@ -391,54 +400,67 @@ if {$fixed_xdc eq ""} {
|
|||
|
||||
puts "Routing ROI inputs"
|
||||
# Arbitrary offset as observed
|
||||
set y [expr {$Y_DIN_BASE - 1}]
|
||||
set y_left $Y_DIN_BASE
|
||||
set y_right [expr {$Y_DIN_BASE + 24}]
|
||||
for {set i 0} {$i < $DIN_N} {incr i} {
|
||||
# needed to force routes away to avoid looping into ROI
|
||||
#set x_EE2BEG3 [expr {$x - 2}]
|
||||
set x_EE2BEG3 7
|
||||
set x_NE2BEG3 9
|
||||
set node "INT_R_X${x_NE2BEG3}Y${y}/NE2BEG3"
|
||||
route_via2 "din_IBUF[$i]" "INT_R_X${x_EE2BEG3}Y${y}/EE2BEG3 $node"
|
||||
if {[net_bank_left "din[$i]"]} {
|
||||
set node "INT_L_X0Y${y_left}/EE2BEG2"
|
||||
route_via2 "din_IBUF[$i]" "$node"
|
||||
set y_left [expr {$y_left + $PITCH}]
|
||||
} else {
|
||||
set node "INT_R_X25Y${y_right}/WW2BEG1"
|
||||
route_via2 "din_IBUF[$i]" "$node"
|
||||
set y_right [expr {$y_right + $PITCH}]
|
||||
}
|
||||
set net "din[$i]"
|
||||
set pin "$net2pin($net)"
|
||||
set wire [node2wire $node]
|
||||
puts $fp "$net $node $pin $wire"
|
||||
set y [expr {$y + $PITCH}]
|
||||
|
||||
set wires [get_wires -of_objects [get_nets "din_IBUF[$i]"]]
|
||||
puts $fp_wires "$net $pin $wires"
|
||||
}
|
||||
|
||||
puts "Routing ROI outputs"
|
||||
# Arbitrary offset as observed
|
||||
set y [expr {$Y_DOUT_BASE + 0}]
|
||||
set y_left [expr {$Y_DOUT_BASE + 0}]
|
||||
set y_right [expr {$Y_DOUT_BASE + 0}]
|
||||
for {set i 0} {$i < $DOUT_N} {incr i} {
|
||||
if {[net_bank_left "dout[$i]"]} {
|
||||
# XXX: find a better solution if we need harness long term
|
||||
# works on 50t but not 35t
|
||||
if {$part eq "xc7a50tfgg484-1"} {
|
||||
set node "INT_L_X10Y${y}/WW2BEG0"
|
||||
set node "INT_L_X1Y${y_left}/WW2BEG0"
|
||||
route_via2 "roi/dout[$i]" "$node"
|
||||
# works on 35t but not 50t
|
||||
} elseif {$part eq "xc7a35tcsg324-1"} {
|
||||
set node "INT_L_X10Y${y}/SW6BEG0"
|
||||
set node "INT_L_X2Y${y_left}/SW6BEG0"
|
||||
route_via2 "roi/dout[$i]" "$node"
|
||||
} elseif {$part eq "xc7a35tcpg236-1"} {
|
||||
set node "INT_L_X10Y${y}/SW6BEG0"
|
||||
set node "INT_L_X2Y${y_left}/SW6BEG0"
|
||||
route_via2 "roi/dout[$i]" "$node"
|
||||
} else {
|
||||
error "Routing: unsupported part $part"
|
||||
}
|
||||
set y_left [expr {$y_left + $PITCH}]
|
||||
# XXX: only care about right ports on Arty
|
||||
} else {
|
||||
set node "INT_R_X17Y${y}/SE6BEG0"
|
||||
set node "INT_R_X23Y${y_right}/LH12"
|
||||
route_via2 "roi/dout[$i]" "$node"
|
||||
set y_right [expr {$y_right + $PITCH}]
|
||||
}
|
||||
set net "dout[$i]"
|
||||
set pin "$net2pin($net)"
|
||||
set wire [node2wire $node]
|
||||
puts $fp "$net $node $pin $wire"
|
||||
set y [expr {$y + $PITCH}]
|
||||
|
||||
set wires [get_wires -of_objects [get_nets "roi/dout[$i]"]]
|
||||
puts $fp_wires "$net $pin $wires"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
close $fp_wires
|
||||
|
||||
puts "routing design"
|
||||
route_design
|
||||
|
|
|
|||
|
|
@ -22,6 +22,9 @@ class FasmAssembler(object):
|
|||
self.db = db
|
||||
self.grid = db.grid()
|
||||
|
||||
self.seen_tile = set()
|
||||
self.frames_in_use = set()
|
||||
|
||||
self.frames = {}
|
||||
self.frames_line = {}
|
||||
|
||||
|
|
@ -29,7 +32,12 @@ class FasmAssembler(object):
|
|||
if not sparse:
|
||||
frames = self.frames_init()
|
||||
else:
|
||||
# Even in sparse mode, zero all frames for any tile that is
|
||||
# setting a bit. This handles the case where the tile has
|
||||
# multiple frames, but the FASM only specifies some of the frames.
|
||||
frames = {}
|
||||
for frame in self.frames_in_use:
|
||||
init_frame_at_address(frames, frame)
|
||||
|
||||
for (frame_addr, word_addr, bit_index), is_set in self.frames.items():
|
||||
init_frame_at_address(frames, frame_addr)
|
||||
|
|
@ -112,6 +120,13 @@ class FasmAssembler(object):
|
|||
|
||||
segbits = self.db.get_tile_segbits(gridinfo.tile_type)
|
||||
|
||||
# Mark all frames used by this tile as in use.
|
||||
if tile not in self.seen_tile:
|
||||
for frame in segbits.frames(bits):
|
||||
self.frames_in_use.add(frame)
|
||||
|
||||
self.seen_tile.add(tile)
|
||||
|
||||
db_k = '%s.%s' % (gridinfo.tile_type, feature)
|
||||
|
||||
try:
|
||||
|
|
|
|||
|
|
@ -140,3 +140,9 @@ class TileSegbits(object):
|
|||
else:
|
||||
for bit in self.segbits[self.feature_addresses[feature][address]]:
|
||||
yield bit
|
||||
|
||||
def frames(self, bits):
|
||||
""" Iterate over frames this tile uses for a given bit location. """
|
||||
for query_bits in self.segbits.values():
|
||||
for bit in query_bits:
|
||||
yield bits.base_address + bit.word_column
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ def main():
|
|||
|
||||
for pip in tile_type.pips:
|
||||
if pip.net_from == parts[2] and pip.net_to == parts[1]:
|
||||
yield '{}/{}.{}'.format(tile, gridinfo.tile_type, pip.name)
|
||||
yield '{}/{}'.format(tile, pip.name)
|
||||
|
||||
print(
|
||||
'highlight_objects [concat {}]'.format(
|
||||
|
|
|
|||
Loading…
Reference in New Issue