mirror of https://github.com/openXC7/prjxray.git
tilegrid: generate products in parallel
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
379ed08344
commit
a77f7bd12e
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@ -1,13 +1,29 @@
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# TODO: parallelize
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FUZDIR=$(shell pwd)
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BUILD_DIR=$(FUZDIR)/build
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database: build/tilegrid.json
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pushdb:
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cp build/tilegrid.json ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/tilegrid.json
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build/tilegrid.json: build/deltas generate.py
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cd build && python3 ../generate.py design_*.delta > tilegrid.json
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build/tiles/tiles.txt:
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bash generate.sh build/tiles tiles
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build/deltas:
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bash generate.sh build
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# TODO: only generate tiles
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build/tilegrid_basic.json: build/tiles/tiles.txt build/clb/deltas build/bram/deltas generate.py
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cd build && python3 ${FUZDIR}/generate.py --tiles $(FUZDIR)/build/tiles/tiles.txt */design_*.delta --out ${BUILD_DIR}/tilegrid_basic.json
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build/clb/deltas:
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bash generate.sh build/clb clb
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build/bram/deltas:
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bash generate.sh build/bram bram
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# TODO: only generate addresses
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build/tilegrid.json: build/tilegrid_basic.json
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cd build && python3 ${FUZDIR}/generate_full.py --json-in tilegrid_basic.json --json-out ${BUILD_DIR}/tilegrid.json design_*.delta
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run:
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$(MAKE) clean
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@ -81,7 +81,9 @@ def load_baseaddrs(deltas_fns):
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for arg in deltas_fns:
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with open(arg) as f:
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line = f.read().strip()
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site = arg[7:-6]
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# clb/design_SLICE_X10Y100.delta
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# site = arg[7:-6]
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site = re.match(r".*/design_(.*).delta", arg).group(1)
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frame = int(line[5:5 + 8], 16)
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# was "0x%08x"
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site_baseaddr[site] = frame & ~0x7f
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@ -112,6 +114,7 @@ def make_tile_baseaddrs(tiles, site_baseaddr, verbose=False):
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verbose and print('')
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verbose and print('%u tiles' % len(tiles))
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verbose and print("%u baseaddrs" % len(site_baseaddr))
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added = 0
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for tile in tiles:
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for site_name in tile["sites"].keys():
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@ -131,7 +134,8 @@ def make_tile_baseaddrs(tiles, site_baseaddr, verbose=False):
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(tile["name"], site_name, bt, framebaseaddr))
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added += 1
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assert added
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assert added, "Failed to add any base addresses"
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assert added == len(site_baseaddr)
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return tile_baseaddrs
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@ -1,16 +1,20 @@
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#!/bin/bash -x
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PRJ=$2
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export FUZDIR=$PWD
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source ${XRAY_GENHEADER}
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vivado -mode batch -source ../generate.tcl
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vivado -mode batch -source $FUZDIR/generate_$PRJ.tcl
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for x in design*.bit; do
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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for x in design_*.bits; do
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diff -u design.bits $x | grep '^[-+]bit' > ${x%.bits}.delta
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done
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touch deltas
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if [ $PRJ != "tiles" ] ; then
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for x in design*.bit; do
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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for x in design_*.bits; do
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diff -u design.bits $x | grep '^[-+]bit' > ${x%.bits}.delta
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done
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touch deltas
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fi
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@ -1,209 +0,0 @@
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proc make_project {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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foreach roi "$::env(XRAY_ROI_TILEGRID)" {
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puts "ROI: $roi"
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resize_pblock [get_pblocks roi] -add "$roi"
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}
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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}
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proc loc_luts {} {
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set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */A6LUT]
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set selected_luts {}
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set lut_index 0
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# LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per CMT column)
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set lut_columns ""
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foreach lut $luts {
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regexp "SLICE_X([0-9]+)Y([0-9]+)/" $lut match slice_x slice_y
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# Only even SLICEs should be used as column bases.
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if { $slice_x % 2 != 0 } {
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continue
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}
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# 50 per column => 50, 100, 150, etc
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# ex: SLICE_X2Y50/A6LUT
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# Only take one of the CLBs within a slice
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set y_column [expr ($slice_y / 50) * 50]
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dict append lut_columns "X${slice_x}Y${y_column}" "$lut "
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}
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# Pick the smallest Y in each column.
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dict for {column luts_in_column} $lut_columns {
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set min_slice_y 9999999
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foreach lut $luts_in_column {
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regexp "SLICE_X([0-9]+)Y([0-9]+)/" $lut slice_x slice_y
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if { $slice_y < $min_slice_y } {
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set selected_lut $lut
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}
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}
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set cell [get_cells roi/luts[$lut_index].lut]
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set lut_site [get_sites -of_objects [get_bels $selected_lut]]
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puts "LOCing $selected_lut to $lut_site"
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set_property LOC $lut_site $cell
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set lut_index [expr $lut_index + 1]
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lappend selected_luts [get_bels $selected_lut]
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}
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return $selected_luts
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}
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# Return a list of sites containing BRAMs
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# sites are better than bels because site type may change and invalidate the bel
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proc loc_brams {} {
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# BRAM have multiple mutually exclusive sites
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# They can be cycled by setting the site type
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# Ex:
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# - RAMB36_X0Y10/RAMBFIFO36E1
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# - RAMB36_X0Y10/RAMB36E1
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# Default is RAMBFIFO36E1?
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# Work primarily on sites, not bels,
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# to avoid issues when switching site type during PnR
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set bram_sites [get_sites -of_objects [get_pblocks roi] -filter {SITE_TYPE =~ RAMBFIFO36E1*}]
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set bram_bels [get_bels -of_objects $bram_sites]
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set selected_bram_sites {}
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set bram_index 0
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# LOC one BRAM (a "selected_lut") into each BRAM segment configuration column (ie 10 per CMT column)
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set bram_columns ""
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foreach bram $bram_bels {
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regexp "RAMB36_X([0-9]+)Y([0-9]+)/" $bram match slice_x slice_y
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# 10 per column => 10, 20, ,etc
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# ex: RAMB36_X0Y10/RAMBFIFO36E1
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set y_column [expr ($slice_y / 10) * 10]
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dict append bram_columns "X${slice_x}Y${y_column}" "$bram "
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}
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# Pick the smallest Y in each column.
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dict for {column brams_in_column} $bram_columns {
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set min_slice_y 9999999
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foreach bram $brams_in_column {
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regexp "RAMB36_X([0-9]+)Y([0-9]+)/" $bram match slice_x slice_y
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if { $slice_y < $min_slice_y } {
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set selected_bram_bel $bram
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}
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}
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set selected_bram_bel [get_bels $selected_bram_bel]
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set bram_site [get_sites -of_objects $selected_bram_bel]
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puts "LOCing BEL: $selected_bram_bel to $bram_site"
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set cell [get_cells roi/brams[$bram_index].bram]
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set_property LOC $bram_site $cell
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if {"$bram_site" == ""} {error "Bad site $bram_site from bel $selected_bram_bel"}
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set bram_index [expr $bram_index + 1]
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# Output site, not bel, to avoid reference issues after PnR
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lappend selected_bram_sites $bram_site
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}
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return $selected_bram_sites
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}
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proc write_tiles_txt {} {
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# Get all tiles, ie not just the selected LUTs
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set tiles [get_tiles]
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# Write tiles.txt with site metadata
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set fp [open "tiles.txt" w]
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foreach tile $tiles {
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set type [get_property TYPE $tile]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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set sites [get_sites -quiet -of_objects $tile]
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set typed_sites {}
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if [llength $sites] {
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set site_types [get_property SITE_TYPE $sites]
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foreach t $site_types s $sites {
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lappend typed_sites $t $s
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}
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}
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puts $fp "$type $tile $grid_x $grid_y $typed_sites"
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}
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close $fp
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}
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proc write_clbs { selected_luts } {
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puts "write_brams: [llength $selected_luts] LUTs"
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puts ""
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# Toggle one bit in each selected LUT to generate base addresses
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for {set i 0} {$i < [llength $selected_luts]} {incr i} {
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puts ""
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set cell [get_cells roi/luts[$i].lut]
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puts "LUT $cell"
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set orig_init [get_property INIT $cell]
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# Flip a bit by changing MSB 0 => 1
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set new_init [regsub "h8" $orig_init "h0"]
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puts "INIT $orig_init => $new_init"
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set_property INIT $new_init $cell
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set site [get_sites -of_objects [lindex $selected_luts $i]]
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write_bitstream -force design_$site.bit
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set_property INIT $orig_init $cell
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}
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}
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proc write_brams { selected_brams_sites } {
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puts "write_brams: [llength $selected_brams_sites] BRAMs"
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puts ""
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# Toggle one bit in each selected BRAM to generate base addresses
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for {set i 0} {$i < [llength $selected_brams_sites]} {incr i} {
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puts ""
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set cell [get_cells roi/brams[$i].bram]
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puts "BRAM $cell"
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set orig_init [get_property INIT_00 $cell]
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# Flip a bit by changing MSB 0 => 1
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set new_init [regsub "h8" $orig_init "h0"]
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puts "INIT_00 $orig_init => $new_init"
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set_property INIT_00 $new_init $cell
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set site [lindex $selected_brams_sites $i]
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if {"$site" == ""} {error "Bad site $site"}
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write_bitstream -force design_$site.bit
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set_property INIT_00 $orig_init $cell
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}
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}
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proc run {} {
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make_project
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set selected_luts [loc_luts]
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puts "Selected LUTs: [llength $selected_luts]"
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set selected_brams_sites [loc_brams]
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puts "Selected BRAMs: [llength $selected_brams_sites]"
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_tiles_txt
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write_clbs $selected_luts
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write_brams $selected_brams_sites
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}
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run
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@ -0,0 +1,93 @@
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source "$::env(FUZDIR)/util.tcl"
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# Return a list of sites containing BRAMs
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# sites are better than bels because site type may change and invalidate the bel
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proc loc_brams {} {
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# BRAM have multiple mutually exclusive sites
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# They can be cycled by setting the site type
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# Ex:
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# - RAMB36_X0Y10/RAMBFIFO36E1
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# - RAMB36_X0Y10/RAMB36E1
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# Default is RAMBFIFO36E1?
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# Work primarily on sites, not bels,
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# to avoid issues when switching site type during PnR
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set bram_sites [get_sites -of_objects [get_pblocks roi] -filter {SITE_TYPE =~ RAMBFIFO36E1*}]
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set bram_bels [get_bels -of_objects $bram_sites]
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set selected_bram_sites {}
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set bram_index 0
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# LOC one BRAM (a "selected_lut") into each BRAM segment configuration column (ie 10 per CMT column)
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set bram_columns ""
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foreach bram $bram_bels {
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regexp "RAMB36_X([0-9]+)Y([0-9]+)/" $bram match slice_x slice_y
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# 10 per column => 10, 20, ,etc
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# ex: RAMB36_X0Y10/RAMBFIFO36E1
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set y_column [expr ($slice_y / 10) * 10]
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dict append bram_columns "X${slice_x}Y${y_column}" "$bram "
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}
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# Pick the smallest Y in each column.
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dict for {column brams_in_column} $bram_columns {
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set min_slice_y 9999999
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foreach bram $brams_in_column {
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regexp "RAMB36_X([0-9]+)Y([0-9]+)/" $bram match slice_x slice_y
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if { $slice_y < $min_slice_y } {
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set selected_bram_bel $bram
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}
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}
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set selected_bram_bel [get_bels $selected_bram_bel]
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set bram_site [get_sites -of_objects $selected_bram_bel]
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puts "LOCing BEL: $selected_bram_bel to $bram_site"
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set cell [get_cells roi/brams[$bram_index].bram]
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set_property LOC $bram_site $cell
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if {"$bram_site" == ""} {error "Bad site $bram_site from bel $selected_bram_bel"}
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set bram_index [expr $bram_index + 1]
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# Output site, not bel, to avoid reference issues after PnR
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lappend selected_bram_sites $bram_site
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}
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return $selected_bram_sites
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}
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proc write_brams { selected_brams_sites } {
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puts "write_brams: [llength $selected_brams_sites] BRAMs"
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puts ""
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# Toggle one bit in each selected BRAM to generate base addresses
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for {set i 0} {$i < [llength $selected_brams_sites]} {incr i} {
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puts ""
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set cell [get_cells roi/brams[$i].bram]
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puts "BRAM $cell"
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set orig_init [get_property INIT_00 $cell]
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# Flip a bit by changing MSB 0 => 1
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set new_init [regsub "h8" $orig_init "h0"]
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puts "INIT_00 $orig_init => $new_init"
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set_property INIT_00 $new_init $cell
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set site [lindex $selected_brams_sites $i]
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if {"$site" == ""} {error "Bad site $site"}
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write_bitstream -force design_$site.bit
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set_property INIT_00 $orig_init $cell
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}
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}
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proc run {} {
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make_project
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set selected_brams_sites [loc_brams]
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puts "Selected BRAMs: [llength $selected_brams_sites]"
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_brams $selected_brams_sites
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}
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run
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@ -0,0 +1,81 @@
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source "$::env(FUZDIR)/util.tcl"
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proc loc_luts {} {
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set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */A6LUT]
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set selected_luts {}
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set lut_index 0
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# LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per CMT column)
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set lut_columns ""
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foreach lut $luts {
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regexp "SLICE_X([0-9]+)Y([0-9]+)/" $lut match slice_x slice_y
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# Only even SLICEs should be used as column bases.
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if { $slice_x % 2 != 0 } {
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continue
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}
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# 50 per column => 50, 100, 150, etc
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# ex: SLICE_X2Y50/A6LUT
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# Only take one of the CLBs within a slice
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set y_column [expr ($slice_y / 50) * 50]
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dict append lut_columns "X${slice_x}Y${y_column}" "$lut "
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}
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# Pick the smallest Y in each column.
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dict for {column luts_in_column} $lut_columns {
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set min_slice_y 9999999
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foreach lut $luts_in_column {
|
||||
regexp "SLICE_X([0-9]+)Y([0-9]+)/" $lut slice_x slice_y
|
||||
|
||||
if { $slice_y < $min_slice_y } {
|
||||
set selected_lut $lut
|
||||
}
|
||||
}
|
||||
|
||||
set cell [get_cells roi/luts[$lut_index].lut]
|
||||
set lut_site [get_sites -of_objects [get_bels $selected_lut]]
|
||||
puts "LOCing $selected_lut to $lut_site"
|
||||
set_property LOC $lut_site $cell
|
||||
set lut_index [expr $lut_index + 1]
|
||||
lappend selected_luts [get_bels $selected_lut]
|
||||
}
|
||||
|
||||
return $selected_luts
|
||||
}
|
||||
|
||||
proc write_clbs { selected_luts } {
|
||||
puts "write_brams: [llength $selected_luts] LUTs"
|
||||
puts ""
|
||||
# Toggle one bit in each selected LUT to generate base addresses
|
||||
for {set i 0} {$i < [llength $selected_luts]} {incr i} {
|
||||
puts ""
|
||||
set cell [get_cells roi/luts[$i].lut]
|
||||
puts "LUT $cell"
|
||||
set orig_init [get_property INIT $cell]
|
||||
# Flip a bit by changing MSB 0 => 1
|
||||
set new_init [regsub "h8" $orig_init "h0"]
|
||||
puts "INIT $orig_init => $new_init"
|
||||
set_property INIT $new_init $cell
|
||||
set site [get_sites -of_objects [lindex $selected_luts $i]]
|
||||
write_bitstream -force design_$site.bit
|
||||
set_property INIT $orig_init $cell
|
||||
}
|
||||
}
|
||||
|
||||
proc run {} {
|
||||
make_project
|
||||
set selected_luts [loc_luts]
|
||||
puts "Selected LUTs: [llength $selected_luts]"
|
||||
|
||||
place_design
|
||||
route_design
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
write_clbs $selected_luts
|
||||
}
|
||||
|
||||
run
|
||||
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
#!/usr/bin/env python3
|
||||
import os, sys, json, re
|
||||
|
||||
|
||||
def run(json_in_fn, json_out_fn, deltas_fns, verbose=False):
|
||||
database = json.load(open(json_in_fn, "r"))
|
||||
|
||||
# TODO: move address processing here
|
||||
|
||||
# Save
|
||||
json.dump(
|
||||
database,
|
||||
open(json_out_fn, "w"),
|
||||
sort_keys=True,
|
||||
indent=4,
|
||||
separators=(",", ": "))
|
||||
|
||||
|
||||
def main():
|
||||
import argparse
|
||||
import glob
|
||||
|
||||
parser = argparse.ArgumentParser(
|
||||
description="Generate tilegrid.json from bitstream deltas")
|
||||
|
||||
parser.add_argument("--verbose", action="store_true", help="")
|
||||
parser.add_argument(
|
||||
"--json-in",
|
||||
default="tiles_basic.json",
|
||||
help="Input .json without addresses")
|
||||
parser.add_argument(
|
||||
"--json-out", default="tilegrid.json", help="Output JSON")
|
||||
parser.add_argument(
|
||||
"deltas", nargs="*", help=".bit diffs to create base addresses from")
|
||||
args = parser.parse_args()
|
||||
|
||||
deltas = args.deltas
|
||||
if not args.deltas:
|
||||
deltas = glob.glob("*.delta")
|
||||
|
||||
run(args.json_in, args.json_out, deltas, verbose=args.verbose)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
source "$::env(FUZDIR)/util.tcl"
|
||||
|
||||
proc write_tiles_txt {} {
|
||||
# Get all tiles, ie not just the selected LUTs
|
||||
set tiles [get_tiles]
|
||||
|
||||
# Write tiles.txt with site metadata
|
||||
set fp [open "tiles.txt" w]
|
||||
foreach tile $tiles {
|
||||
set type [get_property TYPE $tile]
|
||||
set grid_x [get_property GRID_POINT_X $tile]
|
||||
set grid_y [get_property GRID_POINT_Y $tile]
|
||||
set sites [get_sites -quiet -of_objects $tile]
|
||||
set typed_sites {}
|
||||
|
||||
if [llength $sites] {
|
||||
set site_types [get_property SITE_TYPE $sites]
|
||||
foreach t $site_types s $sites {
|
||||
lappend typed_sites $t $s
|
||||
}
|
||||
}
|
||||
|
||||
puts $fp "$type $tile $grid_x $grid_y $typed_sites"
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
proc run {} {
|
||||
make_project
|
||||
|
||||
place_design
|
||||
route_design
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
write_tiles_txt
|
||||
}
|
||||
|
||||
run
|
||||
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
proc make_project {} {
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
|
||||
read_verilog "$::env(FUZDIR)/top.v"
|
||||
synth_design -top top
|
||||
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
|
||||
|
||||
create_pblock roi
|
||||
add_cells_to_pblock [get_pblocks roi] [get_cells roi]
|
||||
foreach roi "$::env(XRAY_ROI_TILEGRID)" {
|
||||
puts "ROI: $roi"
|
||||
resize_pblock [get_pblocks roi] -add "$roi"
|
||||
}
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
set_param tcl.collectionResultDisplayLimit 0
|
||||
|
||||
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -12,9 +12,11 @@ clean:
|
|||
build/env:
|
||||
test "$(XRAY_PART)" = "xc7a50tfgg484-1"
|
||||
|
||||
# Didn't work
|
||||
build/roi_io.diff:
|
||||
$(MAKE) -f diff.mk OUT_DIFF=build/roi_io.diff PRJL=roi_io_a PRJR=roi_io_b
|
||||
|
||||
# Didn't work
|
||||
build/roi_prop.diff:
|
||||
$(MAKE) -f diff.mk OUT_DIFF=build/roi_prop.diff PRJL=roi_prop_a PRJR=roi_prop_b
|
||||
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
|
|||
|
||||
place_design
|
||||
route_design
|
||||
write_checkpoint -force design.dcp
|
||||
|
||||
# set port [create_port -direction OUT myport]
|
||||
# set_property -dict "PACKAGE_PIN D19 IOSTANDARD LVCMOS33" $port
|
||||
|
|
|
|||
|
|
@ -8,12 +8,13 @@ fi
|
|||
set -ex
|
||||
|
||||
# for some reason on sourced script set -e doesn't work
|
||||
test $# = 1 || exit 1
|
||||
# Scripts may have additional arguments, but first is reserved for build directory
|
||||
test $# -ge 1 || exit 1
|
||||
test ! -e "$SPECN"
|
||||
SPECN=$1
|
||||
|
||||
rm -rf "$SPECN"
|
||||
mkdir "$SPECN"
|
||||
mkdir -p "$SPECN"
|
||||
cd "$SPECN"
|
||||
|
||||
export SEED="$(echo $SPECN | md5sum | cut -c1-8)"
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
set -ex
|
||||
|
||||
FUZDIR=$PWD
|
||||
export FUZDIR=$PWD
|
||||
source ${XRAY_GENHEADER}
|
||||
|
||||
# Some projects have hard coded top.v, others are generated
|
||||
|
|
|
|||
Loading…
Reference in New Issue