Fixed the LiteX generated SoC to be Linux capable

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-17 13:45:11 +02:00 · 2019-06-17 13:45:11 +02:00 · 3783e7b2e3
parent 4798c08ad8
commit 3783e7b2e3
10 changed files with 18394 additions and 13899 deletions
--- a/minitests/litex/README.md
+++ b/minitests/litex/README.md
@ -0,0 +1,11 @@
+# LiteX minitest
+
+This folder contains a minitest for a Linux capable LiteX SoC for Arty board.
+
+There are two variants: for Vivado only flow and for Yosys+Vivado flow. In order to run one of them enter the specific directory and run `make`.
+
+The SoC "gateware" files were generated using the command:
+
+```
+./arty.py --cpu-type vexriscv --cpu-variant linux --with-ethernet --no-compile-software --no-compile-gateware
+```
--- a/minitests/litex/src.vivado/VexRiscv.v
+++ b/minitests/litex/src.vivado/VexRiscv.v
--- a/minitests/litex/src.vivado/VexRiscv_Linux.v
+++ b/minitests/litex/src.vivado/VexRiscv_Linux.v
--- a/minitests/litex/src.vivado/top.tcl
+++ b/minitests/litex/src.vivado/top.tcl
@ -1,7 +1,7 @@
 create_project -force -name top -part xc7a35ticsg324-1L
 add_files {../top.v}
-add_files {../VexRiscv.v}
-read_xdc {../top.xdc}
+add_files {../VexRiscv_Linux.v}
+read_xdc ../top.xdc
 synth_design -top top -part xc7a35ticsg324-1L
 report_timing_summary -file top_timing_synth.rpt
 report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
@ -22,6 +22,6 @@ report_drc -file top_drc.rpt
 report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
 report_power -file top_power.rpt
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-write_bitstream -force top.bit
+write_bitstream -force top.bit 
 write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
 quit
--- a/minitests/litex/src.vivado/top.v
+++ b/minitests/litex/src.vivado/top.v
--- a/minitests/litex/src.yosys/VexRiscv.v
+++ b/minitests/litex/src.yosys/VexRiscv.v
--- a/minitests/litex/src.yosys/VexRiscv_Linux.v
+++ b/minitests/litex/src.yosys/VexRiscv_Linux.v
--- a/minitests/litex/src.yosys/synth.ys
+++ b/minitests/litex/src.yosys/synth.ys
@ -1,3 +1,3 @@
 read_verilog top.v
-read_verilog VexRiscv.v
+read_verilog VexRiscv_Linux.v
 synth_xilinx -edif top.edif
--- a/minitests/litex/src.yosys/top.tcl
+++ b/minitests/litex/src.yosys/top.tcl
@ -21,6 +21,6 @@ report_drc -file top_drc.rpt
 report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
 report_power -file top_power.rpt
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-write_bitstream -force top.bit
+write_bitstream -force top.bit 
 write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
 quit
--- a/minitests/litex/src.yosys/top.v
+++ b/minitests/litex/src.yosys/top.v