mirror of https://github.com/openXC7/prjxray.git
tcl: reformat existing code
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
c7aacd521b
commit
54dcdf1f2e
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@ -9,7 +9,7 @@ set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_po
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
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[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
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[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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@ -27,17 +27,16 @@ route_design
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write_checkpoint -force design.dcp
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proc write_txtdata {filename} {
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puts "Writing $filename."
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set fp [open $filename w]
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foreach tile [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] {
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puts "Dumping pips from tile $tile"
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foreach pip [get_pips -of_objects $tile] {
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if {[get_nets -quiet -of_objects $pip] == {}} {puts $fp "$pip 0"} {puts $fp "$pip 1"}
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}
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}
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close $fp
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puts "Writing $filename."
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set fp [open $filename w]
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foreach tile [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] {
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puts "Dumping pips from tile $tile"
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foreach pip [get_pips -of_objects $tile] {
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if {[get_nets -quiet -of_objects $pip] == {}} {puts $fp "$pip 0"} {puts $fp "$pip 1"}
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}
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}
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close $fp
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}
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write_bitstream -force design.bit
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write_txtdata design.txt
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@ -1,76 +1,76 @@
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proc puts_list {l} {
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foreach e $l {puts $e}
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foreach e $l {puts $e}
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}
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proc get_carry_cyinit_mux_cfg {carry_cell} {
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set cyinit_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == CYINIT}]
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set cyinit_net [get_nets -quiet -of_objects $cyinit_pin]
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set cyinit_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == CYINIT}]
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set cyinit_net [get_nets -quiet -of_objects $cyinit_pin]
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if {[string last "<const0>" $cyinit_net] > 0} { return "zro" }
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if {[string last "<const1>" $cyinit_net] > 0} { return "one" }
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if {[string last "<const0>" $cyinit_net] > 0} { return "zro" }
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if {[string last "<const1>" $cyinit_net] > 0} { return "one" }
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set ax_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */AX]
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set ax_net [get_nets -quiet -of_objects $ax_pin]
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if {"$cyinit_net" == "$ax_net"} { return "ax " }
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set ax_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */AX]
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set ax_net [get_nets -quiet -of_objects $ax_pin]
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if {"$cyinit_net" == "$ax_net"} { return "ax " }
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set cin_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */CIN]
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set cin_net [get_nets -quiet -of_objects $cin_pin]
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if {"$cyinit_net" == "$cin_net"} { return "cin" }
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set cin_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */CIN]
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set cin_net [get_nets -quiet -of_objects $cin_pin]
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if {"$cyinit_net" == "$cin_net"} { return "cin" }
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return "???"
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return "???"
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}
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proc get_carry_di0_mux_cfg {carry_cell} {
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set di0_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[0]}]
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set di0_net [get_nets -quiet -of_objects $di0_pin]
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set di0_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[0]}]
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set di0_net [get_nets -quiet -of_objects $di0_pin]
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set ax_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */AX]
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set ax_net [get_nets -quiet -of_objects $ax_pin]
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if {"$di0_net" == "$ax_net"} { return "ax " }
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set ax_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */AX]
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set ax_net [get_nets -quiet -of_objects $ax_pin]
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if {"$di0_net" == "$ax_net"} { return "ax " }
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return "o5 "
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return "o5 "
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}
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proc get_carry_di1_mux_cfg {carry_cell} {
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set di1_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[1]}]
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set di1_net [get_nets -quiet -of_objects $di1_pin]
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set di1_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[1]}]
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set di1_net [get_nets -quiet -of_objects $di1_pin]
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set bx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */BX]
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set bx_net [get_nets -quiet -of_objects $bx_pin]
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if {"$di1_net" == "$bx_net"} { return "bx " }
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set bx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */BX]
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set bx_net [get_nets -quiet -of_objects $bx_pin]
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if {"$di1_net" == "$bx_net"} { return "bx " }
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return "o5 "
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return "o5 "
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}
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proc get_carry_di2_mux_cfg {carry_cell} {
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set di2_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[2]}]
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set di2_net [get_nets -quiet -of_objects $di2_pin]
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set di2_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[2]}]
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set di2_net [get_nets -quiet -of_objects $di2_pin]
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set cx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */CX]
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set cx_net [get_nets -quiet -of_objects $cx_pin]
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if {"$di2_net" == "$cx_net"} { return "cx " }
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set cx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */CX]
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set cx_net [get_nets -quiet -of_objects $cx_pin]
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if {"$di2_net" == "$cx_net"} { return "cx " }
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return "o5 "
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return "o5 "
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}
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proc get_carry_di3_mux_cfg {carry_cell} {
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set di3_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[3]}]
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set di3_net [get_nets -quiet -of_objects $di3_pin]
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set di3_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[3]}]
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set di3_net [get_nets -quiet -of_objects $di3_pin]
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set dx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */DX]
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set dx_net [get_nets -quiet -of_objects $dx_pin]
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if {"$di3_net" == "$dx_net"} { return "dx " }
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set dx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */DX]
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set dx_net [get_nets -quiet -of_objects $dx_pin]
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if {"$di3_net" == "$dx_net"} { return "dx " }
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return "o5 "
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return "o5 "
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}
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proc list_carry_cfg {} {
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foreach carry_cell [get_cells -hierarchical -filter {REF_NAME == CARRY4}] {
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set cyinit_mux_cfg [get_carry_cyinit_mux_cfg $carry_cell]
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set di0_mux_cfg [get_carry_di0_mux_cfg $carry_cell]
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set di1_mux_cfg [get_carry_di1_mux_cfg $carry_cell]
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set di2_mux_cfg [get_carry_di2_mux_cfg $carry_cell]
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set di3_mux_cfg [get_carry_di3_mux_cfg $carry_cell]
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puts "[get_bels -of_objects $carry_cell] $cyinit_mux_cfg $di0_mux_cfg $di1_mux_cfg $di2_mux_cfg $di3_mux_cfg"
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}
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foreach carry_cell [get_cells -hierarchical -filter {REF_NAME == CARRY4}] {
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set cyinit_mux_cfg [get_carry_cyinit_mux_cfg $carry_cell]
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set di0_mux_cfg [get_carry_di0_mux_cfg $carry_cell]
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set di1_mux_cfg [get_carry_di1_mux_cfg $carry_cell]
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set di2_mux_cfg [get_carry_di2_mux_cfg $carry_cell]
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set di3_mux_cfg [get_carry_di3_mux_cfg $carry_cell]
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puts "[get_bels -of_objects $carry_cell] $cyinit_mux_cfg $di0_mux_cfg $di1_mux_cfg $di2_mux_cfg $di3_mux_cfg"
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}
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}
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@ -23,7 +23,7 @@ source ../../../utils/utils.tcl
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set fp [open "../todo.txt" r]
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set todo_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend todo_lines [split $line .]
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lappend todo_lines [split $line .]
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}
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close $fp
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@ -31,57 +31,56 @@ set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi
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set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
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for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
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set line [lindex $todo_lines $idx]
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puts "== $idx: $line"
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set line [lindex $todo_lines $idx]
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puts "== $idx: $line"
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set tile_type [lindex $line 0]
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set dst_wire [lindex $line 1]
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set src_wire [lindex $line 2]
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set tile_type [lindex $line 0]
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set dst_wire [lindex $line 1]
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set src_wire [lindex $line 2]
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if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
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if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
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if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
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if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
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set recv_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
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-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
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set recv_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
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-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
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set mynet [create_net mynet_$idx]
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set mylut [create_cell -reference LUT1 mylut_$idx]
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set_property -dict "LOC $recv_site BEL A6LUT" $mylut
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set mynet [create_net mynet_$idx]
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set mylut [create_cell -reference LUT1 mylut_$idx]
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set_property -dict "LOC $recv_site BEL A6LUT" $mylut
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if {$src_wire == "VCC_WIRE"} {
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set mytie [create_cell -reference VCC mytie_$idx]
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connect_net -net $mynet -objects "$mytie/P $mylut/I0"
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}
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if {$src_wire == "VCC_WIRE"} {
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set mytie [create_cell -reference VCC mytie_$idx]
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connect_net -net $mynet -objects "$mytie/P $mylut/I0"
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}
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if {$src_wire == "GND_WIRE"} {
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set mytie [create_cell -reference GND mytie_$idx]
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connect_net -net $mynet -objects "$mytie/G $mylut/I0"
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}
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if {$src_wire == "GND_WIRE"} {
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set mytie [create_cell -reference GND mytie_$idx]
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connect_net -net $mynet -objects "$mytie/G $mylut/I0"
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}
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route_via $mynet "$tile/$src_wire $tile/$dst_wire"
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route_via $mynet "$tile/$src_wire $tile/$dst_wire"
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}
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proc write_txtdata {filename} {
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puts "Writing $filename."
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set fp [open $filename w]
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set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
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if {$all_pips != {}} {
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puts "Dumping pips."
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foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
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foreach pip [filter $all_pips "TILE == $tile"] {
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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}
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}
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}
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close $fp
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puts "Writing $filename."
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set fp [open $filename w]
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set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
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if {$all_pips != {}} {
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puts "Dumping pips."
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foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
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foreach pip [filter $all_pips "TILE == $tile"] {
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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}
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}
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}
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close $fp
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}
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_txtdata design.txt
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@ -21,19 +21,18 @@ write_checkpoint -force piplist.dcp
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source ../../utils/utils.tcl
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proc print_tile_pips {tile_type filename} {
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set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
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puts "Dumping and PIPs for tile $tile ($tile_type) to $filename."
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set fp [open $filename w]
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foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
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set src [get_wires -uphill -of_objects $pip]
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set dst [get_wires -downhill -of_objects $pip]
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if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
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puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
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}
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}
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close $fp
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set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
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puts "Dumping and PIPs for tile $tile ($tile_type) to $filename."
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set fp [open $filename w]
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foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
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set src [get_wires -uphill -of_objects $pip]
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set dst [get_wires -downhill -of_objects $pip]
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if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
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puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
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}
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}
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close $fp
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}
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print_tile_pips INT_L pips_int_l.txt
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print_tile_pips INT_R pips_int_r.txt
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@ -23,22 +23,22 @@ write_checkpoint -force design.dcp
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source ../../../utils/utils.tcl
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proc write_txtdata {filename} {
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puts "Writing $filename."
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set fp [open $filename w]
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set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
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if {$all_pips != {}} {
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puts "Dumping pips."
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foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
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foreach pip [filter $all_pips "TILE == $tile"] {
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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}
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}
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}
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close $fp
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puts "Writing $filename."
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set fp [open $filename w]
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set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
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if {$all_pips != {}} {
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puts "Dumping pips."
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foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
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foreach pip [filter $all_pips "TILE == $tile"] {
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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}
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}
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}
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close $fp
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}
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set int_l_tiles [filter [pblock_tiles roi] {TYPE == INT_L}]
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@ -47,37 +47,36 @@ set int_r_tiles [filter [pblock_tiles roi] {TYPE == INT_R}]
|
|||
set fp [open "../todo.txt" r]
|
||||
set todo_lines {}
|
||||
for {gets $fp line} {$line != ""} {gets $fp line} {
|
||||
lappend todo_lines $line
|
||||
lappend todo_lines $line
|
||||
}
|
||||
close $fp
|
||||
|
||||
for {set i 100} {$i < 200} {incr i} {
|
||||
set route_nodes {}
|
||||
foreach line [randsample_list 5 $todo_lines] {
|
||||
set line [split $line .]
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
set route_nodes {}
|
||||
foreach line [randsample_list 5 $todo_lines] {
|
||||
set line [split $line .]
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
|
||||
set tile ""
|
||||
if {$tile_type == "INT_L"} {
|
||||
set j [expr {int(rand()*[llength $int_l_tiles])}]
|
||||
set tile [lindex $int_l_tiles $j]
|
||||
}
|
||||
if {$tile_type == "INT_R"} {
|
||||
set j [expr {int(rand()*[llength $int_r_tiles])}]
|
||||
set tile [lindex $int_r_tiles $j]
|
||||
}
|
||||
set tile ""
|
||||
if {$tile_type == "INT_L"} {
|
||||
set j [expr {int(rand()*[llength $int_l_tiles])}]
|
||||
set tile [lindex $int_l_tiles $j]
|
||||
}
|
||||
if {$tile_type == "INT_R"} {
|
||||
set j [expr {int(rand()*[llength $int_r_tiles])}]
|
||||
set tile [lindex $int_r_tiles $j]
|
||||
}
|
||||
|
||||
lappend route_nodes $tile/$src_wire
|
||||
lappend route_nodes $tile/$dst_wire
|
||||
}
|
||||
lappend route_nodes $tile/$src_wire
|
||||
lappend route_nodes $tile/$dst_wire
|
||||
}
|
||||
|
||||
set_property FIXED_ROUTE {} [get_nets o_OBUF]
|
||||
route_design -unroute -net [get_nets o_OBUF]
|
||||
route_via o_OBUF $route_nodes
|
||||
set_property FIXED_ROUTE {} [get_nets o_OBUF]
|
||||
route_design -unroute -net [get_nets o_OBUF]
|
||||
route_via o_OBUF $route_nodes
|
||||
|
||||
write_bitstream -quiet -force design_$i.bit
|
||||
write_txtdata design_$i.txt
|
||||
write_bitstream -quiet -force design_$i.bit
|
||||
write_txtdata design_$i.txt
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -21,19 +21,18 @@ write_checkpoint -force piplist.dcp
|
|||
source ../../utils/utils.tcl
|
||||
|
||||
proc print_tile_pips {tile_type filename} {
|
||||
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
|
||||
puts "Dumping and PIPs for tile $tile ($tile_type) to $filename."
|
||||
set fp [open $filename w]
|
||||
foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set dst [get_wires -downhill -of_objects $pip]
|
||||
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
|
||||
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
|
||||
puts "Dumping and PIPs for tile $tile ($tile_type) to $filename."
|
||||
set fp [open $filename w]
|
||||
foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set dst [get_wires -downhill -of_objects $pip]
|
||||
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
|
||||
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
print_tile_pips INT_L pips_int_l.txt
|
||||
print_tile_pips INT_R pips_int_r.txt
|
||||
|
||||
|
|
|
|||
|
|
@ -53,4 +53,3 @@ proc run {} {
|
|||
}
|
||||
|
||||
run
|
||||
|
||||
|
|
|
|||
|
|
@ -59,4 +59,3 @@ proc run {} {
|
|||
}
|
||||
|
||||
run
|
||||
|
||||
|
|
|
|||
|
|
@ -40,4 +40,3 @@ proc run {} {
|
|||
}
|
||||
|
||||
run
|
||||
|
||||
|
|
|
|||
|
|
@ -38,4 +38,3 @@ proc run {} {
|
|||
}
|
||||
|
||||
run
|
||||
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ proc make_io_pad_sites {} {
|
|||
foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
|
||||
set site [get_sites -of_objects $pad]
|
||||
if {[llength $site] == 0} {
|
||||
continue
|
||||
continue
|
||||
}
|
||||
if [string match IOB33* [get_property SITE_TYPE $site]] {
|
||||
dict append io_pad_sites $site $pad
|
||||
|
|
@ -130,9 +130,9 @@ proc assign_iobs {} {
|
|||
set fixed_pins 3
|
||||
set iports [get_ports di*]
|
||||
for {set i 0} {$i < [llength $iports]} {incr i} {
|
||||
set pad [lindex $iopad [expr $i+$fixed_pins]]
|
||||
set port [lindex $iports $i]
|
||||
set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port
|
||||
set pad [lindex $iopad [expr $i+$fixed_pins]]
|
||||
set port [lindex $iports $i]
|
||||
set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -167,4 +167,3 @@ proc make_project_roi { roi_var } {
|
|||
|
||||
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -27,4 +27,3 @@ set TIME_taken [expr [clock clicks -milliseconds] - $TIME_start]
|
|||
puts "Took ms: $TIME_taken"
|
||||
puts "Result: $opins_zero / $nnets zero"
|
||||
puts "Result: $opins_multi / $nnets multi"
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ proc build_design {} {
|
|||
|
||||
puts "Locking pins"
|
||||
set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
|
||||
puts "Package stuff"
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
|
|
@ -93,4 +93,3 @@ proc wires_all {} {
|
|||
build_design
|
||||
pips_all
|
||||
wires_all
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ proc build_design {} {
|
|||
|
||||
puts "Locking pins"
|
||||
set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
|
||||
puts "Package stuff"
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
|
|
@ -43,4 +43,3 @@ proc build_design {} {
|
|||
|
||||
build_design
|
||||
write_info4
|
||||
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ proc build_design {} {
|
|||
|
||||
puts "Locking pins"
|
||||
set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
|
||||
puts "Package stuff"
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
|
|
@ -44,4 +44,3 @@ proc build_design {} {
|
|||
|
||||
build_design
|
||||
write_info4
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ proc build_design {} {
|
|||
|
||||
puts "Locking pins"
|
||||
set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
|
||||
puts "Package stuff"
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
|
|
@ -43,4 +43,3 @@ proc build_design {} {
|
|||
|
||||
build_design
|
||||
write_info4
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ proc build_design {} {
|
|||
|
||||
puts "Locking pins"
|
||||
set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
|
||||
puts "Package stuff"
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
|
|
@ -43,4 +43,3 @@ proc build_design {} {
|
|||
|
||||
build_design
|
||||
write_info4
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ proc build_design {} {
|
|||
|
||||
puts "Locking pins"
|
||||
set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
|
||||
puts "Package stuff"
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
|
|
@ -43,4 +43,3 @@ proc build_design {} {
|
|||
|
||||
build_design
|
||||
write_info4
|
||||
|
||||
|
|
|
|||
|
|
@ -163,12 +163,12 @@ proc write_info4 {} {
|
|||
# Just output
|
||||
incr lines_no_int
|
||||
line_net_internal $fp $net $src_site $src_site_type $src_bel $src_bel_pin $dst_bel $dst_bel_pin $ico $fast_max $fast_min $slow_max $slow_min
|
||||
# At least some fabric exists
|
||||
# Does dest BEL exist but not source BEL?
|
||||
# At least some fabric exists
|
||||
# Does dest BEL exist but not source BEL?
|
||||
} elseif {$src_bel eq ""} {
|
||||
puts "ERROR: should have been filtered"
|
||||
return
|
||||
# Ideally query from and to cell pins
|
||||
# Ideally query from and to cell pins
|
||||
} else {
|
||||
# Nested list delimination precedence: ",|:"
|
||||
|
||||
|
|
@ -219,4 +219,3 @@ proc write_info4 {} {
|
|||
# for debugging
|
||||
# source ../project.tcl
|
||||
# write_info4
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ proc build_design_full {} {
|
|||
synth_design -top top
|
||||
|
||||
#set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
|
||||
# [get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
# [get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
|
||||
|
|
@ -170,4 +170,3 @@ proc nodes_unique_cc {} {
|
|||
build_design_full
|
||||
speed_models2
|
||||
nodes_unique_cc
|
||||
|
||||
|
|
|
|||
|
|
@ -40,23 +40,23 @@ proc build_project {} {
|
|||
# Also, if GRID_MIN/MAX is not defined, automatically create it based on used CLBs
|
||||
# See caveat in README on automatic creation
|
||||
foreach lut $luts {
|
||||
set tile [get_tile -of_objects $lut]
|
||||
set grid_x [get_property GRID_POINT_X $tile]
|
||||
set grid_y [get_property GRID_POINT_Y $tile]
|
||||
set tile [get_tile -of_objects $lut]
|
||||
set grid_x [get_property GRID_POINT_X $tile]
|
||||
set grid_y [get_property GRID_POINT_Y $tile]
|
||||
|
||||
if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x}
|
||||
if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x}
|
||||
if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x}
|
||||
if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x}
|
||||
|
||||
if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y}
|
||||
if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y}
|
||||
if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y}
|
||||
if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y}
|
||||
|
||||
# 50 per column => 50, 100, 150, etc
|
||||
if [regexp "Y(0|[0-9]*[05]0)/" $lut] {
|
||||
set cell [get_cells roi/is[$lut_index].lut]
|
||||
set_property LOC [get_sites -of_objects $lut] $cell
|
||||
set lut_index [expr $lut_index + 1]
|
||||
lappend selected_luts $lut
|
||||
}
|
||||
# 50 per column => 50, 100, 150, etc
|
||||
if [regexp "Y(0|[0-9]*[05]0)/" $lut] {
|
||||
set cell [get_cells roi/is[$lut_index].lut]
|
||||
set_property LOC [get_sites -of_objects $lut] $cell
|
||||
set lut_index [expr $lut_index + 1]
|
||||
lappend selected_luts $lut
|
||||
}
|
||||
}
|
||||
|
||||
place_design
|
||||
|
|
@ -85,35 +85,34 @@ proc write_data {} {
|
|||
# Write tiles.txt with site metadata
|
||||
set fp [open "timgrid.txt" w]
|
||||
foreach tile $tiles {
|
||||
set type [get_property TYPE $tile]
|
||||
set grid_x [get_property GRID_POINT_X $tile]
|
||||
set grid_y [get_property GRID_POINT_Y $tile]
|
||||
set type [get_property TYPE $tile]
|
||||
set grid_x [get_property GRID_POINT_X $tile]
|
||||
set grid_y [get_property GRID_POINT_Y $tile]
|
||||
|
||||
set items {}
|
||||
set items {}
|
||||
|
||||
set wires [get_wires -of_objects $tile]
|
||||
if [llength $wires] {
|
||||
if [llength $wires] {
|
||||
foreach wire $wires {
|
||||
set name [get_property NAME $wire]
|
||||
set speed_index [get_property SPEED_INDEX $wire]
|
||||
lappend items wire $name $speed_index
|
||||
}
|
||||
}
|
||||
lappend items wire $name $speed_index
|
||||
}
|
||||
}
|
||||
|
||||
set pips [get_pips -of_objects $tile]
|
||||
if [llength $pips] {
|
||||
if [llength $pips] {
|
||||
foreach pip $pips {
|
||||
set name [get_property NAME $pip]
|
||||
set speed_index [get_property SPEED_INDEX $pip]
|
||||
lappend items pip $name $speed_index
|
||||
}
|
||||
}
|
||||
lappend items pip $name $speed_index
|
||||
}
|
||||
}
|
||||
|
||||
puts $fp "$type $tile $grid_x $grid_y $items"
|
||||
puts $fp "$type $tile $grid_x $grid_y $items"
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
build_project
|
||||
write_data
|
||||
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_po
|
|||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
|
||||
|
||||
set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
|
||||
create_pblock roi
|
||||
add_cells_to_pblock [get_pblocks roi] [get_cells roi]
|
||||
|
|
@ -32,15 +32,15 @@ write_checkpoint -force design.dcp
|
|||
# Unmodified design with random LUTs
|
||||
|
||||
proc write_txtdata {filename} {
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] {
|
||||
set bel [get_property BEL $cell]
|
||||
set loc [get_property LOC $cell]
|
||||
set init [get_property INIT $cell]
|
||||
puts $fp "$loc $bel $init"
|
||||
}
|
||||
close $fp
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] {
|
||||
set bel [get_property BEL $cell]
|
||||
set loc [get_property LOC $cell]
|
||||
set init [get_property INIT $cell]
|
||||
puts $fp "$loc $bel $init"
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
write_bitstream -force design_0.bit
|
||||
|
|
@ -51,24 +51,24 @@ write_txtdata design_0.txt
|
|||
# XOR LUT INITs
|
||||
|
||||
set pattern_list {
|
||||
0x1234567812345678
|
||||
0xFFFFFFFF00000000
|
||||
0xFFFF0000FFFF0000
|
||||
0xFF00FF00FF00FF00
|
||||
0xF0F0F0F0F0F0F0F0
|
||||
0xCCCCCCCCCCCCCCCC
|
||||
0xAAAAAAAAAAAAAAAA
|
||||
0x1234567812345678
|
||||
0xFFFFFFFF00000000
|
||||
0xFFFF0000FFFF0000
|
||||
0xFF00FF00FF00FF00
|
||||
0xF0F0F0F0F0F0F0F0
|
||||
0xCCCCCCCCCCCCCCCC
|
||||
0xAAAAAAAAAAAAAAAA
|
||||
}
|
||||
|
||||
set pattern_index 0
|
||||
|
||||
foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] {
|
||||
set v [get_property init $cell]
|
||||
set v [scan [string range $v 4 100] %x]
|
||||
set v [expr $v ^ [lindex $pattern_list $pattern_index]]
|
||||
set v [format %x $v]
|
||||
set_property init 64'h$v $cell
|
||||
set pattern_index [expr ($pattern_index + 1) % 7]
|
||||
set v [get_property init $cell]
|
||||
set v [scan [string range $v 4 100] %x]
|
||||
set v [expr $v ^ [lindex $pattern_list $pattern_index]]
|
||||
set v [format %x $v]
|
||||
set_property init 64'h$v $cell
|
||||
set pattern_index [expr ($pattern_index + 1) % 7]
|
||||
}
|
||||
|
||||
write_bitstream -force design_1.bit
|
||||
|
|
@ -81,10 +81,9 @@ write_txtdata design_1.txt
|
|||
set pattern_index 1
|
||||
|
||||
foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] {
|
||||
set_property init 64'h[lindex $pattern_list $pattern_index] $cell
|
||||
set pattern_index [expr ($pattern_index + 1) % 7]
|
||||
set_property init 64'h[lindex $pattern_list $pattern_index] $cell
|
||||
set pattern_index [expr ($pattern_index + 1) % 7]
|
||||
}
|
||||
|
||||
write_bitstream -force design_2.bit
|
||||
write_txtdata design_2.txt
|
||||
|
||||
|
|
|
|||
|
|
@ -44,9 +44,9 @@ foreach ff $ffs {
|
|||
set usedstr ""
|
||||
|
||||
if $used {
|
||||
set ffc [get_cells -of_objects $ff]
|
||||
set cell_bel [get_property BEL $ffc]
|
||||
# ex: FDRE
|
||||
set ffc [get_cells -of_objects $ff]
|
||||
set cell_bel [get_property BEL $ffc]
|
||||
# ex: FDRE
|
||||
set ref_name [get_property REF_NAME $ffc]
|
||||
#set cinv [get_property IS_C_INVERTED $ffc]
|
||||
|
||||
|
|
@ -55,11 +55,10 @@ foreach ff $ffs {
|
|||
set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C || REF_PIN_NAME == G}]
|
||||
set cinv [get_property IS_INVERTED $cpin]
|
||||
|
||||
set init [get_property INIT $ffc]
|
||||
set init [get_property INIT $ffc]
|
||||
|
||||
set usedstr "$cell_bel $ref_name $cinv $init"
|
||||
}
|
||||
puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
|
||||
puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
|
||||
}
|
||||
close $fp
|
||||
|
||||
|
|
|
|||
|
|
@ -24,4 +24,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -24,4 +24,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -43,9 +43,9 @@ foreach ff $ffs {
|
|||
set used [get_property IS_USED $ff]
|
||||
set usedstr ""
|
||||
if $used {
|
||||
set ffc [get_cells -of_objects $ff]
|
||||
set cell_bel [get_property BEL $ffc]
|
||||
# ex: FDRE
|
||||
set ffc [get_cells -of_objects $ff]
|
||||
set cell_bel [get_property BEL $ffc]
|
||||
# ex: FDRE
|
||||
set ref_name [get_property REF_NAME $ffc]
|
||||
#set cinv [get_property IS_C_INVERTED $ffc]
|
||||
|
||||
|
|
@ -53,7 +53,6 @@ foreach ff $ffs {
|
|||
set cinv [get_property IS_INVERTED $cpin]
|
||||
set usedstr "$cell_bel $ref_name $cinv"
|
||||
}
|
||||
puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
|
||||
puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
|
||||
}
|
||||
close $fp
|
||||
|
||||
|
|
|
|||
|
|
@ -24,4 +24,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -24,4 +24,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -24,4 +24,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -24,4 +24,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -24,4 +24,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -23,4 +23,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -28,4 +28,3 @@ write_checkpoint -force design.dcp
|
|||
# BRAM SDP WEA check, to make test slightly easier to write
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-1931}]
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -22,4 +22,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -28,4 +28,3 @@ write_checkpoint -force design.dcp
|
|||
# BRAM SDP WEA check, to make test slightly easier to write
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-1931}]
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -29,22 +29,21 @@ route_design
|
|||
write_checkpoint -force design.dcp
|
||||
|
||||
proc write_txtdata {filename} {
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
puts "Dumping pips from tile $tile"
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
puts "Dumping pips from tile $tile"
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
write_bitstream -force design.bit
|
||||
write_txtdata design.txt
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ route_design
|
|||
set fp [open "../todo.txt" r]
|
||||
set todo_lines {}
|
||||
for {gets $fp line} {$line != ""} {gets $fp line} {
|
||||
lappend todo_lines [split $line .]
|
||||
lappend todo_lines [split $line .]
|
||||
}
|
||||
close $fp
|
||||
|
||||
|
|
@ -33,59 +33,58 @@ set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi
|
|||
set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
|
||||
|
||||
for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
|
||||
set line [lindex $todo_lines $idx]
|
||||
set line [lindex $todo_lines $idx]
|
||||
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]}
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]}
|
||||
|
||||
set clb_dst_wire [get_wires -filter {TILE_NAME =~ CLB*} -of_objects [get_nodes -of_objects [get_wire $tile/$dst_wire]]]
|
||||
set clb_src_wire [get_wires -filter {TILE_NAME =~ CLB*} -of_objects [get_nodes -of_objects [get_wire $tile/$src_wire]]]
|
||||
set clb_dst_wire [get_wires -filter {TILE_NAME =~ CLB*} -of_objects [get_nodes -of_objects [get_wire $tile/$dst_wire]]]
|
||||
set clb_src_wire [get_wires -filter {TILE_NAME =~ CLB*} -of_objects [get_nodes -of_objects [get_wire $tile/$src_wire]]]
|
||||
|
||||
set clb_dst_pin [get_site_pins -of_objects [get_nodes -downhill -of_objects [get_pips -of_objects $clb_dst_wire]]]
|
||||
set clb_src_pin [get_site_pins -of_objects [get_nodes -uphill -of_objects [get_pips -of_objects $clb_src_wire]]]
|
||||
set clb_dst_pin [get_site_pins -of_objects [get_nodes -downhill -of_objects [get_pips -of_objects $clb_dst_wire]]]
|
||||
set clb_src_pin [get_site_pins -of_objects [get_nodes -uphill -of_objects [get_pips -of_objects $clb_src_wire]]]
|
||||
|
||||
set src_prefix [regsub {(.*/.).*} ${clb_src_pin} {\1}]
|
||||
set dst_prefix [regsub {(.*/.).*} ${clb_dst_pin} {\1}]
|
||||
set src_prefix [regsub {(.*/.).*} ${clb_src_pin} {\1}]
|
||||
set dst_prefix [regsub {(.*/.).*} ${clb_dst_pin} {\1}]
|
||||
|
||||
if {$src_prefix == $dst_prefix} {
|
||||
set slice [get_sites -of_objects $clb_dst_pin]
|
||||
set lut [regsub {.*/} $src_prefix {}]6LUT
|
||||
if {$src_prefix == $dst_prefix} {
|
||||
set slice [get_sites -of_objects $clb_dst_pin]
|
||||
set lut [regsub {.*/} $src_prefix {}]6LUT
|
||||
|
||||
puts "=== $slice $lut ($clb_src_pin -> $clb_dst_pin)"
|
||||
puts "=== $slice $lut ($clb_src_pin -> $clb_dst_pin)"
|
||||
|
||||
set mynet [create_net mynet_$idx]
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set lutin [regsub {.*(.)} $clb_dst_pin {A\1}]
|
||||
set_property -dict "LOC $slice BEL $lut LOCK_PINS I0:$lutin" $mylut
|
||||
connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
|
||||
}
|
||||
set mynet [create_net mynet_$idx]
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set lutin [regsub {.*(.)} $clb_dst_pin {A\1}]
|
||||
set_property -dict "LOC $slice BEL $lut LOCK_PINS I0:$lutin" $mylut
|
||||
connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
|
||||
}
|
||||
}
|
||||
|
||||
proc write_txtdata {filename} {
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
if {$all_pips != {}} {
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
if {$all_pips != {}} {
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
route_design
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
write_txtdata design.txt
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ route_design
|
|||
set fp [open "../todo.txt" r]
|
||||
set todo_lines {}
|
||||
for {gets $fp line} {$line != ""} {gets $fp line} {
|
||||
lappend todo_lines [split $line .]
|
||||
lappend todo_lines [split $line .]
|
||||
}
|
||||
close $fp
|
||||
|
||||
|
|
@ -33,55 +33,54 @@ set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi
|
|||
set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
|
||||
|
||||
for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
|
||||
set line [lindex $todo_lines $idx]
|
||||
puts "== $idx: $line"
|
||||
set line [lindex $todo_lines $idx]
|
||||
puts "== $idx: $line"
|
||||
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
|
||||
|
||||
set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
|
||||
set recv_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $tile/$dst_wire]]]]]
|
||||
set recv_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $tile/$dst_wire]]]]]
|
||||
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set_property -dict "LOC $driver_site BEL A6LUT" $mylut
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set_property -dict "LOC $driver_site BEL A6LUT" $mylut
|
||||
|
||||
set myff [create_cell -reference FDRE myff_$idx]
|
||||
set ffbel [lindex "AFF A5FF BFF B5FF CFF C5FF DFF D5FF" [expr {int(rand()*8)}]]
|
||||
set_property -dict "LOC $recv_site BEL $ffbel" $myff
|
||||
set myff [create_cell -reference FDRE myff_$idx]
|
||||
set ffbel [lindex "AFF A5FF BFF B5FF CFF C5FF DFF D5FF" [expr {int(rand()*8)}]]
|
||||
set_property -dict "LOC $recv_site BEL $ffbel" $myff
|
||||
|
||||
set mynet [create_net mynet_$idx]
|
||||
connect_net -net $mynet -objects "$mylut/O $myff/C"
|
||||
route_via $mynet "$tile/$src_wire $tile/$dst_wire"
|
||||
set mynet [create_net mynet_$idx]
|
||||
connect_net -net $mynet -objects "$mylut/O $myff/C"
|
||||
route_via $mynet "$tile/$src_wire $tile/$dst_wire"
|
||||
}
|
||||
|
||||
proc write_txtdata {filename} {
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
if {$all_pips != {}} {
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
if {$all_pips != {}} {
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
route_design
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
write_txtdata design.txt
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ route_design
|
|||
set fp [open "../todo.txt" r]
|
||||
set todo_lines {}
|
||||
for {gets $fp line} {$line != ""} {gets $fp line} {
|
||||
lappend todo_lines [split $line .]
|
||||
lappend todo_lines [split $line .]
|
||||
}
|
||||
close $fp
|
||||
|
||||
|
|
@ -33,55 +33,54 @@ set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi
|
|||
set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
|
||||
|
||||
for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
|
||||
set line [lindex $todo_lines $idx]
|
||||
puts "== $idx: $line"
|
||||
set line [lindex $todo_lines $idx]
|
||||
puts "== $idx: $line"
|
||||
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
|
||||
|
||||
set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
|
||||
set recv_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $tile/$dst_wire]]]]]
|
||||
set recv_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $tile/$dst_wire]]]]]
|
||||
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set_property -dict "LOC $driver_site BEL A6LUT" $mylut
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set_property -dict "LOC $driver_site BEL A6LUT" $mylut
|
||||
|
||||
set myff [create_cell -reference FDRE myff_$idx]
|
||||
set ffbel [lindex "AFF A5FF BFF B5FF CFF C5FF DFF D5FF" [expr {int(rand()*8)}]]
|
||||
set_property -dict "LOC $recv_site BEL $ffbel" $myff
|
||||
set myff [create_cell -reference FDRE myff_$idx]
|
||||
set ffbel [lindex "AFF A5FF BFF B5FF CFF C5FF DFF D5FF" [expr {int(rand()*8)}]]
|
||||
set_property -dict "LOC $recv_site BEL $ffbel" $myff
|
||||
|
||||
set mynet [create_net mynet_$idx]
|
||||
connect_net -net $mynet -objects "$mylut/O $myff/R"
|
||||
route_via $mynet "$tile/$src_wire $tile/$dst_wire"
|
||||
set mynet [create_net mynet_$idx]
|
||||
connect_net -net $mynet -objects "$mylut/O $myff/R"
|
||||
route_via $mynet "$tile/$src_wire $tile/$dst_wire"
|
||||
}
|
||||
|
||||
proc write_txtdata {filename} {
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
if {$all_pips != {}} {
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
if {$all_pips != {}} {
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
route_design
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
write_txtdata design.txt
|
||||
|
||||
|
|
|
|||
|
|
@ -26,16 +26,16 @@ proc write_txtdata {filename} {
|
|||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
if {$all_pips != {}} {
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
|
@ -49,7 +49,7 @@ proc loop { line idx int_l_tile int_r_tile } {
|
|||
if {$tile_type == "INT_R"} {set tile $int_r_tile; set other_tile $int_l_tile}
|
||||
|
||||
set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set_property -dict "LOC $driver_site BEL A6LUT" $mylut
|
||||
|
|
@ -63,7 +63,7 @@ proc load_todo_lines {} {
|
|||
set fp [open "../todo.txt" r]
|
||||
set todo_lines {}
|
||||
for {gets $fp line} {$line != ""} {gets $fp line} {
|
||||
lappend todo_lines [split $line .]
|
||||
lappend todo_lines [split $line .]
|
||||
}
|
||||
close $fp
|
||||
return $todo_lines
|
||||
|
|
@ -79,10 +79,10 @@ proc run {} {
|
|||
set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
|
||||
|
||||
for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
|
||||
set line [lindex $todo_lines $idx]
|
||||
set line [lindex $todo_lines $idx]
|
||||
puts "== $idx: $line"
|
||||
set int_l_tile [lindex $int_l_tiles $idx]
|
||||
set int_r_tile [lindex $int_r_tiles $idx]
|
||||
set int_l_tile [lindex $int_l_tiles $idx]
|
||||
set int_r_tile [lindex $int_r_tiles $idx]
|
||||
loop $line $idx $int_l_tile $int_r_tile
|
||||
}
|
||||
|
||||
|
|
@ -94,4 +94,3 @@ proc run {} {
|
|||
}
|
||||
|
||||
run
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ source ../../../utils/utils.tcl
|
|||
set fp [open "../todo.txt" r]
|
||||
set todo_lines {}
|
||||
for {gets $fp line} {$line != ""} {gets $fp line} {
|
||||
lappend todo_lines [split $line .]
|
||||
lappend todo_lines [split $line .]
|
||||
}
|
||||
close $fp
|
||||
|
||||
|
|
@ -32,57 +32,56 @@ set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi
|
|||
set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
|
||||
|
||||
for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
|
||||
set line [lindex $todo_lines $idx]
|
||||
puts "== $idx: $line"
|
||||
set line [lindex $todo_lines $idx]
|
||||
puts "== $idx: $line"
|
||||
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
|
||||
|
||||
set recv_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
set recv_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
|
||||
set mynet [create_net mynet_$idx]
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set_property -dict "LOC $recv_site BEL A6LUT" $mylut
|
||||
set mynet [create_net mynet_$idx]
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set_property -dict "LOC $recv_site BEL A6LUT" $mylut
|
||||
|
||||
if {$src_wire == "VCC_WIRE"} {
|
||||
set mytie [create_cell -reference VCC mytie_$idx]
|
||||
connect_net -net $mynet -objects "$mytie/P $mylut/I0"
|
||||
}
|
||||
if {$src_wire == "VCC_WIRE"} {
|
||||
set mytie [create_cell -reference VCC mytie_$idx]
|
||||
connect_net -net $mynet -objects "$mytie/P $mylut/I0"
|
||||
}
|
||||
|
||||
if {$src_wire == "GND_WIRE"} {
|
||||
set mytie [create_cell -reference GND mytie_$idx]
|
||||
connect_net -net $mynet -objects "$mytie/G $mylut/I0"
|
||||
}
|
||||
if {$src_wire == "GND_WIRE"} {
|
||||
set mytie [create_cell -reference GND mytie_$idx]
|
||||
connect_net -net $mynet -objects "$mytie/G $mylut/I0"
|
||||
}
|
||||
|
||||
route_via $mynet "$tile/$src_wire $tile/$dst_wire"
|
||||
route_via $mynet "$tile/$src_wire $tile/$dst_wire"
|
||||
}
|
||||
|
||||
proc write_txtdata {filename} {
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
if {$all_pips != {}} {
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
if {$all_pips != {}} {
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
route_design
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
write_txtdata design.txt
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ route_design
|
|||
set fp [open "../todo.txt" r]
|
||||
set todo_lines {}
|
||||
for {gets $fp line} {$line != ""} {gets $fp line} {
|
||||
lappend todo_lines [split $line .]
|
||||
lappend todo_lines [split $line .]
|
||||
}
|
||||
close $fp
|
||||
|
||||
|
|
@ -32,56 +32,55 @@ set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi
|
|||
set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
|
||||
|
||||
for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
|
||||
set line [lindex $todo_lines $idx]
|
||||
puts "== $idx: $line"
|
||||
set line [lindex $todo_lines $idx]
|
||||
puts "== $idx: $line"
|
||||
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
|
||||
|
||||
puts "PIP Tile: $tile"
|
||||
puts "PIP Tile: $tile"
|
||||
|
||||
set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
|
||||
puts "LUT Tile (Site): $other_tile ($driver_site)"
|
||||
puts "LUT Tile (Site): $other_tile ($driver_site)"
|
||||
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set_property -dict "LOC $driver_site BEL A6LUT" $mylut
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set_property -dict "LOC $driver_site BEL A6LUT" $mylut
|
||||
|
||||
set mynet [create_net mynet_$idx]
|
||||
connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
|
||||
route_via $mynet "$tile/$src_wire $tile/$dst_wire"
|
||||
set mynet [create_net mynet_$idx]
|
||||
connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
|
||||
route_via $mynet "$tile/$src_wire $tile/$dst_wire"
|
||||
}
|
||||
|
||||
proc write_txtdata {filename} {
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
if {$all_pips != {}} {
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
if {$all_pips != {}} {
|
||||
puts "Dumping pips."
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
route_design
|
||||
|
||||
# Ex: ERROR: [DRC RTSTAT-5] Partial antennas: 1 net(s) have a partial antenna. The problem bus(es) and/or net(s) are mynet_2.
|
||||
# set_property IS_ENABLED 0 [get_drc_checks {RTSTAT-5}]
|
||||
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
write_txtdata design.txt
|
||||
|
||||
|
|
|
|||
|
|
@ -21,20 +21,19 @@ write_checkpoint -force bipiplist.dcp
|
|||
source ../../utils/utils.tcl
|
||||
|
||||
proc print_tile_pips {tile_type filename} {
|
||||
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
|
||||
puts "Dumping bidirectional PIPs for tile $tile ($tile_type) to $filename."
|
||||
set fp [open $filename w]
|
||||
foreach pip [lsort [get_pips -filter {!IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set dst [get_wires -downhill -of_objects $pip]
|
||||
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
|
||||
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
|
||||
puts $fp "$tile_type.[regsub {.*/} $src ""].[regsub {.*/} $dst ""]"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
|
||||
puts "Dumping bidirectional PIPs for tile $tile ($tile_type) to $filename."
|
||||
set fp [open $filename w]
|
||||
foreach pip [lsort [get_pips -filter {!IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set dst [get_wires -downhill -of_objects $pip]
|
||||
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
|
||||
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
|
||||
puts $fp "$tile_type.[regsub {.*/} $src ""].[regsub {.*/} $dst ""]"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
print_tile_pips INT_L bipips_int_l.txt
|
||||
print_tile_pips INT_R bipips_int_r.txt
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ source ../../../utils/utils.tcl
|
|||
set fp [open "../todo.txt" r]
|
||||
set todo_lines {}
|
||||
for {gets $fp line} {$line != ""} {gets $fp line} {
|
||||
lappend todo_lines [split $line .]
|
||||
lappend todo_lines [split $line .]
|
||||
}
|
||||
close $fp
|
||||
|
||||
|
|
@ -34,46 +34,45 @@ set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi
|
|||
set fp [open "design.txt" w]
|
||||
|
||||
for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
|
||||
set line [lindex $todo_lines $idx]
|
||||
puts "== $idx: $line"
|
||||
set line [lindex $todo_lines $idx]
|
||||
puts "== $idx: $line"
|
||||
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
set tile_type [lindex $line 0]
|
||||
set dst_wire [lindex $line 1]
|
||||
set src_wire [lindex $line 2]
|
||||
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
|
||||
if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
|
||||
if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
|
||||
|
||||
puts "PIP Tile: $tile"
|
||||
puts "PIP Tile: $tile"
|
||||
|
||||
set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
|
||||
-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
|
||||
|
||||
puts "LUT Tile (Site): $other_tile ($driver_site)"
|
||||
puts "LUT Tile (Site): $other_tile ($driver_site)"
|
||||
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set_property -dict "LOC $driver_site BEL A6LUT" $mylut
|
||||
set mylut [create_cell -reference LUT1 mylut_$idx]
|
||||
set_property -dict "LOC $driver_site BEL A6LUT" $mylut
|
||||
|
||||
set mynet [create_net mynet_$idx]
|
||||
connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
|
||||
route_via $mynet "$tile/$src_wire $tile/$dst_wire"
|
||||
set mynet [create_net mynet_$idx]
|
||||
connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
|
||||
route_via $mynet "$tile/$src_wire $tile/$dst_wire"
|
||||
|
||||
if {[get_pips -filter "NAME == \"${tile}/${tile_type}.${src_wire}<<->>${dst_wire}\" || NAME == \"${tile}/${tile_type}.${dst_wire}<<->>${src_wire}\"" -of_objects [get_nets $mynet]] != ""} {
|
||||
puts $fp "A $tile/$dst_wire $tile/$src_wire"
|
||||
}
|
||||
if {[get_pips -filter "NAME == \"${tile}/${tile_type}.${src_wire}<<->>${dst_wire}\" || NAME == \"${tile}/${tile_type}.${dst_wire}<<->>${src_wire}\"" -of_objects [get_nets $mynet]] != ""} {
|
||||
puts $fp "A $tile/$dst_wire $tile/$src_wire"
|
||||
}
|
||||
}
|
||||
|
||||
route_design
|
||||
|
||||
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
|
||||
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
puts $fp "B [get_wires -of_objects $pip]"
|
||||
}
|
||||
foreach pip [filter $all_pips "TILE == $tile"] {
|
||||
puts $fp "B [get_wires -of_objects $pip]"
|
||||
}
|
||||
}
|
||||
|
||||
close $fp
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -28,16 +28,15 @@ set net [get_nets o_OBUF]
|
|||
set pips [get_pips -of_objects $tile]
|
||||
|
||||
for {set i 0} {$i < [llength $pips]} {incr i} {
|
||||
set pip [lindex $pips $i]
|
||||
set_property IS_ROUTE_FIXED 0 $net
|
||||
route_design -unroute -net $net
|
||||
set n1 [get_nodes -uphill -of_objects $pip]
|
||||
set n2 [get_nodes -downhill -of_objects $pip]
|
||||
route_via $net "$n1 $n2"
|
||||
write_checkpoint -force design_$i.dcp
|
||||
write_bitstream -force design_$i.bit
|
||||
set fp [open "design_$i.txt" w]
|
||||
puts $fp "$tile $pip"
|
||||
close $fp
|
||||
set pip [lindex $pips $i]
|
||||
set_property IS_ROUTE_FIXED 0 $net
|
||||
route_design -unroute -net $net
|
||||
set n1 [get_nodes -uphill -of_objects $pip]
|
||||
set n2 [get_nodes -downhill -of_objects $pip]
|
||||
route_via $net "$n1 $n2"
|
||||
write_checkpoint -force design_$i.dcp
|
||||
write_bitstream -force design_$i.bit
|
||||
set fp [open "design_$i.txt" w]
|
||||
puts $fp "$tile $pip"
|
||||
close $fp
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -21,50 +21,49 @@ write_checkpoint -force design.dcp
|
|||
# write_bitstream -force design.bit
|
||||
|
||||
proc write_clb_ppips_db {filename tile} {
|
||||
set fp [open $filename "w"]
|
||||
set tile [get_tiles $tile]
|
||||
set tile_type [get_property TILE_TYPE $tile]
|
||||
set fp [open $filename "w"]
|
||||
set tile [get_tiles $tile]
|
||||
set tile_type [get_property TILE_TYPE $tile]
|
||||
|
||||
foreach pip [get_pips -of_objects $tile] {
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
if {[get_property IS_PSEUDO $pip]} {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] hint"
|
||||
} elseif {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
|
||||
}
|
||||
}
|
||||
foreach pip [get_pips -of_objects $tile] {
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
if {[get_property IS_PSEUDO $pip]} {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] hint"
|
||||
} elseif {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
|
||||
}
|
||||
}
|
||||
|
||||
close $fp
|
||||
close $fp
|
||||
}
|
||||
|
||||
proc write_int_ppips_db {filename tile} {
|
||||
set fp [open $filename "w"]
|
||||
set tile [get_tiles $tile]
|
||||
set tile_type [get_property TILE_TYPE $tile]
|
||||
set fp [open $filename "w"]
|
||||
set tile [get_tiles $tile]
|
||||
set tile_type [get_property TILE_TYPE $tile]
|
||||
|
||||
foreach pip [get_pips -of_objects [get_wires $tile/VCC_WIRE]] {
|
||||
set wire [regsub {.*/} [get_wires -downhill -of_objects $pip] ""]
|
||||
puts $fp "${tile_type}.${wire}.VCC_WIRE default"
|
||||
}
|
||||
foreach pip [get_pips -of_objects [get_wires $tile/VCC_WIRE]] {
|
||||
set wire [regsub {.*/} [get_wires -downhill -of_objects $pip] ""]
|
||||
puts $fp "${tile_type}.${wire}.VCC_WIRE default"
|
||||
}
|
||||
|
||||
foreach pip [get_pips -of_objects $tile] {
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
|
||||
}
|
||||
}
|
||||
foreach pip [get_pips -of_objects $tile] {
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
|
||||
}
|
||||
}
|
||||
|
||||
close $fp
|
||||
close $fp
|
||||
}
|
||||
|
||||
foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R INT_L INT_R} {
|
||||
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
|
||||
if {[llength $tiles] != 0} {
|
||||
set tile [lindex $tiles 0]
|
||||
write_clb_ppips_db "ppips_[string tolower $tile_type].txt" $tile
|
||||
}
|
||||
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
|
||||
if {[llength $tiles] != 0} {
|
||||
set tile [lindex $tiles 0]
|
||||
write_clb_ppips_db "ppips_[string tolower $tile_type].txt" $tile
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -6,14 +6,14 @@ set downhill_fp [open downhill_wires.txt w]
|
|||
set uphill_fp [open uphill_wires.txt w]
|
||||
#set_param tcl.collectionResultDisplayLimit 0
|
||||
foreach pip [get_pips] {
|
||||
foreach downhill_node [get_nodes -downhill -of_object $pip] {
|
||||
set ordered_downhill_wires [get_wires -from $pip -of_object $downhill_node]
|
||||
puts $downhill_fp "$pip $downhill_node $ordered_downhill_wires"
|
||||
}
|
||||
foreach uphill_node [get_nodes -uphill -of_object $pip] {
|
||||
set ordered_uphill_wires [get_wires -to $pip -of_object $uphill_node]
|
||||
puts $uphill_fp "$pip $uphill_node $ordered_uphill_wires"
|
||||
}
|
||||
foreach downhill_node [get_nodes -downhill -of_object $pip] {
|
||||
set ordered_downhill_wires [get_wires -from $pip -of_object $downhill_node]
|
||||
puts $downhill_fp "$pip $downhill_node $ordered_downhill_wires"
|
||||
}
|
||||
foreach uphill_node [get_nodes -uphill -of_object $pip] {
|
||||
set ordered_uphill_wires [get_wires -to $pip -of_object $uphill_node]
|
||||
puts $uphill_fp "$pip $uphill_node $ordered_uphill_wires"
|
||||
}
|
||||
}
|
||||
close $downhill_fp
|
||||
close $uphill_fp
|
||||
|
|
|
|||
|
|
@ -15,8 +15,8 @@ set num_site_pins 0
|
|||
set num_site_pips 0
|
||||
puts $fp "sites,[llength $sites]"
|
||||
foreach site $sites {
|
||||
set num_site_pins [expr $num_site_pins + [llength [get_site_pins -of_objects $site]]]
|
||||
set num_site_pips [expr $num_site_pips + [llength [get_site_pips -of_objects $site]]]
|
||||
set num_site_pins [expr $num_site_pins + [llength [get_site_pins -of_objects $site]]]
|
||||
set num_site_pips [expr $num_site_pips + [llength [get_site_pips -of_objects $site]]]
|
||||
}
|
||||
puts $fp "site_pins,$num_site_pins"
|
||||
puts $fp "site_pips,$num_site_pips"
|
||||
|
|
|
|||
|
|
@ -5,132 +5,132 @@ open_io_design -name io_1
|
|||
set root_fp [open root.csv w]
|
||||
puts $root_fp "filetype,subtype,filename"
|
||||
foreach tile [get_tiles] {
|
||||
set fname tile_$tile.json5
|
||||
set tile_type [get_property TYPE $tile]
|
||||
puts $root_fp "tile,$tile_type,$fname"
|
||||
set fname tile_$tile.json5
|
||||
set tile_type [get_property TYPE $tile]
|
||||
puts $root_fp "tile,$tile_type,$fname"
|
||||
|
||||
set fp [open $fname w]
|
||||
puts $fp "\{"
|
||||
puts $fp "\t\"tile\": \"$tile\","
|
||||
# tile properties:
|
||||
# CLASS COLUMN DEVICE_ID FIRST_SITE_ID GRID_POINT_X GRID_POINT_Y INDEX
|
||||
# INT_TILE_X INT_TILE_Y IS_CENTER_TILE IS_DCM_TILE IS_GT_CLOCK_SITE_TILE
|
||||
# IS_GT_SITE_TILE NAME NUM_ARCS NUM_SITES ROW SLR_REGION_ID
|
||||
# TILE_PATTERN_IDX TILE_TYPE TILE_TYPE_INDEX TILE_X TILE_Y TYPE
|
||||
puts $fp "\t\"type\": \"$tile_type\","
|
||||
puts $fp "\t\"x\": [get_property GRID_POINT_X $tile],"
|
||||
puts $fp "\t\"y\": [get_property GRID_POINT_Y $tile],"
|
||||
puts $fp "\t\"sites\": \["
|
||||
foreach site [get_sites -of_objects $tile] {
|
||||
# site properties:
|
||||
# ALTERNATE_SITE_TYPES CLASS CLOCK_REGION IS_BONDED IS_CLOCK_BUFFER
|
||||
# IS_CLOCK_PAD IS_GLOBAL_CLOCK_BUFFER IS_GLOBAL_CLOCK_PAD IS_PAD
|
||||
# IS_REGIONAL_CLOCK_BUFFER IS_REGIONAL_CLOCK_PAD IS_RESERVED IS_TEST
|
||||
# IS_USED MANUAL_ROUTING NAME NUM_ARCS NUM_BELS NUM_INPUTS NUM_OUTPUTS
|
||||
# NUM_PINS PRIMITIVE_COUNT PROHIBIT PROHIBIT_FROM_PERSIST RPM_X RPM_Y
|
||||
# SITE_PIPS SITE_TYPE
|
||||
set fp [open $fname w]
|
||||
puts $fp "\{"
|
||||
puts $fp "\t\"tile\": \"$tile\","
|
||||
# tile properties:
|
||||
# CLASS COLUMN DEVICE_ID FIRST_SITE_ID GRID_POINT_X GRID_POINT_Y INDEX
|
||||
# INT_TILE_X INT_TILE_Y IS_CENTER_TILE IS_DCM_TILE IS_GT_CLOCK_SITE_TILE
|
||||
# IS_GT_SITE_TILE NAME NUM_ARCS NUM_SITES ROW SLR_REGION_ID
|
||||
# TILE_PATTERN_IDX TILE_TYPE TILE_TYPE_INDEX TILE_X TILE_Y TYPE
|
||||
puts $fp "\t\"type\": \"$tile_type\","
|
||||
puts $fp "\t\"x\": [get_property GRID_POINT_X $tile],"
|
||||
puts $fp "\t\"y\": [get_property GRID_POINT_Y $tile],"
|
||||
puts $fp "\t\"sites\": \["
|
||||
foreach site [get_sites -of_objects $tile] {
|
||||
# site properties:
|
||||
# ALTERNATE_SITE_TYPES CLASS CLOCK_REGION IS_BONDED IS_CLOCK_BUFFER
|
||||
# IS_CLOCK_PAD IS_GLOBAL_CLOCK_BUFFER IS_GLOBAL_CLOCK_PAD IS_PAD
|
||||
# IS_REGIONAL_CLOCK_BUFFER IS_REGIONAL_CLOCK_PAD IS_RESERVED IS_TEST
|
||||
# IS_USED MANUAL_ROUTING NAME NUM_ARCS NUM_BELS NUM_INPUTS NUM_OUTPUTS
|
||||
# NUM_PINS PRIMITIVE_COUNT PROHIBIT PROHIBIT_FROM_PERSIST RPM_X RPM_Y
|
||||
# SITE_PIPS SITE_TYPE
|
||||
|
||||
puts $fp "\t\t\{"
|
||||
puts $fp "\t\t\t\"site\":\"$site\","
|
||||
puts $fp "\t\t\t\"type\":\"[get_property SITE_TYPE $site]\","
|
||||
puts $fp "\t\t\t\"site_pins\": \["
|
||||
foreach site_pin [get_site_pins -of_objects $site] {
|
||||
# site_pin properties:
|
||||
# CLASS DIRECTION INDEX INDEX_IN_BUS INDEX_IN_SITE INDEX_IN_TILE IS_BAD
|
||||
# IS_INPUT IS_OUTPUT IS_PART_OF_BUS IS_TEST IS_USED NAME SITE_ID
|
||||
# SPEED_INDEX
|
||||
puts $fp "\t\t\t\{"
|
||||
puts $fp "\t\t\t\t\"site_pin\":\"$site_pin\","
|
||||
puts $fp "\t\t\t\t\"direction\":\"[get_property DIRECTION $site_pin]\","
|
||||
set site_pin_node [get_nodes -of_objects $site_pin]
|
||||
if {[llength $site_pin_node] == 0} {
|
||||
puts $fp "\t\t\t\t\"node\":null,"
|
||||
} else {
|
||||
puts $fp "\t\t\t\t\"node\":\"$site_pin_node\","
|
||||
}
|
||||
puts $fp "\t\t\t\},"
|
||||
puts $fp "\t\t\{"
|
||||
puts $fp "\t\t\t\"site\":\"$site\","
|
||||
puts $fp "\t\t\t\"type\":\"[get_property SITE_TYPE $site]\","
|
||||
puts $fp "\t\t\t\"site_pins\": \["
|
||||
foreach site_pin [get_site_pins -of_objects $site] {
|
||||
# site_pin properties:
|
||||
# CLASS DIRECTION INDEX INDEX_IN_BUS INDEX_IN_SITE INDEX_IN_TILE IS_BAD
|
||||
# IS_INPUT IS_OUTPUT IS_PART_OF_BUS IS_TEST IS_USED NAME SITE_ID
|
||||
# SPEED_INDEX
|
||||
puts $fp "\t\t\t\{"
|
||||
puts $fp "\t\t\t\t\"site_pin\":\"$site_pin\","
|
||||
puts $fp "\t\t\t\t\"direction\":\"[get_property DIRECTION $site_pin]\","
|
||||
set site_pin_node [get_nodes -of_objects $site_pin]
|
||||
if {[llength $site_pin_node] == 0} {
|
||||
puts $fp "\t\t\t\t\"node\":null,"
|
||||
} else {
|
||||
puts $fp "\t\t\t\t\"node\":\"$site_pin_node\","
|
||||
}
|
||||
puts $fp "\t\t\t\},"
|
||||
}
|
||||
puts $fp "\t\t\t\],"
|
||||
puts $fp "\t\t\t\"site_pips\": \["
|
||||
foreach site_pip [get_site_pips -of_objects $site] {
|
||||
puts $fp "\t\t\t\{"
|
||||
# site_pips properties:
|
||||
# CLASS FROM_PIN IS_FIXED IS_USED NAME SITE TO_PIN
|
||||
puts $fp "\t\t\t\t\"site_pip\":\"$site_pip\","
|
||||
puts $fp "\t\t\t\t\"to_pin\":\"[get_property TO_PIN $site_pip]\","
|
||||
puts $fp "\t\t\t\t\"from_pin\":\"[get_property FROM_PIN $site_pip]\","
|
||||
puts $fp "\t\t\t\},"
|
||||
}
|
||||
puts $fp "\t\t\t\],"
|
||||
|
||||
puts $fp "\t\t\t\"package_pins\": \["
|
||||
foreach package_pin [get_package_pins -of_objects $site] {
|
||||
puts $fp "\t\t\t\t\{"
|
||||
puts $fp "\t\t\t\t\t\"package_pin\":\"$package_pin\","
|
||||
puts $fp "\t\t\t\t\},"
|
||||
}
|
||||
puts $fp "\t\t\t\],"
|
||||
|
||||
puts $fp "\t\t\},"
|
||||
}
|
||||
puts $fp "\t\t\t\],"
|
||||
puts $fp "\t\t\t\"site_pips\": \["
|
||||
foreach site_pip [get_site_pips -of_objects $site] {
|
||||
puts $fp "\t\t\t\{"
|
||||
# site_pips properties:
|
||||
# CLASS FROM_PIN IS_FIXED IS_USED NAME SITE TO_PIN
|
||||
puts $fp "\t\t\t\t\"site_pip\":\"$site_pip\","
|
||||
puts $fp "\t\t\t\t\"to_pin\":\"[get_property TO_PIN $site_pip]\","
|
||||
puts $fp "\t\t\t\t\"from_pin\":\"[get_property FROM_PIN $site_pip]\","
|
||||
puts $fp "\t\t\t\},"
|
||||
puts $fp "\t\],"
|
||||
puts $fp "\t\"pips\": \["
|
||||
foreach pip [get_pips -of_objects $tile] {
|
||||
# pip properties:
|
||||
# CAN_INVERT CLASS IS_BUFFERED_2_0 IS_BUFFERED_2_1 IS_DIRECTIONAL
|
||||
# IS_EXCLUDED_PIP IS_FIXED_INVERSION IS_INVERTED IS_PSEUDO IS_SITE_PIP
|
||||
# IS_TEST_PIP NAME SPEED_INDEX TILE
|
||||
puts $fp "\t\t\{"
|
||||
puts $fp "\t\t\t\"pip\":\"$pip\","
|
||||
puts $fp "\t\t\t\"src_wire\":\"[get_wires -uphill -of_objects $pip]\","
|
||||
puts $fp "\t\t\t\"dst_wire\":\"[get_wires -downhill -of_objects $pip]\","
|
||||
puts $fp "\t\t\t\"is_pseudo\":\"[get_property IS_PSEUDO $pip]\","
|
||||
puts $fp "\t\t\t\"is_directional\":\"[get_property IS_DIRECTIONAL $pip]\","
|
||||
puts $fp "\t\t\t\"can_invert\":\"[get_property CAN_INVERT $pip]\","
|
||||
puts $fp "\t\t\},"
|
||||
}
|
||||
puts $fp "\t\t\t\],"
|
||||
puts $fp "\t\],"
|
||||
|
||||
puts $fp "\t\t\t\"package_pins\": \["
|
||||
foreach package_pin [get_package_pins -of_objects $site] {
|
||||
puts $fp "\t\t\t\t\{"
|
||||
puts $fp "\t\t\t\t\t\"package_pin\":\"$package_pin\","
|
||||
puts $fp "\t\t\t\t\},"
|
||||
puts $fp "\t\"wires\": \["
|
||||
foreach wire [get_wires -of_objects $tile] {
|
||||
# wire properties:
|
||||
# CLASS COST_CODE ID_IN_TILE_TYPE IS_CONNECTED IS_INPUT_PIN IS_OUTPUT_PIN
|
||||
# IS_PART_OF_BUS NAME NUM_DOWNHILL_PIPS NUM_INTERSECTS NUM_PIPS
|
||||
# NUM_TILE_PORTS NUM_UPHILL_PIPS SPEED_INDEX TILE_NAME TILE_PATTERN_OFFSET
|
||||
puts $fp "\t\t\{"
|
||||
puts $fp "\t\t\t\"wire\":\"$wire\","
|
||||
puts $fp "\t\t\},"
|
||||
}
|
||||
puts $fp "\t\t\t\],"
|
||||
|
||||
puts $fp "\t\t\},"
|
||||
}
|
||||
puts $fp "\t\],"
|
||||
puts $fp "\t\"pips\": \["
|
||||
foreach pip [get_pips -of_objects $tile] {
|
||||
# pip properties:
|
||||
# CAN_INVERT CLASS IS_BUFFERED_2_0 IS_BUFFERED_2_1 IS_DIRECTIONAL
|
||||
# IS_EXCLUDED_PIP IS_FIXED_INVERSION IS_INVERTED IS_PSEUDO IS_SITE_PIP
|
||||
# IS_TEST_PIP NAME SPEED_INDEX TILE
|
||||
puts $fp "\t\t\{"
|
||||
puts $fp "\t\t\t\"pip\":\"$pip\","
|
||||
puts $fp "\t\t\t\"src_wire\":\"[get_wires -uphill -of_objects $pip]\","
|
||||
puts $fp "\t\t\t\"dst_wire\":\"[get_wires -downhill -of_objects $pip]\","
|
||||
puts $fp "\t\t\t\"is_pseudo\":\"[get_property IS_PSEUDO $pip]\","
|
||||
puts $fp "\t\t\t\"is_directional\":\"[get_property IS_DIRECTIONAL $pip]\","
|
||||
puts $fp "\t\t\t\"can_invert\":\"[get_property CAN_INVERT $pip]\","
|
||||
puts $fp "\t\t\},"
|
||||
}
|
||||
puts $fp "\t\],"
|
||||
|
||||
puts $fp "\t\"wires\": \["
|
||||
foreach wire [get_wires -of_objects $tile] {
|
||||
# wire properties:
|
||||
# CLASS COST_CODE ID_IN_TILE_TYPE IS_CONNECTED IS_INPUT_PIN IS_OUTPUT_PIN
|
||||
# IS_PART_OF_BUS NAME NUM_DOWNHILL_PIPS NUM_INTERSECTS NUM_PIPS
|
||||
# NUM_TILE_PORTS NUM_UPHILL_PIPS SPEED_INDEX TILE_NAME TILE_PATTERN_OFFSET
|
||||
puts $fp "\t\t\{"
|
||||
puts $fp "\t\t\t\"wire\":\"$wire\","
|
||||
puts $fp "\t\t\},"
|
||||
}
|
||||
puts $fp "\t\],"
|
||||
puts $fp "\}"
|
||||
close $fp
|
||||
puts $fp "\t\],"
|
||||
puts $fp "\}"
|
||||
close $fp
|
||||
}
|
||||
|
||||
foreach node [get_nodes] {
|
||||
file mkdir [file dirname $node]
|
||||
set fname $node.json5
|
||||
puts $root_fp "node,,$fname"
|
||||
file mkdir [file dirname $node]
|
||||
set fname $node.json5
|
||||
puts $root_fp "node,,$fname"
|
||||
|
||||
set fp [open $fname w]
|
||||
# node properties:
|
||||
# BASE_CLOCK_REGION CLASS COST_CODE COST_CODE_NAME IS_BAD IS_COMPLETE
|
||||
# IS_GND IS_INPUT_PIN IS_OUTPUT_PIN IS_PIN IS_VCC NAME NUM_WIRES PIN_WIRE
|
||||
# SPEED_CLASS
|
||||
puts $fp "\{"
|
||||
puts $fp "\t\"node\": \"$node\","
|
||||
puts $fp "\t\"wires\": \["
|
||||
foreach wire [get_wires -of_objects $node] {
|
||||
# wire properties:
|
||||
# CLASS COST_CODE ID_IN_TILE_TYPE IS_CONNECTED IS_INPUT_PIN IS_OUTPUT_PIN
|
||||
# IS_PART_OF_BUS NAME NUM_DOWNHILL_PIPS NUM_INTERSECTS NUM_PIPS
|
||||
# NUM_TILE_PORTS NUM_UPHILL_PIPS SPEED_INDEX TILE_NAME TILE_PATTERN_OFFSET
|
||||
puts $fp "\t\t\{"
|
||||
puts $fp "\t\t\t\"wire\":\"$wire\","
|
||||
puts $fp "\t\t\},"
|
||||
}
|
||||
puts $fp "\t\]"
|
||||
puts $fp "\}"
|
||||
close $fp
|
||||
set fp [open $fname w]
|
||||
# node properties:
|
||||
# BASE_CLOCK_REGION CLASS COST_CODE COST_CODE_NAME IS_BAD IS_COMPLETE
|
||||
# IS_GND IS_INPUT_PIN IS_OUTPUT_PIN IS_PIN IS_VCC NAME NUM_WIRES PIN_WIRE
|
||||
# SPEED_CLASS
|
||||
puts $fp "\{"
|
||||
puts $fp "\t\"node\": \"$node\","
|
||||
puts $fp "\t\"wires\": \["
|
||||
foreach wire [get_wires -of_objects $node] {
|
||||
# wire properties:
|
||||
# CLASS COST_CODE ID_IN_TILE_TYPE IS_CONNECTED IS_INPUT_PIN IS_OUTPUT_PIN
|
||||
# IS_PART_OF_BUS NAME NUM_DOWNHILL_PIPS NUM_INTERSECTS NUM_PIPS
|
||||
# NUM_TILE_PORTS NUM_UPHILL_PIPS SPEED_INDEX TILE_NAME TILE_PATTERN_OFFSET
|
||||
puts $fp "\t\t\{"
|
||||
puts $fp "\t\t\t\"wire\":\"$wire\","
|
||||
puts $fp "\t\t\},"
|
||||
}
|
||||
puts $fp "\t\]"
|
||||
puts $fp "\}"
|
||||
close $fp
|
||||
}
|
||||
|
||||
close $root_fp
|
||||
|
|
|
|||
|
|
@ -27,45 +27,44 @@ set gnd_cell [create_cell -reference GND gnd_cell]
|
|||
connect_net -net $gnd_net -objects [get_pins $gnd_cell/G]
|
||||
|
||||
foreach site [get_sites -of_objects [filter [roi_tiles] -filter {TYPE == "DSP_L" || TYPE == "DSP_R"}] -filter {SITE_TYPE =~ DSP*}] {
|
||||
set cell [create_cell -reference DSP48E1 ${site}_cell]
|
||||
lappend cells $cell
|
||||
set_property LOC $site $cell
|
||||
foreach pin [get_pins -of_objects $cell -filter {DIRECTION == "IN"}] {
|
||||
connect_net -net $gnd_net -objects $pin
|
||||
}
|
||||
set cell [create_cell -reference DSP48E1 ${site}_cell]
|
||||
lappend cells $cell
|
||||
set_property LOC $site $cell
|
||||
foreach pin [get_pins -of_objects $cell -filter {DIRECTION == "IN"}] {
|
||||
connect_net -net $gnd_net -objects $pin
|
||||
}
|
||||
}
|
||||
|
||||
route_design
|
||||
|
||||
proc write_txtdata {filename} {
|
||||
upvar 1 cells cells
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
foreach cell $cells {
|
||||
set loc [get_property LOC $cell]
|
||||
set mask [get_property MASK $cell]
|
||||
set pattern [get_property PATTERN $cell]
|
||||
set tile [get_tiles -of_objects [get_sites -filter "NAME == $loc"]]
|
||||
puts $fp "$tile $loc $mask $pattern"
|
||||
}
|
||||
close $fp
|
||||
upvar 1 cells cells
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
foreach cell $cells {
|
||||
set loc [get_property LOC $cell]
|
||||
set mask [get_property MASK $cell]
|
||||
set pattern [get_property PATTERN $cell]
|
||||
set tile [get_tiles -of_objects [get_sites -filter "NAME == $loc"]]
|
||||
puts $fp "$tile $loc $mask $pattern"
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
proc randhex {len} {
|
||||
set s ""
|
||||
for {set i 0} {$i < $len} {incr i} {
|
||||
set s "$s[format %x [expr {int(rand()*16)}]]"
|
||||
}
|
||||
return $s
|
||||
set s ""
|
||||
for {set i 0} {$i < $len} {incr i} {
|
||||
set s "$s[format %x [expr {int(rand()*16)}]]"
|
||||
}
|
||||
return $s
|
||||
}
|
||||
|
||||
for {set i 10} {$i < 30} {incr i} {
|
||||
foreach cell $cells {
|
||||
set_property MASK "48'h[randhex 12]" $cell
|
||||
set_property PATTERN "48'h[randhex 12]" $cell
|
||||
}
|
||||
write_checkpoint -force design_${i}.dcp
|
||||
write_bitstream -force design_${i}.bit
|
||||
write_txtdata design_${i}.txt
|
||||
foreach cell $cells {
|
||||
set_property MASK "48'h[randhex 12]" $cell
|
||||
set_property PATTERN "48'h[randhex 12]" $cell
|
||||
}
|
||||
write_checkpoint -force design_${i}.dcp
|
||||
write_bitstream -force design_${i}.bit
|
||||
write_txtdata design_${i}.txt
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -21,19 +21,18 @@ write_checkpoint -force piplist.dcp
|
|||
source "$::env(XRAY_DIR)/utils/utils.tcl"
|
||||
|
||||
proc print_tile_pips {tile_type filename} {
|
||||
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
|
||||
puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
|
||||
set fp [open $filename w]
|
||||
foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set dst [get_wires -downhill -of_objects $pip]
|
||||
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
|
||||
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
|
||||
puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
|
||||
set fp [open $filename w]
|
||||
foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set dst [get_wires -downhill -of_objects $pip]
|
||||
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
|
||||
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
print_tile_pips INT_L pips_int_l.txt
|
||||
print_tile_pips INT_R pips_int_r.txt
|
||||
|
||||
|
|
|
|||
|
|
@ -2,16 +2,15 @@
|
|||
set sites [get_sites -filter {(SITE_TYPE == "SLICEL" || SITE_TYPE == "SLICEM") && (NAME =~ "*Y0" || NAME =~ "*Y50" || NAME =~ "*Y?00" || NAME =~ "*Y?50")}]
|
||||
|
||||
foreach site $sites {
|
||||
puts ""; puts ""; puts ""; puts ""; puts ""; puts ""
|
||||
puts "=========================== $site ==========================="
|
||||
puts ""; puts ""; puts ""; puts ""; puts ""; puts ""
|
||||
puts "=========================== $site ==========================="
|
||||
|
||||
set_property LOC $site [get_cells lut]
|
||||
route_design
|
||||
set_property LOC $site [get_cells lut]
|
||||
route_design
|
||||
|
||||
set_property INIT 64'h8000000000000000 [get_cells lut]
|
||||
write_bitstream -force logicframes_${site}_0.bit
|
||||
set_property INIT 64'h8000000000000000 [get_cells lut]
|
||||
write_bitstream -force logicframes_${site}_0.bit
|
||||
|
||||
set_property INIT 64'h8000000000000001 [get_cells lut]
|
||||
write_bitstream -force logicframes_${site}_1.bit
|
||||
set_property INIT 64'h8000000000000001 [get_cells lut]
|
||||
write_bitstream -force logicframes_${site}_1.bit
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,16 +1,15 @@
|
|||
|
||||
foreach tile [get_tiles] {
|
||||
foreach prop [list_property $tile] {
|
||||
puts "--tiledata-- TILEPROP $tile $prop [get_property $prop $tile]"
|
||||
}
|
||||
foreach site [get_sites -quiet -of_objects $tile] {
|
||||
puts "--tiledata-- TILESITE $tile $site"
|
||||
}
|
||||
foreach prop [list_property $tile] {
|
||||
puts "--tiledata-- TILEPROP $tile $prop [get_property $prop $tile]"
|
||||
}
|
||||
foreach site [get_sites -quiet -of_objects $tile] {
|
||||
puts "--tiledata-- TILESITE $tile $site"
|
||||
}
|
||||
}
|
||||
|
||||
foreach site [get_sites] {
|
||||
foreach prop [list_property $site] {
|
||||
puts "--tiledata-- SITEPROP $site $prop [get_property $prop $site]"
|
||||
}
|
||||
foreach prop [list_property $site] {
|
||||
puts "--tiledata-- SITEPROP $site $prop [get_property $prop $site]"
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -19,4 +19,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -23,4 +23,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -25,29 +25,28 @@ write_bitstream -force design.bit
|
|||
source ../../utils/utils.tcl
|
||||
|
||||
foreach it {
|
||||
{b11 INT_L_X12Y100/GCLK_L_B11}
|
||||
{b10 INT_L_X12Y100/GCLK_L_B10}
|
||||
{b9 INT_L_X12Y100/GCLK_L_B9}
|
||||
{b8 INT_L_X12Y100/GCLK_L_B8}
|
||||
{b7 INT_L_X12Y100/GCLK_L_B7}
|
||||
{b6 INT_L_X12Y100/GCLK_L_B6}
|
||||
{b5 INT_R_X13Y100/GCLK_B5}
|
||||
{b4 INT_R_X13Y100/GCLK_B4}
|
||||
{b3 INT_R_X13Y100/GCLK_B3}
|
||||
{b2 INT_R_X13Y100/GCLK_B2}
|
||||
{b1 INT_R_X13Y100/GCLK_B1}
|
||||
{b0 INT_R_X13Y100/GCLK_B0}
|
||||
{b11 INT_L_X12Y100/GCLK_L_B11}
|
||||
{b10 INT_L_X12Y100/GCLK_L_B10}
|
||||
{b9 INT_L_X12Y100/GCLK_L_B9}
|
||||
{b8 INT_L_X12Y100/GCLK_L_B8}
|
||||
{b7 INT_L_X12Y100/GCLK_L_B7}
|
||||
{b6 INT_L_X12Y100/GCLK_L_B6}
|
||||
{b5 INT_R_X13Y100/GCLK_B5}
|
||||
{b4 INT_R_X13Y100/GCLK_B4}
|
||||
{b3 INT_R_X13Y100/GCLK_B3}
|
||||
{b2 INT_R_X13Y100/GCLK_B2}
|
||||
{b1 INT_R_X13Y100/GCLK_B1}
|
||||
{b0 INT_R_X13Y100/GCLK_B0}
|
||||
} {
|
||||
set net [get_nets c_IBUF_BUFG]
|
||||
set_property FIXED_ROUTE {} $net
|
||||
route_design -unroute -net $net
|
||||
set net [get_nets c_IBUF_BUFG]
|
||||
set_property FIXED_ROUTE {} $net
|
||||
route_design -unroute -net $net
|
||||
|
||||
set id [lindex $it 0]
|
||||
set gclk [lindex $it 1]
|
||||
set id [lindex $it 0]
|
||||
set gclk [lindex $it 1]
|
||||
|
||||
route_via $net "$gclk"
|
||||
route_via $net "$gclk"
|
||||
|
||||
write_checkpoint -force design_$id.dcp
|
||||
write_bitstream -force design_$id.bit
|
||||
write_checkpoint -force design_$id.dcp
|
||||
write_bitstream -force design_$id.bit
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -16,30 +16,30 @@ set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
|||
source ../../utils/utils.tcl
|
||||
|
||||
proc get_rand_lut6_init {} {
|
||||
return "64'h[format %08x [expr int(rand() * 65536 * 65536)]][format %08x [expr int(rand() * 65536 * 65536)]]"
|
||||
return "64'h[format %08x [expr int(rand() * 65536 * 65536)]][format %08x [expr int(rand() * 65536 * 65536)]]"
|
||||
}
|
||||
|
||||
set i 1
|
||||
foreach site [randsample_list 100 [get_sites -of_objects [get_pblocks roi]]] {
|
||||
puts "$i/100: $site"
|
||||
incr i
|
||||
puts "$i/100: $site"
|
||||
incr i
|
||||
|
||||
create_cell -reference LUT6 LUT_${site}_ALUT
|
||||
create_cell -reference LUT6 LUT_${site}_BLUT
|
||||
create_cell -reference LUT6 LUT_${site}_CLUT
|
||||
create_cell -reference LUT6 LUT_${site}_DLUT
|
||||
create_cell -reference LUT6 LUT_${site}_ALUT
|
||||
create_cell -reference LUT6 LUT_${site}_BLUT
|
||||
create_cell -reference LUT6 LUT_${site}_CLUT
|
||||
create_cell -reference LUT6 LUT_${site}_DLUT
|
||||
|
||||
set_property -dict "LOC $site BEL A6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_ALUT]
|
||||
set_property -dict "LOC $site BEL B6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_BLUT]
|
||||
set_property -dict "LOC $site BEL C6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_CLUT]
|
||||
set_property -dict "LOC $site BEL D6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_DLUT]
|
||||
set_property -dict "LOC $site BEL A6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_ALUT]
|
||||
set_property -dict "LOC $site BEL B6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_BLUT]
|
||||
set_property -dict "LOC $site BEL C6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_CLUT]
|
||||
set_property -dict "LOC $site BEL D6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_DLUT]
|
||||
|
||||
connect_net -net [get_nets y_OBUF] -objects [get_pins "
|
||||
LUT_${site}_ALUT/I0 LUT_${site}_ALUT/I1 LUT_${site}_ALUT/I2 LUT_${site}_ALUT/I3 LUT_${site}_ALUT/I4 LUT_${site}_ALUT/I5
|
||||
LUT_${site}_BLUT/I0 LUT_${site}_BLUT/I1 LUT_${site}_BLUT/I2 LUT_${site}_BLUT/I3 LUT_${site}_BLUT/I4 LUT_${site}_BLUT/I5
|
||||
LUT_${site}_CLUT/I0 LUT_${site}_CLUT/I1 LUT_${site}_CLUT/I2 LUT_${site}_CLUT/I3 LUT_${site}_CLUT/I4 LUT_${site}_CLUT/I5
|
||||
LUT_${site}_DLUT/I0 LUT_${site}_DLUT/I1 LUT_${site}_DLUT/I2 LUT_${site}_DLUT/I3 LUT_${site}_DLUT/I4 LUT_${site}_DLUT/I5
|
||||
"]
|
||||
"]
|
||||
}
|
||||
|
||||
place_design
|
||||
|
|
@ -47,4 +47,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -30,17 +30,16 @@ write_bitstream -force design_fdre.bit
|
|||
close_project
|
||||
|
||||
foreach variant {fdse fdce fdce_inv fdpe ldce ldpe} {
|
||||
create_project -force -part $::env(XRAY_PART) design_${variant} design_${variant}
|
||||
read_verilog top_${variant}.v
|
||||
read_xdc fixed.xdc
|
||||
create_project -force -part $::env(XRAY_PART) design_${variant} design_${variant}
|
||||
read_verilog top_${variant}.v
|
||||
read_xdc fixed.xdc
|
||||
|
||||
synth_design -top top
|
||||
place_design
|
||||
route_design
|
||||
synth_design -top top
|
||||
place_design
|
||||
route_design
|
||||
|
||||
write_checkpoint -force design_${variant}.dcp
|
||||
write_bitstream -force design_${variant}.bit
|
||||
write_checkpoint -force design_${variant}.dcp
|
||||
write_bitstream -force design_${variant}.bit
|
||||
|
||||
close_project
|
||||
close_project
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -6,4 +6,3 @@ source "$::env(SRC_DIR)/template.tcl"
|
|||
set prop DRIVE
|
||||
set port [get_ports do]
|
||||
source "$::env(SRC_DIR)/sweep.tcl"
|
||||
|
||||
|
|
|
|||
|
|
@ -3,4 +3,3 @@ source "$::env(SRC_DIR)/template.tcl"
|
|||
set prop IOSTANDARD
|
||||
set port [get_ports do]
|
||||
source "$::env(SRC_DIR)/sweep.tcl"
|
||||
|
||||
|
|
|
|||
|
|
@ -12,4 +12,3 @@ foreach {val} $vals {
|
|||
write_checkpoint -force design_$val.dcp
|
||||
write_bitstream -force design_$val.bit
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -5,4 +5,3 @@ source "$::env(SRC_DIR)/template.tcl"
|
|||
set prop SLEW
|
||||
set port [get_ports do]
|
||||
source "$::env(SRC_DIR)/sweep.tcl"
|
||||
|
||||
|
|
|
|||
|
|
@ -28,4 +28,3 @@ write_checkpoint -force design.dcp
|
|||
|
||||
# set_property BITSTREAM.GENERAL.DEBUGBITSTREAM Yes [current_design]
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ foreach {val} $vals {
|
|||
puts "WARNING failed to write: $issue"
|
||||
continue
|
||||
}
|
||||
# Only write checkpoints for acceptable bitstreams
|
||||
# Only write checkpoints for acceptable bitstreams
|
||||
write_checkpoint -force design_$val.dcp
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -23,4 +23,3 @@ write_checkpoint -force design.dcp
|
|||
# set_property -dict "PACKAGE_PIN D19 IOSTANDARD LVCMOS33" $port
|
||||
# set_property PULLTYPE PULLUP $port
|
||||
# set_property PULLTYPE PULLDOWN $port
|
||||
|
||||
|
|
|
|||
|
|
@ -22,13 +22,13 @@ set_property FIXED_ROUTE {} [get_nets o_OBUF]
|
|||
route_design -unroute
|
||||
|
||||
route_via o_OBUF {
|
||||
INT_L_X12Y144/LVB_L12 INT_L_X12Y132/LVB_L12
|
||||
INT_L_X12Y144/LVB_L12 INT_L_X12Y132/LVB_L12
|
||||
|
||||
INT_L_X12Y120/SS6BEG2
|
||||
INT_L_X14Y120/NN6END3
|
||||
INT_L_X12Y120/SS6BEG2
|
||||
INT_L_X14Y120/NN6END3
|
||||
|
||||
INT_L_X14Y132/LVB_L12 INT_L_X14Y144/LVB_L12
|
||||
INT_L_X16Y144/LVB_L12 INT_L_X16Y132/LVB_L12
|
||||
INT_L_X14Y132/LVB_L12 INT_L_X14Y144/LVB_L12
|
||||
INT_L_X16Y144/LVB_L12 INT_L_X16Y132/LVB_L12
|
||||
}
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
|
@ -43,18 +43,18 @@ set_property FIXED_ROUTE {} [get_nets o_OBUF]
|
|||
route_design -unroute
|
||||
|
||||
route_via o_OBUF {
|
||||
INT_L_X12Y120/NN6END3
|
||||
INT_L_X12Y120/NN6END3
|
||||
|
||||
INT_L_X12Y132/LVB_L12 INT_L_X12Y144/LVB_L12
|
||||
INT_L_X12Y132/LVB_L12 INT_L_X12Y144/LVB_L12
|
||||
|
||||
INT_L_X14Y144/LVB_L12 INT_L_X14Y132/LVB_L12
|
||||
INT_L_X14Y144/LVB_L12 INT_L_X14Y132/LVB_L12
|
||||
|
||||
INT_L_X14Y120/SS6BEG2
|
||||
INT_L_X16Y120/NN6END3
|
||||
INT_L_X14Y120/SS6BEG2
|
||||
INT_L_X16Y120/NN6END3
|
||||
|
||||
INT_L_X16Y132/LVB_L12 INT_L_X16Y144/LVB_L12
|
||||
INT_L_X16Y132/LVB_L12 INT_L_X16Y144/LVB_L12
|
||||
|
||||
INT_L_X16Y144/EE4BEG2
|
||||
INT_L_X16Y144/EE4BEG2
|
||||
}
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
|
@ -62,4 +62,3 @@ route_via o_OBUF {
|
|||
route_design
|
||||
write_checkpoint -force design_b.dcp
|
||||
write_bitstream -force design_b.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -23,8 +23,7 @@ source ../../utils/utils.tcl
|
|||
|
||||
set fp [open "nodes_wires_list.txt" w]
|
||||
foreach node [lsort [get_nodes -of_objects [pblock_tiles roi]]] {
|
||||
set wires [lsort [get_wires -of_objects $node]]
|
||||
if {$wires != $node} {puts $fp $wires}
|
||||
set wires [lsort [get_wires -of_objects $node]]
|
||||
if {$wires != $node} {puts $fp $wires}
|
||||
}
|
||||
close $fp
|
||||
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ if {$part eq "xc7a50tfgg484-1"} {
|
|||
set pin [lindex $bank_16 $banki]
|
||||
incr banki
|
||||
set net2pin(dout[$i]) $pin
|
||||
}
|
||||
}
|
||||
} elseif {$part eq "xc7a35tcsg324-1"} {
|
||||
# Arty A7 switch, button, and LED
|
||||
if {$pincfg eq "ARTY-A7-SWBUT"} {
|
||||
|
|
@ -66,9 +66,9 @@ if {$part eq "xc7a50tfgg484-1"} {
|
|||
for {set i 0} {$i < $DOUT_N} {incr i} {
|
||||
set pin [lindex $leds $i]
|
||||
set net2pin(dout[$i]) $pin
|
||||
}
|
||||
# Arty A7 pmod
|
||||
# Disabled per above
|
||||
}
|
||||
# Arty A7 pmod
|
||||
# Disabled per above
|
||||
} elseif {$pincfg eq "ARTY-A7-PMOD"} {
|
||||
# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
|
||||
set pmod_ja "G13 B11 A11 D12 D13 B18 A18 K16"
|
||||
|
|
@ -89,7 +89,7 @@ if {$part eq "xc7a50tfgg484-1"} {
|
|||
for {set i 0} {$i < $DOUT_N} {incr i} {
|
||||
set pin [lindex $pmod_jc $i]
|
||||
set net2pin(dout[$i]) $pin
|
||||
}
|
||||
}
|
||||
} else {
|
||||
error "Unsupported config $pincfg"
|
||||
}
|
||||
|
|
@ -115,7 +115,7 @@ if {$part eq "xc7a50tfgg484-1"} {
|
|||
for {set i 0} {$i < $DOUT_N} {incr i} {
|
||||
set pin [lindex $leds $i]
|
||||
set net2pin(dout[$i]) $pin
|
||||
}
|
||||
}
|
||||
} else {
|
||||
error "Unsupported config $pincfg"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
read_verilog [lindex $argv 0]
|
||||
synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
|
||||
write_checkpoint -force [lindex $argv 1]
|
||||
|
||||
|
|
|
|||
|
|
@ -23,4 +23,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -29,4 +29,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -104,7 +104,7 @@ if {$part eq "xc7a50tfgg484-1"} {
|
|||
set pin [lindex $bank_16 $banki]
|
||||
incr banki
|
||||
set net2pin(dout[$i]) $pin
|
||||
}
|
||||
}
|
||||
} elseif {$part eq "xc7a35tcsg324-1"} {
|
||||
# Arty A7 switch, button, and LED
|
||||
if {$pincfg eq "ARTY-A7-SWBUT"} {
|
||||
|
|
@ -128,9 +128,9 @@ if {$part eq "xc7a50tfgg484-1"} {
|
|||
for {set i 0} {$i < $DOUT_N} {incr i} {
|
||||
set pin [lindex $leds $i]
|
||||
set net2pin(dout[$i]) $pin
|
||||
}
|
||||
# Arty A7 pmod
|
||||
# Disabled per above
|
||||
}
|
||||
# Arty A7 pmod
|
||||
# Disabled per above
|
||||
} elseif {$pincfg eq "ARTY-A7-PMOD"} {
|
||||
# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
|
||||
set pmod_ja "G13 B11 A11 D12 D13 B18 A18 K16"
|
||||
|
|
@ -151,7 +151,7 @@ if {$part eq "xc7a50tfgg484-1"} {
|
|||
for {set i 0} {$i < $DOUT_N} {incr i} {
|
||||
set pin [lindex $pmod_jc $i]
|
||||
set net2pin(dout[$i]) $pin
|
||||
}
|
||||
}
|
||||
} else {
|
||||
error "Unsupported config $pincfg"
|
||||
}
|
||||
|
|
@ -182,7 +182,7 @@ if {$part eq "xc7a50tfgg484-1"} {
|
|||
for {set i 0} {$i < $DOUT_N} {incr i} {
|
||||
set pin [lindex $outs $i]
|
||||
set net2pin(dout[$i]) $pin
|
||||
}
|
||||
}
|
||||
} else {
|
||||
error "Unsupported config $pincfg"
|
||||
}
|
||||
|
|
@ -268,7 +268,7 @@ proc net_bank_left {net} {
|
|||
# left
|
||||
if {[lsearch -exact $left_banks $bank] >= 0} {
|
||||
return 1
|
||||
# right
|
||||
# right
|
||||
} elseif {[lsearch -exact $right_banks $bank] >= 0} {
|
||||
return 0
|
||||
} else {
|
||||
|
|
@ -438,7 +438,7 @@ if {$fixed_xdc eq ""} {
|
|||
if {$part eq "xc7a50tfgg484-1"} {
|
||||
set node "INT_L_X1Y${y_left}/WW2BEG0"
|
||||
route_via2 "roi/dout[$i]" "$node"
|
||||
# works on 35t but not 50t
|
||||
# works on 35t but not 50t
|
||||
} elseif {$part eq "xc7a35tcsg324-1"} {
|
||||
set node "INT_L_X2Y${y_left}/SW6BEG0"
|
||||
route_via2 "roi/dout[$i]" "$node"
|
||||
|
|
@ -449,7 +449,7 @@ if {$fixed_xdc eq ""} {
|
|||
error "Routing: unsupported part $part"
|
||||
}
|
||||
set y_left [expr {$y_left + $PITCH}]
|
||||
# XXX: only care about right ports on Arty
|
||||
# XXX: only care about right ports on Arty
|
||||
} else {
|
||||
set node "INT_R_X23Y${y_right}/LH12"
|
||||
route_via2 "roi/dout[$i]" "$node"
|
||||
|
|
@ -482,4 +482,3 @@ if {$fixed_xdc eq ""} {
|
|||
write_checkpoint -force design.dcp
|
||||
#set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -1,63 +1,62 @@
|
|||
|
||||
proc tile_pip_report {fd tile_name} {
|
||||
set tile [get_tile $tile_name]
|
||||
set pips [get_pips -of_object $tile]
|
||||
set dsts [lsort -unique [get_wires -filter "TILE_NAME == $tile" -downhill -of_objects $pips]]
|
||||
set tile [get_tile $tile_name]
|
||||
set pips [get_pips -of_object $tile]
|
||||
set dsts [lsort -unique [get_wires -filter "TILE_NAME == $tile" -downhill -of_objects $pips]]
|
||||
|
||||
puts $fd ""
|
||||
puts $fd "PIP Report for tile $tile"
|
||||
puts $fd "==================================="
|
||||
puts $fd ""
|
||||
puts $fd "PIP Report for tile $tile"
|
||||
puts $fd "==================================="
|
||||
|
||||
puts $fd ""
|
||||
puts $fd "PIPs that implement 1:1 connections"
|
||||
puts $fd "-----------------------------------"
|
||||
puts $fd ""
|
||||
puts $fd "PIPs that implement 1:1 connections"
|
||||
puts $fd "-----------------------------------"
|
||||
|
||||
foreach dst $dsts {
|
||||
set dst_node [get_node -of_objects $dst]
|
||||
set dst_span [llength [get_tiles -of_objects $dst_node]]
|
||||
set pips [get_pips -filter "TILE == $tile" -uphill -of_objects $dst_node]
|
||||
if {[llength $pips] == 1} {
|
||||
puts $fd ""
|
||||
puts $fd "Destination Wire (Node, Span): $dst ($dst_node, $dst_span)"
|
||||
foreach pip $pips {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set src_node [get_node -of_objects $src]
|
||||
set src_span [llength [get_tiles -of_objects $src_node]]
|
||||
puts $fd " Source Wire (Node, Span): $src ($src_node, $src_span) via $pip"
|
||||
}
|
||||
foreach pip [get_pips -quiet -filter "TILE != $tile" -uphill -of_objects $dst_node] {
|
||||
puts $fd " Outside Source PIP: $pip"
|
||||
}
|
||||
}
|
||||
}
|
||||
foreach dst $dsts {
|
||||
set dst_node [get_node -of_objects $dst]
|
||||
set dst_span [llength [get_tiles -of_objects $dst_node]]
|
||||
set pips [get_pips -filter "TILE == $tile" -uphill -of_objects $dst_node]
|
||||
if {[llength $pips] == 1} {
|
||||
puts $fd ""
|
||||
puts $fd "Destination Wire (Node, Span): $dst ($dst_node, $dst_span)"
|
||||
foreach pip $pips {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set src_node [get_node -of_objects $src]
|
||||
set src_span [llength [get_tiles -of_objects $src_node]]
|
||||
puts $fd " Source Wire (Node, Span): $src ($src_node, $src_span) via $pip"
|
||||
}
|
||||
foreach pip [get_pips -quiet -filter "TILE != $tile" -uphill -of_objects $dst_node] {
|
||||
puts $fd " Outside Source PIP: $pip"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
puts $fd ""
|
||||
puts $fd "PIPs that implement N:1 connections"
|
||||
puts $fd "-----------------------------------"
|
||||
puts $fd ""
|
||||
puts $fd "PIPs that implement N:1 connections"
|
||||
puts $fd "-----------------------------------"
|
||||
|
||||
foreach dst $dsts {
|
||||
set dst_node [get_node -of_objects $dst]
|
||||
set dst_span [llength [get_tiles -of_objects $dst_node]]
|
||||
set pips [get_pips -filter "TILE == $tile" -uphill -of_objects $dst_node]
|
||||
if {[llength $pips] != 1} {
|
||||
puts $fd ""
|
||||
puts $fd "Destination Wire (Node, Span): $dst ($dst_node, $dst_span)"
|
||||
foreach pip $pips {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set src_node [get_node -of_objects $src]
|
||||
set src_span [llength [get_tiles -of_objects $src_node]]
|
||||
puts $fd " Source Wire (Node, Span): $src ($src_node, $src_span) via $pip"
|
||||
}
|
||||
foreach pip [get_pips -quiet -filter "TILE != $tile" -uphill -of_objects $dst_node] {
|
||||
puts $fd " Outside Source PIP: $pip"
|
||||
}
|
||||
}
|
||||
}
|
||||
foreach dst $dsts {
|
||||
set dst_node [get_node -of_objects $dst]
|
||||
set dst_span [llength [get_tiles -of_objects $dst_node]]
|
||||
set pips [get_pips -filter "TILE == $tile" -uphill -of_objects $dst_node]
|
||||
if {[llength $pips] != 1} {
|
||||
puts $fd ""
|
||||
puts $fd "Destination Wire (Node, Span): $dst ($dst_node, $dst_span)"
|
||||
foreach pip $pips {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set src_node [get_node -of_objects $src]
|
||||
set src_span [llength [get_tiles -of_objects $src_node]]
|
||||
puts $fd " Source Wire (Node, Span): $src ($src_node, $src_span) via $pip"
|
||||
}
|
||||
foreach pip [get_pips -quiet -filter "TILE != $tile" -uphill -of_objects $dst_node] {
|
||||
puts $fd " Outside Source PIP: $pip"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
puts $fd ""
|
||||
puts $fd ""
|
||||
puts $fd ""
|
||||
puts $fd ""
|
||||
}
|
||||
|
||||
tile_pip_report [open "pips_clbll.txt" w] CLBLL_L_X12Y119
|
||||
tile_pip_report [open "pips_int.txt" w] INT_L_X12Y119
|
||||
|
||||
|
|
|
|||
|
|
@ -10,4 +10,3 @@ route_design
|
|||
|
||||
write_checkpoint -force routes.dcp
|
||||
write_bitstream -force routes.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -23,4 +23,3 @@ write_bitstream -force design.bit
|
|||
source ../../utils/utils.tcl
|
||||
source pips.tcl
|
||||
source routes.tcl
|
||||
|
||||
|
|
|
|||
|
|
@ -22,20 +22,19 @@ write_bitstream -force design.bit
|
|||
source ../../utils/utils.tcl
|
||||
|
||||
proc print_tile_info {tile} {
|
||||
puts "Dumping wires and PIPs for tile $tile."
|
||||
set fp [open "wires_${tile}.txt" w]
|
||||
foreach wire [lsort [get_wires -of_objects [get_tiles $tile]]] {
|
||||
puts $fp [regsub {.*/} $wire ""]
|
||||
}
|
||||
close $fp
|
||||
set fp [open "pips_${tile}.txt" w]
|
||||
foreach wire [lsort [get_pips -of_objects [get_tiles $tile]]] {
|
||||
puts $fp [regsub {.*/} $wire ""]
|
||||
}
|
||||
close $fp
|
||||
puts "Dumping wires and PIPs for tile $tile."
|
||||
set fp [open "wires_${tile}.txt" w]
|
||||
foreach wire [lsort [get_wires -of_objects [get_tiles $tile]]] {
|
||||
puts $fp [regsub {.*/} $wire ""]
|
||||
}
|
||||
close $fp
|
||||
set fp [open "pips_${tile}.txt" w]
|
||||
foreach wire [lsort [get_pips -of_objects [get_tiles $tile]]] {
|
||||
puts $fp [regsub {.*/} $wire ""]
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
foreach tile [lsort [get_tiles]] {
|
||||
print_tile_info $tile
|
||||
print_tile_info $tile
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -22,4 +22,3 @@ route_design
|
|||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -28,4 +28,6 @@ export XRAY_FASM2FRAMES="python3 ${XRAY_UTILS_DIR}/fasm2frames.py"
|
|||
export XRAY_BITTOOL="${XRAY_TOOLS_DIR}/bittool"
|
||||
export XRAY_BLOCKWIDTH="python3 ${XRAY_UTILS_DIR}/blockwidth.py"
|
||||
export XRAY_PARSEDB="python3 ${XRAY_UTILS_DIR}/parsedb.py"
|
||||
export XRAY_REFORMAT_TCL="${XRAY_UTILS_DIR}/reformat.tcl"
|
||||
export XRAY_TCL_REFORMAT="${XRAY_UTILS_DIR}/tcl-reformat.sh"
|
||||
|
||||
|
|
|
|||
127
utils/utils.tcl
127
utils/utils.tcl
|
|
@ -5,38 +5,38 @@ proc route_via {net nodes} {
|
|||
# nodes: list of node or wires strings?
|
||||
# Returns 1 on success (previously would silently failed with antenna nets)
|
||||
|
||||
set net [get_nets $net]
|
||||
# fixed_route: list of nodes in the full route
|
||||
# Begins at implicit node
|
||||
set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]]
|
||||
# Implicit end node. Route it at the end
|
||||
lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]]
|
||||
set net [get_nets $net]
|
||||
# fixed_route: list of nodes in the full route
|
||||
# Begins at implicit node
|
||||
set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]]
|
||||
# Implicit end node. Route it at the end
|
||||
lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]]
|
||||
|
||||
puts ""
|
||||
puts "Routing net $net:"
|
||||
puts ""
|
||||
puts "Routing net $net:"
|
||||
|
||||
foreach to_node $nodes {
|
||||
# convert wire string to node object
|
||||
set to_node [get_nodes -of_objects [get_wires $to_node]]
|
||||
# Start at the last point
|
||||
set from_node [lindex $fixed_route end]
|
||||
# Make vivado do the hard work
|
||||
set route [find_routing_path -quiet -from $from_node -to $to_node]
|
||||
# TODO: check for this
|
||||
if {$route == ""} {
|
||||
# This can also happen if you try to route to a node already in the route
|
||||
if { [ lsearch $route $to_node ] >= 0 } {
|
||||
puts "WARNING: route_via loop. $to_node is already in the path, ignoring"
|
||||
} else {
|
||||
puts " $from_node -> $to_node: no route found - assuming direct PIP"
|
||||
lappend fixed_route $to_node
|
||||
}
|
||||
} {
|
||||
puts " $from_node -> $to_node: $route"
|
||||
set fixed_route [concat $fixed_route [lrange $route 1 end]]
|
||||
}
|
||||
set_property -quiet FIXED_ROUTE $fixed_route $net
|
||||
}
|
||||
foreach to_node $nodes {
|
||||
# convert wire string to node object
|
||||
set to_node [get_nodes -of_objects [get_wires $to_node]]
|
||||
# Start at the last point
|
||||
set from_node [lindex $fixed_route end]
|
||||
# Make vivado do the hard work
|
||||
set route [find_routing_path -quiet -from $from_node -to $to_node]
|
||||
# TODO: check for this
|
||||
if {$route == ""} {
|
||||
# This can also happen if you try to route to a node already in the route
|
||||
if { [ lsearch $route $to_node ] >= 0 } {
|
||||
puts "WARNING: route_via loop. $to_node is already in the path, ignoring"
|
||||
} else {
|
||||
puts " $from_node -> $to_node: no route found - assuming direct PIP"
|
||||
lappend fixed_route $to_node
|
||||
}
|
||||
} {
|
||||
puts " $from_node -> $to_node: $route"
|
||||
set fixed_route [concat $fixed_route [lrange $route 1 end]]
|
||||
}
|
||||
set_property -quiet FIXED_ROUTE $fixed_route $net
|
||||
}
|
||||
|
||||
# Earlier check should catch this now
|
||||
set status [get_property ROUTE_STATUS $net]
|
||||
|
|
@ -46,64 +46,63 @@ proc route_via {net nodes} {
|
|||
# return 0
|
||||
}
|
||||
|
||||
set_property -quiet FIXED_ROUTE $fixed_route $net
|
||||
puts ""
|
||||
set_property -quiet FIXED_ROUTE $fixed_route $net
|
||||
puts ""
|
||||
return 1
|
||||
}
|
||||
|
||||
proc tile_wire_pairs {tile1 tile2} {
|
||||
set tile1 [get_tiles $tile1]
|
||||
set tile2 [get_tiles $tile2]
|
||||
set tile1 [get_tiles $tile1]
|
||||
set tile2 [get_tiles $tile2]
|
||||
|
||||
foreach wire1 [lsort [get_wires -of_objects $tile1]] {
|
||||
set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]]
|
||||
if {$wire2 != ""} {puts "$wire1 $wire2"}
|
||||
}
|
||||
foreach wire1 [lsort [get_wires -of_objects $tile1]] {
|
||||
set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]]
|
||||
if {$wire2 != ""} {puts "$wire1 $wire2"}
|
||||
}
|
||||
}
|
||||
|
||||
proc randsample_list {num lst} {
|
||||
set rlst {}
|
||||
for {set i 0} {$i<$num} {incr i} {
|
||||
set j [expr {int(rand()*[llength $lst])}]
|
||||
lappend rlst [lindex $lst $j]
|
||||
set lst [lreplace $lst $j $j]
|
||||
}
|
||||
return $rlst
|
||||
set rlst {}
|
||||
for {set i 0} {$i<$num} {incr i} {
|
||||
set j [expr {int(rand()*[llength $lst])}]
|
||||
lappend rlst [lindex $lst $j]
|
||||
set lst [lreplace $lst $j $j]
|
||||
}
|
||||
return $rlst
|
||||
}
|
||||
|
||||
proc randplace_pblock {num pblock} {
|
||||
set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]]
|
||||
set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]]
|
||||
for {set i 0} {$i<$num} {incr i} {
|
||||
set site [lindex $sites $i]
|
||||
set cell [lindex $cells $i]
|
||||
set_property LOC $site $cell
|
||||
}
|
||||
set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]]
|
||||
set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]]
|
||||
for {set i 0} {$i<$num} {incr i} {
|
||||
set site [lindex $sites $i]
|
||||
set cell [lindex $cells $i]
|
||||
set_property LOC $site $cell
|
||||
}
|
||||
}
|
||||
|
||||
proc roi_tiles {} {
|
||||
return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \
|
||||
GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \
|
||||
GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \
|
||||
GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"]
|
||||
GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"]
|
||||
}
|
||||
|
||||
proc pblock_tiles {pblock} {
|
||||
set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]]
|
||||
set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]]
|
||||
return [get_tiles "$clb_tiles $int_tiles"]
|
||||
set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]]
|
||||
set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]]
|
||||
return [get_tiles "$clb_tiles $int_tiles"]
|
||||
}
|
||||
|
||||
proc lintersect {lst1 lst2} {
|
||||
set rlst {}
|
||||
foreach el $lst1 {
|
||||
set idx [lsearch $lst2 $el]
|
||||
if {$idx >= 0} {lappend rlst $el}
|
||||
}
|
||||
return $rlst
|
||||
set rlst {}
|
||||
foreach el $lst1 {
|
||||
set idx [lsearch $lst2 $el]
|
||||
if {$idx >= 0} {lappend rlst $el}
|
||||
}
|
||||
return $rlst
|
||||
}
|
||||
|
||||
proc putl {lst} {
|
||||
foreach line $lst {puts $line}
|
||||
foreach line $lst {puts $line}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue