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Merge pull request #1119 from antmicro/litex_litedram 

minitests: Add test for Litex DRAM memory interface
This commit is contained in:
litghost 2019-10-30 10:40:01 -07:00 committed by GitHub
parent 78cf96be0f 43fe925ff3
commit daf284151c
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minitests/litex_litedram/README.md Normal file
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# LiteX Litex BaseSoC + LiteDRAM minitest
This folder contains a minitest for the Litex memory controller (LiteDRAM).
For checking the memory interface we leverage the fact that the BIOS firmware performs a memory test at startup.
The SoC is a Basic LiteX SoC configuration for the Arty board with the VexRiscv core.
## Synthesis+implementation
There are two variants: for Vivado only flow and for Yosys+Vivado flow. In order to run one of them enter the specific directory and run `make`.
Once the bitstream is generated and loaded to the board, we should see the test result on the terminal connected to one of the serial ports.

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minitests/litex_litedram/src.vivado/ExtractFrames.py Executable file
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#!/bin/python
'''
Extract the frames from the output of the prjxray bitread tool.
'''
import sys
import re
def extract_frames(args):
""" Extract the frame addresses and the corresponding content """
frames_dict = dict()
with open(args[1], 'r') as f:
parse_frames = False
for cnt, line in enumerate(f):
if line.startswith("\n"):
parse_frames = False
continue
line = line.strip()
if not parse_frames and not line.startswith("Frame"):
continue
if line.startswith("Frame"):
match = re.match("Frame 0x([0-9a-fA-F]+) ", line)
frame_addr = "0x" + match.group(1).upper()
parse_frames = True
frames_dict[frame_addr] = list()
continue
for frame in line.split():
frames_dict[frame_addr].append("0x" + frame.upper())
for addr, words in frames_dict.items():
print("{addr} {words}".format(addr=addr, words=",".join(words)))
if __name__ == "__main__":
extract_frames(sys.argv)

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minitests/litex_litedram/src.vivado/Makefile Normal file
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export XRAY_PART = xc7a35tcsg324-1
export XRAY_PART_YAML = $(XRAY_DATABASE_DIR)/$(XRAY_DATABASE)/$(XRAY_PART).yaml
SOURCES = verilog/mem.init verilog/mem_1.init verilog/top.v verilog/VexRiscv.v
all: top.f2b.bit
clean:
@rm -f *.bit
@rm -f *.bin
@rm -f *.bits
@rm -f *.fasm
@rm -f *.frames*
@rm -f *.log
@rm -rf build
.PHONY: all clean
top.bit: $(VIVADO) $(SOURCES) top.xdc top.tcl
mkdir -p build
cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
cp build/*.bit ./
top.fasm: top.bit
$(XRAY_BIT2FASM) --verbose $< > $@ \
|| (rm -f top.fasm && exit 1)
top.bits: top.bit
$(XRAY_BITREAD) -part_file $(XRAY_PART_YAML) -o top.bits -z -y top.bit
segprint.log: top.bits
$(XRAY_SEGPRINT) -z -D -b top.bits > segprint.log
top.frames: top.fasm
$(XRAY_FASM2FRAMES) $< $@
top.bitread.frames: top.bit
$(XRAY_DIR)/build/tools/bitread --part_file $(XRAY_PART_YAML) $< > top.frames.bitread
python3 ./ExtractFrames.py top.frames.bitread > $@
top.f2b.bit: top.frames
$(XRAY_DIR)/build/tools/xc7frames2bit --output_file $@ --part_name $(XRAY_PART) --part_file $(XRAY_PART_YAML) --frm_file $<
top.f2b.bitread.bit: top.bitread.frames
$(XRAY_DIR)/build/tools/xc7frames2bit --output_file $@ --part_name $(XRAY_PART) --part_file $(XRAY_PART_YAML) --frm_file $<
program: top.f2b.bit
xc3sprog -c nexys4 top.f2b.bit

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minitests/litex_litedram/src.vivado/top.tcl Normal file
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create_project -force -name top -part $::env(XRAY_PART)
set_msg_config -id {Common 17-55} -new_severity {Warning}
read_verilog ../verilog/VexRiscv.v
read_verilog ../verilog/top.v
read_xdc ../top.xdc
synth_design -directive default -top top -part $::env(XRAY_PART)
report_timing_summary -file top_timing_synth.rpt
report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
report_utilization -file top_utilization_synth.rpt
opt_design -directive default
place_design -directive default
report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
report_utilization -file top_utilization_place.rpt
report_io -file top_io.rpt
report_control_sets -verbose -file top_control_sets.rpt
report_clock_utilization -file top_clock_utilization.rpt
route_design -directive default
phys_opt_design -directive default
report_timing_summary -no_header -no_detailed_paths
write_checkpoint -force top_route.dcp
report_route_status -file top_route_status.rpt
report_drc -file top_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
report_power -file top_power.rpt
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
write_bitstream -force top.bit
write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
quit

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## serial:0.tx
set_property LOC D10 [get_ports serial_tx]
set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
## serial:0.rx
set_property LOC A9 [get_ports serial_rx]
set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
## cpu_reset:0
set_property LOC C2 [get_ports cpu_reset]
set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
## clk100:0
set_property LOC E3 [get_ports clk100]
set_property IOSTANDARD LVCMOS33 [get_ports clk100]
## eth_ref_clk:0
set_property LOC G18 [get_ports eth_ref_clk]
set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk]
## ddram:0.a
set_property LOC R2 [get_ports ddram_a[0]]
set_property SLEW FAST [get_ports ddram_a[0]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]]
## ddram:0.a
set_property LOC M6 [get_ports ddram_a[1]]
set_property SLEW FAST [get_ports ddram_a[1]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]]
## ddram:0.a
set_property LOC N4 [get_ports ddram_a[2]]
set_property SLEW FAST [get_ports ddram_a[2]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]]
## ddram:0.a
set_property LOC T1 [get_ports ddram_a[3]]
set_property SLEW FAST [get_ports ddram_a[3]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]]
## ddram:0.a
set_property LOC N6 [get_ports ddram_a[4]]
set_property SLEW FAST [get_ports ddram_a[4]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]]
## ddram:0.a
set_property LOC R7 [get_ports ddram_a[5]]
set_property SLEW FAST [get_ports ddram_a[5]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]]
## ddram:0.a
set_property LOC V6 [get_ports ddram_a[6]]
set_property SLEW FAST [get_ports ddram_a[6]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]]
## ddram:0.a
set_property LOC U7 [get_ports ddram_a[7]]
set_property SLEW FAST [get_ports ddram_a[7]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]]
## ddram:0.a
set_property LOC R8 [get_ports ddram_a[8]]
set_property SLEW FAST [get_ports ddram_a[8]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]]
## ddram:0.a
set_property LOC V7 [get_ports ddram_a[9]]
set_property SLEW FAST [get_ports ddram_a[9]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]]
## ddram:0.a
set_property LOC R6 [get_ports ddram_a[10]]
set_property SLEW FAST [get_ports ddram_a[10]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]]
## ddram:0.a
set_property LOC U6 [get_ports ddram_a[11]]
set_property SLEW FAST [get_ports ddram_a[11]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]]
## ddram:0.a
set_property LOC T6 [get_ports ddram_a[12]]
set_property SLEW FAST [get_ports ddram_a[12]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]]
## ddram:0.a
set_property LOC T8 [get_ports ddram_a[13]]
set_property SLEW FAST [get_ports ddram_a[13]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]]
## ddram:0.ba
set_property LOC R1 [get_ports ddram_ba[0]]
set_property SLEW FAST [get_ports ddram_ba[0]]
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]]
## ddram:0.ba
set_property LOC P4 [get_ports ddram_ba[1]]
set_property SLEW FAST [get_ports ddram_ba[1]]
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]]
## ddram:0.ba
set_property LOC P2 [get_ports ddram_ba[2]]
set_property SLEW FAST [get_ports ddram_ba[2]]
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]]
## ddram:0.ras_n
set_property LOC P3 [get_ports ddram_ras_n]
set_property SLEW FAST [get_ports ddram_ras_n]
set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
## ddram:0.cas_n
set_property LOC M4 [get_ports ddram_cas_n]
set_property SLEW FAST [get_ports ddram_cas_n]
set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
## ddram:0.we_n
set_property LOC P5 [get_ports ddram_we_n]
set_property SLEW FAST [get_ports ddram_we_n]
set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
## ddram:0.cs_n
set_property LOC U8 [get_ports ddram_cs_n]
set_property SLEW FAST [get_ports ddram_cs_n]
set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
## ddram:0.dm
set_property LOC L1 [get_ports ddram_dm[0]]
set_property SLEW FAST [get_ports ddram_dm[0]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]]
## ddram:0.dm
set_property LOC U1 [get_ports ddram_dm[1]]
set_property SLEW FAST [get_ports ddram_dm[1]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]]
## ddram:0.dq
set_property LOC K5 [get_ports ddram_dq[0]]
set_property SLEW FAST [get_ports ddram_dq[0]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
## ddram:0.dq
set_property LOC L3 [get_ports ddram_dq[1]]
set_property SLEW FAST [get_ports ddram_dq[1]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
## ddram:0.dq
set_property LOC K3 [get_ports ddram_dq[2]]
set_property SLEW FAST [get_ports ddram_dq[2]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
## ddram:0.dq
set_property LOC L6 [get_ports ddram_dq[3]]
set_property SLEW FAST [get_ports ddram_dq[3]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
## ddram:0.dq
set_property LOC M3 [get_ports ddram_dq[4]]
set_property SLEW FAST [get_ports ddram_dq[4]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
## ddram:0.dq
set_property LOC M1 [get_ports ddram_dq[5]]
set_property SLEW FAST [get_ports ddram_dq[5]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
## ddram:0.dq
set_property LOC L4 [get_ports ddram_dq[6]]
set_property SLEW FAST [get_ports ddram_dq[6]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
## ddram:0.dq
set_property LOC M2 [get_ports ddram_dq[7]]
set_property SLEW FAST [get_ports ddram_dq[7]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
## ddram:0.dq
set_property LOC V4 [get_ports ddram_dq[8]]
set_property SLEW FAST [get_ports ddram_dq[8]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
## ddram:0.dq
set_property LOC T5 [get_ports ddram_dq[9]]
set_property SLEW FAST [get_ports ddram_dq[9]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
## ddram:0.dq
set_property LOC U4 [get_ports ddram_dq[10]]
set_property SLEW FAST [get_ports ddram_dq[10]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
## ddram:0.dq
set_property LOC V5 [get_ports ddram_dq[11]]
set_property SLEW FAST [get_ports ddram_dq[11]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
## ddram:0.dq
set_property LOC V1 [get_ports ddram_dq[12]]
set_property SLEW FAST [get_ports ddram_dq[12]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
## ddram:0.dq
set_property LOC T3 [get_ports ddram_dq[13]]
set_property SLEW FAST [get_ports ddram_dq[13]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
## ddram:0.dq
set_property LOC U3 [get_ports ddram_dq[14]]
set_property SLEW FAST [get_ports ddram_dq[14]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
## ddram:0.dq
set_property LOC R3 [get_ports ddram_dq[15]]
set_property SLEW FAST [get_ports ddram_dq[15]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
## ddram:0.dqs_p
set_property LOC N2 [get_ports ddram_dqs_p[0]]
set_property SLEW FAST [get_ports ddram_dqs_p[0]]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]]
## ddram:0.dqs_p
set_property LOC U2 [get_ports ddram_dqs_p[1]]
set_property SLEW FAST [get_ports ddram_dqs_p[1]]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]]
## ddram:0.dqs_n
set_property LOC N1 [get_ports ddram_dqs_n[0]]
set_property SLEW FAST [get_ports ddram_dqs_n[0]]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]]
## ddram:0.dqs_n
set_property LOC V2 [get_ports ddram_dqs_n[1]]
set_property SLEW FAST [get_ports ddram_dqs_n[1]]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]]
## ddram:0.clk_p
set_property LOC U9 [get_ports ddram_clk_p]
set_property SLEW FAST [get_ports ddram_clk_p]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
## ddram:0.clk_n
set_property LOC V9 [get_ports ddram_clk_n]
set_property SLEW FAST [get_ports ddram_clk_n]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
## ddram:0.cke
set_property LOC N5 [get_ports ddram_cke]
set_property SLEW FAST [get_ports ddram_cke]
set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
## ddram:0.odt
set_property LOC R5 [get_ports ddram_odt]
set_property SLEW FAST [get_ports ddram_odt]
set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
## ddram:0.reset_n
set_property LOC K6 [get_ports ddram_reset_n]
set_property SLEW FAST [get_ports ddram_reset_n]
set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
create_clock -name clk100 -period 10.0 [get_nets clk100]
set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]

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minitests/litex_litedram/src.yosys/ExtractFrames.py Executable file
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#!/bin/python
'''
Extract the frames from the output of the prjxray bitread tool.
'''
import sys
import re
def extract_frames(args):
""" Extract the frame addresses and the corresponding content """
frames_dict = dict()
with open(args[1], 'r') as f:
parse_frames = False
for cnt, line in enumerate(f):
if line.startswith("\n"):
parse_frames = False
continue
line = line.strip()
if not parse_frames and not line.startswith("Frame"):
continue
if line.startswith("Frame"):
match = re.match("Frame 0x([0-9a-fA-F]+) ", line)
frame_addr = "0x" + match.group(1).upper()
parse_frames = True
frames_dict[frame_addr] = list()
continue
for frame in line.split():
frames_dict[frame_addr].append("0x" + frame.upper())
for addr, words in frames_dict.items():
print("{addr} {words}".format(addr=addr, words=",".join(words)))
if __name__ == "__main__":
extract_frames(sys.argv)

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export XRAY_PART = xc7a35tcsg324-1
export XRAY_PART_YAML = $(XRAY_DATABASE_DIR)/$(XRAY_DATABASE)/$(XRAY_PART).yaml
YOSYS = $(XRAY_DIR)/third_party/yosys/yosys
SOURCES = mem.init mem_1.init verilog/top.v verilog/VexRiscv.v
all: top.f2b.bit
clean:
@rm -f *.bit
@rm -f *.bin
@rm -f *.bits
@rm -f *.fasm
@rm -f *.frames*
@rm -f *.log
@rm -rf build
.PHONY: all clean
$(YOSYS):
cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc)
top.edif: $(YOSYS) synth.ys $(SOURCES)
$(YOSYS) -s synth.ys -l yosys.log
top.bit: $(VIVADO) $(SOURCES) top.xdc top.tcl
mkdir -p build
cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
python3 $(XRAY_DIR)/minitests/timing/clean_json5.py < build/iobuf_report.json5 > build/iobuf_report.json
cp build/*.bit ./
top.fasm: top.bit
$(XRAY_BIT2FASM) --verbose $< > $@ \
|| (rm -f top.fasm && exit 1)
top.bits: top.bit
$(XRAY_BITREAD) -part_file $(XRAY_PART_YAML) -o top.bits -z -y top.bit
segprint.log: top.bits
$(XRAY_SEGPRINT) -z -D -b top.bits > segprint.log
top.frames: top.fasm
$(XRAY_FASM2FRAMES) $< $@
top.bitread.frames: top.bit
$(XRAY_DIR)/build/tools/bitread --part_file $(XRAY_PART_YAML) $< > top.frames.bitread
python3 ./ExtractFrames.py top.frames.bitread > $@
top.f2b.bit: top.frames
$(XRAY_DIR)/build/tools/xc7frames2bit --output_file $@ --part_name $(XRAY_PART) --part_file $(XRAY_PART_YAML) --frm_file $<
top.f2b.bitread.bit: top.bitread.frames
$(XRAY_DIR)/build/tools/xc7frames2bit --output_file $@ --part_name $(XRAY_PART) --part_file $(XRAY_PART_YAML) --frm_file $<
program: top.f2b.bit
xc3sprog -c nexys4 top.f2b.bit

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read_verilog ./verilog/top.v
read_verilog ./verilog/VexRiscv.v
synth_xilinx -edif top.edif

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proc write_iobuf_report {filename} {
set fp [open $filename w]
puts $fp "{ \"tiles\": \["
foreach port [get_ports] {
set net [get_nets -of $port]
if { $net == "" } {
continue
}
set cell [get_cells -of $net]
set site [get_sites -of $cell]
set tile [get_tiles -of $site]
puts $fp "{"
puts $fp "\"port\": \"$port\","
puts $fp "\"pad_wire\": \"$net\","
puts $fp "\"cell\": \"$cell\","
puts $fp "\"site\": \"$site\","
puts $fp "\"tile\": \"$tile\","
puts $fp "\"type\": \"[get_property REF_NAME $cell]\","
puts $fp "\"IOSTANDARD\": \"\\\"[get_property IOSTANDARD $cell]\\\"\","
puts $fp "\"PULLTYPE\": \"\\\"[get_property PULLTYPE $cell]\\\"\","
puts $fp "\"DRIVE\": \"[get_property DRIVE $cell]\","
puts $fp "\"SLEW\": \"\\\"[get_property SLEW $cell]\\\"\","
puts $fp "},"
}
puts $fp "\]}"
close $fp
}
create_project -force -name top -part $::env(XRAY_PART)
read_xdc ../top.xdc
read_edif ../top.edif
link_design -top top -part $::env(XRAY_PART)
report_timing_summary -file top_timing_synth.rpt
report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
report_utilization -file top_utilization_synth.rpt
opt_design
place_design
report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
report_utilization -file top_utilization_place.rpt
report_io -file top_io.rpt
report_control_sets -verbose -file top_control_sets.rpt
report_clock_utilization -file top_clock_utilization.rpt
route_design
phys_opt_design
report_timing_summary -no_header -no_detailed_paths
write_checkpoint -force top_route.dcp
report_route_status -file top_route_status.rpt
report_drc -file top_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
report_power -file top_power.rpt
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
write_bitstream -force top.bit
write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
write_iobuf_report iobuf_report.json5
quit

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## serial:0.tx
set_property LOC D10 [get_ports serial_tx]
set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
## serial:0.rx
set_property LOC A9 [get_ports serial_rx]
set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
## cpu_reset:0
set_property LOC C2 [get_ports cpu_reset]
set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
## clk100:0
set_property LOC E3 [get_ports clk100]
set_property IOSTANDARD LVCMOS33 [get_ports clk100]
## eth_ref_clk:0
set_property LOC G18 [get_ports eth_ref_clk]
set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk]
## ddram:0.a
set_property LOC R2 [get_ports ddram_a[0]]
set_property SLEW FAST [get_ports ddram_a[0]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]]
## ddram:0.a
set_property LOC M6 [get_ports ddram_a[1]]
set_property SLEW FAST [get_ports ddram_a[1]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]]
## ddram:0.a
set_property LOC N4 [get_ports ddram_a[2]]
set_property SLEW FAST [get_ports ddram_a[2]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]]
## ddram:0.a
set_property LOC T1 [get_ports ddram_a[3]]
set_property SLEW FAST [get_ports ddram_a[3]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]]
## ddram:0.a
set_property LOC N6 [get_ports ddram_a[4]]
set_property SLEW FAST [get_ports ddram_a[4]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]]
## ddram:0.a
set_property LOC R7 [get_ports ddram_a[5]]
set_property SLEW FAST [get_ports ddram_a[5]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]]
## ddram:0.a
set_property LOC V6 [get_ports ddram_a[6]]
set_property SLEW FAST [get_ports ddram_a[6]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]]
## ddram:0.a
set_property LOC U7 [get_ports ddram_a[7]]
set_property SLEW FAST [get_ports ddram_a[7]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]]
## ddram:0.a
set_property LOC R8 [get_ports ddram_a[8]]
set_property SLEW FAST [get_ports ddram_a[8]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]]
## ddram:0.a
set_property LOC V7 [get_ports ddram_a[9]]
set_property SLEW FAST [get_ports ddram_a[9]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]]
## ddram:0.a
set_property LOC R6 [get_ports ddram_a[10]]
set_property SLEW FAST [get_ports ddram_a[10]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]]
## ddram:0.a
set_property LOC U6 [get_ports ddram_a[11]]
set_property SLEW FAST [get_ports ddram_a[11]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]]
## ddram:0.a
set_property LOC T6 [get_ports ddram_a[12]]
set_property SLEW FAST [get_ports ddram_a[12]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]]
## ddram:0.a
set_property LOC T8 [get_ports ddram_a[13]]
set_property SLEW FAST [get_ports ddram_a[13]]
set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]]
## ddram:0.ba
set_property LOC R1 [get_ports ddram_ba[0]]
set_property SLEW FAST [get_ports ddram_ba[0]]
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]]
## ddram:0.ba
set_property LOC P4 [get_ports ddram_ba[1]]
set_property SLEW FAST [get_ports ddram_ba[1]]
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]]
## ddram:0.ba
set_property LOC P2 [get_ports ddram_ba[2]]
set_property SLEW FAST [get_ports ddram_ba[2]]
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]]
## ddram:0.ras_n
set_property LOC P3 [get_ports ddram_ras_n]
set_property SLEW FAST [get_ports ddram_ras_n]
set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
## ddram:0.cas_n
set_property LOC M4 [get_ports ddram_cas_n]
set_property SLEW FAST [get_ports ddram_cas_n]
set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
## ddram:0.we_n
set_property LOC P5 [get_ports ddram_we_n]
set_property SLEW FAST [get_ports ddram_we_n]
set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
## ddram:0.cs_n
set_property LOC U8 [get_ports ddram_cs_n]
set_property SLEW FAST [get_ports ddram_cs_n]
set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
## ddram:0.dm
set_property LOC L1 [get_ports ddram_dm[0]]
set_property SLEW FAST [get_ports ddram_dm[0]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]]
## ddram:0.dm
set_property LOC U1 [get_ports ddram_dm[1]]
set_property SLEW FAST [get_ports ddram_dm[1]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]]
## ddram:0.dq
set_property LOC K5 [get_ports ddram_dq[0]]
set_property SLEW FAST [get_ports ddram_dq[0]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
## ddram:0.dq
set_property LOC L3 [get_ports ddram_dq[1]]
set_property SLEW FAST [get_ports ddram_dq[1]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
## ddram:0.dq
set_property LOC K3 [get_ports ddram_dq[2]]
set_property SLEW FAST [get_ports ddram_dq[2]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
## ddram:0.dq
set_property LOC L6 [get_ports ddram_dq[3]]
set_property SLEW FAST [get_ports ddram_dq[3]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
## ddram:0.dq
set_property LOC M3 [get_ports ddram_dq[4]]
set_property SLEW FAST [get_ports ddram_dq[4]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
## ddram:0.dq
set_property LOC M1 [get_ports ddram_dq[5]]
set_property SLEW FAST [get_ports ddram_dq[5]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
## ddram:0.dq
set_property LOC L4 [get_ports ddram_dq[6]]
set_property SLEW FAST [get_ports ddram_dq[6]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
## ddram:0.dq
set_property LOC M2 [get_ports ddram_dq[7]]
set_property SLEW FAST [get_ports ddram_dq[7]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
## ddram:0.dq
set_property LOC V4 [get_ports ddram_dq[8]]
set_property SLEW FAST [get_ports ddram_dq[8]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
## ddram:0.dq
set_property LOC T5 [get_ports ddram_dq[9]]
set_property SLEW FAST [get_ports ddram_dq[9]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
## ddram:0.dq
set_property LOC U4 [get_ports ddram_dq[10]]
set_property SLEW FAST [get_ports ddram_dq[10]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
## ddram:0.dq
set_property LOC V5 [get_ports ddram_dq[11]]
set_property SLEW FAST [get_ports ddram_dq[11]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
## ddram:0.dq
set_property LOC V1 [get_ports ddram_dq[12]]
set_property SLEW FAST [get_ports ddram_dq[12]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
## ddram:0.dq
set_property LOC T3 [get_ports ddram_dq[13]]
set_property SLEW FAST [get_ports ddram_dq[13]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
## ddram:0.dq
set_property LOC U3 [get_ports ddram_dq[14]]
set_property SLEW FAST [get_ports ddram_dq[14]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
## ddram:0.dq
set_property LOC R3 [get_ports ddram_dq[15]]
set_property SLEW FAST [get_ports ddram_dq[15]]
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]]
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
## ddram:0.dqs_p
set_property LOC N2 [get_ports ddram_dqs_p[0]]
set_property SLEW FAST [get_ports ddram_dqs_p[0]]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]]
## ddram:0.dqs_p
set_property LOC U2 [get_ports ddram_dqs_p[1]]
set_property SLEW FAST [get_ports ddram_dqs_p[1]]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]]
## ddram:0.dqs_n
set_property LOC N1 [get_ports ddram_dqs_n[0]]
set_property SLEW FAST [get_ports ddram_dqs_n[0]]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]]
## ddram:0.dqs_n
set_property LOC V2 [get_ports ddram_dqs_n[1]]
set_property SLEW FAST [get_ports ddram_dqs_n[1]]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]]
## ddram:0.clk_p
set_property LOC U9 [get_ports ddram_clk_p]
set_property SLEW FAST [get_ports ddram_clk_p]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
## ddram:0.clk_n
set_property LOC V9 [get_ports ddram_clk_n]
set_property SLEW FAST [get_ports ddram_clk_n]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
## ddram:0.cke
set_property LOC N5 [get_ports ddram_cke]
set_property SLEW FAST [get_ports ddram_cke]
set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
## ddram:0.odt
set_property LOC R5 [get_ports ddram_odt]
set_property SLEW FAST [get_ports ddram_odt]
set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
## ddram:0.reset_n
set_property LOC K6 [get_ports ddram_reset_n]
set_property SLEW FAST [get_ports ddram_reset_n]
set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
## eth_clocks:0.tx
set_property LOC H16 [get_ports eth_clocks_tx]
set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_tx]
## eth_clocks:0.rx
set_property LOC F15 [get_ports eth_clocks_rx]
set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_rx]
## eth:0.rst_n
set_property LOC C16 [get_ports eth_rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports eth_rst_n]
## eth:0.mdio
set_property LOC K13 [get_ports eth_mdio]
set_property IOSTANDARD LVCMOS33 [get_ports eth_mdio]
## eth:0.mdc
set_property LOC F16 [get_ports eth_mdc]
set_property IOSTANDARD LVCMOS33 [get_ports eth_mdc]
## eth:0.rx_dv
set_property LOC G16 [get_ports eth_rx_dv]
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_dv]
## eth:0.rx_er
set_property LOC C17 [get_ports eth_rx_er]
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_er]
## eth:0.rx_data
set_property LOC D18 [get_ports eth_rx_data[0]]
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[0]]
## eth:0.rx_data
set_property LOC E17 [get_ports eth_rx_data[1]]
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[1]]
## eth:0.rx_data
set_property LOC E18 [get_ports eth_rx_data[2]]
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[2]]
## eth:0.rx_data
set_property LOC G17 [get_ports eth_rx_data[3]]
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[3]]
## eth:0.tx_en
set_property LOC H15 [get_ports eth_tx_en]
set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_en]
## eth:0.tx_data
set_property LOC H14 [get_ports eth_tx_data[0]]
set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[0]]
## eth:0.tx_data
set_property LOC J14 [get_ports eth_tx_data[1]]
set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[1]]
## eth:0.tx_data
set_property LOC J13 [get_ports eth_tx_data[2]]
set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[2]]
## eth:0.tx_data
set_property LOC H17 [get_ports eth_tx_data[3]]
set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[3]]
## eth:0.col
set_property LOC D17 [get_ports eth_col]
set_property IOSTANDARD LVCMOS33 [get_ports eth_col]
## eth:0.crs
set_property LOC G14 [get_ports eth_crs]
set_property IOSTANDARD LVCMOS33 [get_ports eth_crs]
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
create_clock -name clk100 -period 10.0 [get_nets clk100]
create_clock -name eth_rx_clk -period 80.0 [get_nets eth_rx_clk]
create_clock -name eth_tx_clk -period 80.0 [get_nets eth_tx_clk]
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -asynchronous
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]

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minitests/litex_litedram/src.yosys/verilog/VexRiscv.v Normal file
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12447
minitests/litex_litedram/src.yosys/verilog/top.v Normal file
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