mirror of https://github.com/openXC7/prjxray.git
Added minitests for SRLs
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
ca6bbee193
commit
4c2b0a5395
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@ -0,0 +1,45 @@
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YOSYS = $(XRAY_DIR)/third_party/yosys/yosys
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PART = xc7a35tcsg324-1
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BIT2FASM_ARGS = --part "$(XRAY_DIR)/database/artix7/$(PART)" --verbose
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VERILOG_FILES = $(wildcard *.v)
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FASM_TARGETS = $(VERILOG_FILES:.v=.fasm)
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SEGPRINT_TARGETS = $(VERILOG_FILES:.v=.segprint.log)
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all: $(FASM_TARGETS) $(SEGPRINT_TARGETS)
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clean:
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@find . -name "build.*" | xargs rm -rf
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@rm -f *.edif
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@rm -f *.bit
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@rm -f *.bin
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@rm -f *.bits
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@rm -f *.fasm
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@rm -f *.log
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@rm -f *.dcp
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.PHONY: all clean
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$(YOSYS):
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cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc)
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%.edif: %.v $(YOSYS)
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$(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl -edif $@" -l $@.log
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%.bit: %.edif par.tcl
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mkdir -p build.$(basename $@)
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cd build.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../par.tcl -nojournal -log ../$@.log
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rm -rf *.backup.log
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%.fasm: %.bit
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PYTHONPATH="$(XRAY_DIR):$(XRAY_DIR)/utils:$(XRAY_DIR)/third_party/fasm" \
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PATH="$(XRAY_DIR)/build/tools:$(PATH)" \
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$(XRAY_BIT2FASM) $(BIT2FASM_ARGS) \
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$< >$@ \
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|| (rm -f $@ && exit 1)
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%.bits: %.bit
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$(XRAY_BITREAD) -part_file $(XRAY_DIR)/database/artix7/$(PART).yaml -o $@ -z -y $<
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%.segprint.log: %.bits
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$(XRAY_SEGPRINT) -z -D -b $< > $@
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@ -0,0 +1,5 @@
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# Minitests for SRLs
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This is a minitest for various SRL configurations.
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Uses Yosys to generate EDIF which is then P&R'd by Vivado. The makefile also invokes bit2fasm and segprint
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create_project -force -name $env(PROJECT_NAME) -part xc7a35ticsg324-1L
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#read_xdc ../top.xdc
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read_edif ../$env(PROJECT_NAME).edif
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link_design -part xc7a35ticsg324-1L
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report_timing_summary -file top_timing_synth.rpt
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report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
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report_utilization -file top_utilization_synth.rpt
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opt_design
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place_design
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report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
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report_utilization -file top_utilization_place.rpt
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report_io -file top_io.rpt
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report_control_sets -verbose -file top_control_sets.rpt
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report_clock_utilization -file top_clock_utilization.rpt
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route_design
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#phys_opt_design
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report_timing_summary -no_header -no_detailed_paths
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write_checkpoint -force ../$env(PROJECT_NAME).dcp
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set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
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set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
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report_route_status -file top_route_status.rpt
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report_drc -file top_drc.rpt
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report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
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report_power -file top_power.rpt
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write_bitstream -force ../$env(PROJECT_NAME).bit
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module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [4:0] A,
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output wire Q
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);
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(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
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SRLC32E #
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(
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.INIT(32'hF0F01030)
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)
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srl_a
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q)
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);
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endmodule
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@ -0,0 +1,21 @@
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module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [4:0] A,
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output wire Q
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);
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(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
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SRLC32E srl_a
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q)
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);
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endmodule
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module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [4:0] A,
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output wire [1:0] Q
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);
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(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
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SRLC32E srl_a
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[0])
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);
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(* LOC="SLICE_X2Y0", BEL="B6LUT" *)
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SRLC32E srl_b
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[1])
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);
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endmodule
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@ -0,0 +1,33 @@
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module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [4:0] A,
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output wire Q
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);
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wire q31_d;
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(* LOC="SLICE_X2Y0", BEL="D6LUT" *)
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SRLC32E srl_d
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q31 (q31_d)
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);
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(* LOC="SLICE_X2Y0", BEL="C6LUT" *)
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SRLC32E srl_c
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(
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.CLK (CLK),
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.CE (CE),
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.D (q31_d),
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.A (A),
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.Q (Q)
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);
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endmodule
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@ -0,0 +1,41 @@
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module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [4:0] A,
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output wire [2:0] Q
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);
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(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
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SRLC32E srl_a
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[0])
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);
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(* LOC="SLICE_X2Y0", BEL="B6LUT" *)
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SRLC32E srl_b
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[1])
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);
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(* LOC="SLICE_X2Y0", BEL="C6LUT" *)
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SRLC32E srl_c
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[2])
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);
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endmodule
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@ -0,0 +1,44 @@
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module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [4:0] A,
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output wire Q
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);
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wire q31_d;
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wire q31_c;
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(* LOC="SLICE_X2Y0", BEL="D6LUT" *)
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SRLC32E srl_d
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q31 (q31_d)
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);
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(* LOC="SLICE_X2Y0", BEL="C6LUT" *)
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SRLC32E srl_c
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(
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.CLK (CLK),
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.CE (CE),
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.D (q31_d),
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.A (A),
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.Q31 (q31_c)
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);
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(* LOC="SLICE_X2Y0", BEL="B6LUT" *)
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SRLC32E srl_b
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(
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.CLK (CLK),
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.CE (CE),
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.D (q31_c),
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.A (A),
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.Q (Q)
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);
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endmodule
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@ -0,0 +1,51 @@
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module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [4:0] A,
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output wire [3:0] Q
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);
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(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
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SRLC32E srl_a
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[0])
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);
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(* LOC="SLICE_X2Y0", BEL="B6LUT" *)
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SRLC32E srl_b
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[1])
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);
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(* LOC="SLICE_X2Y0", BEL="C6LUT" *)
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SRLC32E srl_c
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[2])
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);
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(* LOC="SLICE_X2Y0", BEL="D6LUT" *)
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SRLC32E srl_d
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[3])
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);
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endmodule
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@ -0,0 +1,55 @@
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module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [4:0] A,
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output wire Q
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);
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wire q31_d;
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wire q31_c;
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wire q31_b;
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(* LOC="SLICE_X2Y0", BEL="D6LUT" *)
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SRLC32E srl_d
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q31 (q31_d)
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);
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(* LOC="SLICE_X2Y0", BEL="C6LUT" *)
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SRLC32E srl_c
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(
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.CLK (CLK),
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.CE (CE),
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.D (q31_d),
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.A (A),
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.Q31 (q31_c)
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);
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(* LOC="SLICE_X2Y0", BEL="B6LUT" *)
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SRLC32E srl_b
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(
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.CLK (CLK),
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.CE (CE),
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.D (q31_c),
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.A (A),
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.Q (q31_b)
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);
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(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
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SRLC32E srl_a
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(
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.CLK (CLK),
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.CE (CE),
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.D (q31_b),
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.A (A),
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.Q (Q)
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);
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endmodule
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