mirror of https://github.com/openXC7/prjxray.git
iob minitest: sweep misc parameters
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
661615a40a
commit
3fa5df7cb1
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@ -0,0 +1,9 @@
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source "$::env(SRC_DIR)/template.tcl"
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# set vals "0 4 8 12 16 24"
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# ERROR: [Common 17-69] Command failed: Illegal DRIVE_STRENGTH value '0' for standard 'LVCMOS33'.
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# Legal values: 4, 8, 12, 16
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set prop DRIVE
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set port [get_ports do]
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source "$::env(SRC_DIR)/sweep.tcl"
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@ -0,0 +1,6 @@
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source "$::env(SRC_DIR)/template.tcl"
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set prop IOSTANDARD
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set port [get_ports do]
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source "$::env(SRC_DIR)/sweep.tcl"
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@ -1,4 +1,9 @@
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all: build/env build/roi_roi_io.diff
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all: build/env build/roi_roi_io.diff \
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build/PULLTYPE/run.ok \
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build/SLEW/run.ok \
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build/DRIVE/run.ok \
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build/IOSTANDARD/run.ok \
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clean:
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rm -rf build
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@ -10,4 +15,18 @@ build/env:
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build/roi_roi_io.diff:
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$(MAKE) -f diff.mk OUT_DIFF=build/roi_io.diff PRJL=roi_io_a PRJR=roi_io_b
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build/PULLTYPE/run.ok:
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PROJECT=PULLTYPE bash runme_tcl.sh
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diff build/PULLTYPE/design_{PULLDOWN,KEEPER}.bits || true
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diff build/PULLTYPE/design_{PULLDOWN,PULLUP}.bits || true
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diff build/PULLTYPE/design_{PULLDOWN,NONE}.bits || true
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build/SLEW/run.ok:
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PROJECT=SLEW bash runme_tcl.sh
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build/DRIVE/run.ok:
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PROJECT=DRIVE bash runme_tcl.sh
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build/IOSTANDARD/run.ok:
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PROJECT=IOSTANDARD bash runme_tcl.sh
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@ -0,0 +1,15 @@
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source "$::env(SRC_DIR)/template.tcl"
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set port [get_ports di]
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set_property PULLTYPE "" $port
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write_checkpoint -force design_NONE.dcp
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write_bitstream -force design_NONE.bit
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set vals "KEEPER PULLUP PULLDOWN"
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foreach {val} $vals {
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set_property PULLTYPE $val $port
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write_checkpoint -force design_$val.dcp
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write_bitstream -force design_$val.bit
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}
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@ -0,0 +1,39 @@
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# PULLTYPE
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PULLTYPE 28 29 30
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NONE X
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KEEPER X X
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PULLDOWN
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PULLUP X X
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# DRIVE
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DRIVE A00 A02 A08 A10 B09 B01
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0 FIXME
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4 X X X
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8 X X X
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12 X X X
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16 X X X
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24 FIXME
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# IOSTANDARD
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Effects bits, TBD exactly how
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Sample output:
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diff LVCMOS33.bits LVTTL.bits
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< bit_00020026_006_00
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> bit_00020026_006_08
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diff LVCMOS33.bits PCI33_3.bits
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< bit_00020026_006_02
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< bit_00020026_006_18
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< bit_00020026_006_22
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> bit_00020026_006_10
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> bit_00020026_006_16
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> bit_00020026_006_20
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> bit_00020027_006_11
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> bit_00020027_006_15
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@ -0,0 +1,8 @@
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source "$::env(SRC_DIR)/template.tcl"
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# set vals "SLOW MEDIUM FAST"
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# ERROR: [Common 17-69] Command failed: Slew type 'MEDIUM' is not supported by I/O standard 'LVCMOS33'
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set prop SLEW
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set port [get_ports do]
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source "$::env(SRC_DIR)/sweep.tcl"
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@ -0,0 +1,11 @@
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all: $(OUT_DIFF)
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$(OUT_DIFF): build/$(PRJL)/design.bits build/$(PRJR)/design.bits
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diff build/$(PRJL)/design.bits build/$(PRJR)/design.bits >$(OUT_DIFF) || true
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build/$(PRJL)/design.bits:
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PROJECT=$(PRJL) bash runme_tcl.sh
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build/$(PRJR)/design.bits:
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PROJECT=$(PRJR) bash runme_tcl.sh
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@ -0,0 +1,21 @@
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#!/bin/bash
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set -ex
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: "${PROJECT:?Need to set PROJECT non-empty}"
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# Create build dir
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export SRC_DIR=$PWD
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BUILD_DIR=build/$PROJECT
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mkdir -p $BUILD_DIR
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cd $BUILD_DIR
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export TOP_V=$SRC_DIR/tcl.v
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vivado -mode batch -source $SRC_DIR/$PROJECT.tcl
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for x in design*.bit; do
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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test -z "$(fgrep CRITICAL vivado.log)"
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touch run.ok
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# Sweep all values of $prop on given I/O $port
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# Write out bitstream for all legal values
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set vals [list_property_value $prop $port]
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foreach {val} $vals {
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puts $val
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# Not all listable properties are settable
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# Its easiest to try setting and see if it sticks
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set_property -quiet $prop $val $port
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set got [get_property $prop $port]
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if {"$got" != "$val"} {
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puts " Skipping: wanted $val, got $got"
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continue
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}
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if {[catch {write_bitstream -force design_$val.bit} issue]} {
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puts "WARNING failed to write: $issue"
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continue
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}
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# Only write checkpoints for acceptable bitstreams
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write_checkpoint -force design_$val.dcp
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}
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@ -0,0 +1,39 @@
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 256;
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localparam integer DOUT_N = 256;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi
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roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [255:0] din, output [255:0] dout);
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assign dout = din;
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endmodule
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/*
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module top (input i, output o);
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assign o = i;
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endmodule
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*/
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@ -0,0 +1,20 @@
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# Create a simple design with a few IOs
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(TOP_V)
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synth_design -top top -flatten_hierarchy none
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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