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Updated EDIF write to include cell attributes 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-07-02 16:03:02 +02:00
parent 4d6f75e8ad
commit cbbf46112f
1 changed files with 1 additions and 1 deletions
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2
minitests/srl/Makefile
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@ -30,7 +30,7 @@ $(YOSYS):
ifeq ($(SYNTH), yosys)
%.edif: %.v $(YOSYS)
$(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl -edif $@" -l $@.log
$(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl; write_edif -pvector bra -attrprop $@" -l $@.log
else ifeq ($(SYNTH), vivado)
%.edif: %.v $(YOSYS)